mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 02:48:37 +02:00
[atheros] nuke trailing whitespaces
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10872 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg
parent
4668cb8663
commit
dd4dcd736d
@ -56,7 +56,7 @@ asmlinkage void ar5312_irq_dispatch(void)
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} else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
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do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
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else if (ar531x_misc_intrs & AR531X_ISR_GPIO)
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ar5312_gpio_irq_dispatch();
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ar5312_gpio_irq_dispatch();
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else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
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do_IRQ(AR531X_MISC_IRQ_UART0);
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else if (ar531x_misc_intrs & AR531X_ISR_WD)
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@ -140,7 +140,7 @@ static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
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printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
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procAddr, proc1, dmaAddr, dma1);
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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@ -89,7 +89,7 @@ static void ar5315_gpio_intr_enable(unsigned int irq)
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/* reconfigure GPIO line as input */
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sysRegMask(AR5315_GPIO_CR, AR5315_GPIO_CR_M(gpio), AR5315_GPIO_CR_I(gpio));
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/* Enable interrupt with edge detection */
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sysRegMask(AR5315_GPIO_INT, AR5315_GPIO_INT_M | AR5315_GPIO_INT_LVL_M, gpio | AR5315_GPIO_INT_LVL(3));
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}
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@ -203,7 +203,7 @@ ar5315_misc_intr_disable(unsigned int irq)
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case AR531X_MISC_IRQ_SPI:
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imr &= ~AR5315_ISR_SPI;
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break;
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case AR531X_MISC_IRQ_TIMER:
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imr &= (~AR5315_ISR_TIMER);
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break;
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@ -51,7 +51,7 @@ static u8 *find_board_config(char *flash_limit)
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printk("WARNING: No board configuration data found!\n");
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addr = NULL;
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}
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return addr;
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}
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@ -59,8 +59,8 @@ static u8 *find_radio_config(char *flash_limit, char *board_config)
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{
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int dataFound;
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u32 radio_config;
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/*
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/*
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* Now find the start of Radio Configuration data, using heuristics:
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* Search forward from Board Configuration data by 0x1000 bytes
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* at a time until we find non-0xffffffff.
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@ -123,14 +123,14 @@ int __init ar531x_find_config(char *flash_limit)
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printk("Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, radio_config - board_config);
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rcfg_size = BOARD_CONFIG_BUFSZ - ((rcfg - bcfg) & (BOARD_CONFIG_BUFSZ - 1));
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memcpy(radio_config, rcfg, rcfg_size);
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return 0;
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}
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void __init serial_setup(unsigned long mapbase, unsigned int uartclk)
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{
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struct uart_port s;
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memset(&s, 0, sizeof(s));
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s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
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@ -162,7 +162,7 @@ const char *get_system_type(void)
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case MACH_ATHEROS_AR2312:
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return "Atheros AR2312";
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case MACH_ATHEROS_AR2313:
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return "Atheros AR2313";
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#endif
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@ -225,7 +225,7 @@ static int __init ar531x_register_gpiodev(void)
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struct platform_device *pdev;
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printk(KERN_INFO "ar531x: Registering GPIODEV device\n");
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pdev = platform_device_register_simple("GPIODEV", 0, &res, 1);
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if (!pdev) {
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@ -27,7 +27,7 @@
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#include <asm/irq_cpu.h>
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#include <asm/gpio.h>
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#include "ar531x.h"
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/*
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/*
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GPIO Interrupt Support
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Make use of request_irq() and the function gpio_to_irq() to trap gpio events
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*/
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@ -147,7 +147,7 @@ static void ar5315_gpio_intr_enable(unsigned int irq) {
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sysRegWrite(AR5315_GPIO_CR, reg);
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(void)sysRegRead(AR5315_GPIO_CR); /* flush write to hardware */
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/* Locate a free register slot to enable gpio intr
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/* Locate a free register slot to enable gpio intr
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will fail silently if no more slots are available
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*/
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reg = sysRegRead(AR5315_GPIO_INT);
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@ -35,7 +35,7 @@ void __init prom_init(void)
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DO_AR5315(ar5315_prom_init();)
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#if 0
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argv = (char **)fw_arg1;
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/* RedBoot desired command line is argv[1] */
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/* RedBoot desired command line is argv[1] */
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strcat(arcs_cmdline, argv[1]);
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#endif
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}
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@ -37,7 +37,7 @@ static void hotplug_button(struct work_struct *wq)
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size_t len;
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char *scratch, *s;
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char buf[128];
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event = container_of(wq, struct event_t, wq);
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if (!uevent_sock)
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goto done;
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@ -48,7 +48,7 @@ static void hotplug_button(struct work_struct *wq)
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skb = alloc_skb(len + 2048, GFP_KERNEL);
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if (!skb)
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goto done;
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/* add header */
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scratch = skb_put(skb, len);
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sprintf(scratch, "%s@",s);
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@ -80,7 +80,7 @@ static irqreturn_t button_handler(int irq, void *dev_id)
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event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
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if (!event)
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return IRQ_NONE;
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pressed = !pressed;
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DO_AR5315(gpio = sysRegRead(AR5315_GPIO_DI);)
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@ -99,7 +99,7 @@ static irqreturn_t button_handler(int irq, void *dev_id)
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void ar531x_disable_reset_button(void)
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{
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disable_irq(AR531X_RESET_GPIO_IRQ);
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disable_irq(AR531X_RESET_GPIO_IRQ);
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}
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EXPORT_SYMBOL(ar531x_disable_reset_button);
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@ -109,7 +109,7 @@ int __init ar531x_init_reset(void)
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bcfg = (struct ar531x_boarddata *) board_config;
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seen = jiffies;
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request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar531x_reset", NULL);
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return 0;
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@ -69,7 +69,7 @@
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spin_lock_bh(&spidata->mutex); \
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} \
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} while (0)
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static __u32 spiflash_regread32(int reg);
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static void spiflash_regwrite32(int reg, __u32 data);
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@ -132,7 +132,7 @@ struct opcodes {
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/* Driver private data structure */
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struct spiflash_data {
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struct mtd_info *mtd;
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struct mtd_info *mtd;
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struct mtd_partition *parsed_parts; /* parsed partitions */
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void *readaddr; /* memory mapped data for read */
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void *mmraddr; /* memory mapped register space */
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@ -161,7 +161,7 @@ spiflash_regread32(int reg)
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return (*data);
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}
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static void
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static void
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spiflash_regwrite32(int reg, __u32 data)
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{
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volatile __u32 *addr = (__u32 *)(spidata->mmraddr + reg);
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@ -171,7 +171,7 @@ spiflash_regwrite32(int reg, __u32 data)
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}
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static __u32
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static __u32
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spiflash_sendcmd (int op, u32 addr)
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{
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u32 reg;
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@ -187,7 +187,7 @@ spiflash_sendcmd (int op, u32 addr)
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spiflash_regwrite32(SPI_FLASH_CTL, reg);
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busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);
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if (!ptr_opcode->rx_cnt)
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return 0;
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@ -218,12 +218,12 @@ spiflash_sendcmd (int op, u32 addr)
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* Function returns 0 for failure.
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* and flashconfig_tbl array index for success.
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*/
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static int
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static int
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spiflash_probe_chip (void)
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{
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__u32 sig;
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int flash_size;
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/* Read the signature on the flash device */
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spin_lock_bh(&spidata->mutex);
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sig = spiflash_sendcmd(SPI_RD_SIG, 0);
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@ -267,7 +267,7 @@ retry:
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spin_unlock_bh(&spidata->mutex);
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schedule();
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remove_wait_queue(&spidata->wq, &wait);
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if(signal_pending(current))
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return 0;
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@ -285,7 +285,7 @@ static inline void spiflash_done(void)
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wake_up(&spidata->wq);
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}
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static int
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static int
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spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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{
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struct opcodes *ptr_opcode;
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@ -312,7 +312,7 @@ spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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spin_unlock_bh(&spidata->mutex);
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msleep(800);
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spin_lock_bh(&spidata->mutex);
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busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
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spiflash_done();
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@ -322,15 +322,15 @@ spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
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return 0;
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}
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static int
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static int
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spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
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{
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u8 *read_addr;
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/* sanity checks */
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if (!len) return (0);
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if (from + len > mtd->size) return (-EINVAL);
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/* we always read len bytes */
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*retlen = len;
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@ -343,7 +343,7 @@ spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_cha
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return 0;
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}
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static int
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static int
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spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
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{
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u32 opcode, bytes_left;
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@ -353,10 +353,10 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
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/* sanity checks */
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if (!len) return (0);
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if (to + len > mtd->size) return (-EINVAL);
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opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
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bytes_left = len;
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do {
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u32 xact_len, reg, page_offset, spi_data = 0;
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@ -389,7 +389,7 @@ spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u
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spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
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break;
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case 4:
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spi_data = (buf[3] << 24) | (buf[2] << 16) |
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spi_data = (buf[3] << 24) | (buf[2] << 16) |
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(buf[1] << 8) | buf[0];
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break;
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default:
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@ -439,7 +439,7 @@ static int spiflash_probe(struct platform_device *pdev)
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spin_lock_init(&spidata->mutex);
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init_waitqueue_head(&spidata->wq);
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spidata->state = FL_READY;
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if (!spidata->mmraddr) {
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printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
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kfree(spidata);
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@ -451,7 +451,7 @@ static int spiflash_probe(struct platform_device *pdev)
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kfree(spidata);
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return -ENXIO;
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}
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if (!(index = spiflash_probe_chip())) {
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printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
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goto error;
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@ -483,9 +483,9 @@ static int spiflash_probe(struct platform_device *pdev)
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result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
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spidata->mtd = mtd;
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return (result);
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error:
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kfree(mtd);
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kfree(spidata);
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@ -505,7 +505,7 @@ struct platform_driver spiflash_driver = {
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.remove = spiflash_remove,
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};
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int __init
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int __init
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spiflash_init (void)
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{
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spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
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@ -518,7 +518,7 @@ spiflash_init (void)
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return 0;
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}
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void __exit
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void __exit
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spiflash_exit (void)
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{
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kfree(spidata);
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@ -14,7 +14,7 @@
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* (at your option) any later version.
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*
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* Additional credits:
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* This code is taken from John Taylor's Sibyte driver and then
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* This code is taken from John Taylor's Sibyte driver and then
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* modified for the AR2313.
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*/
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@ -134,7 +134,7 @@
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#define CRC_LEN 4
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#define RX_OFFSET 2
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
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#define VLAN_HDR 4
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#else
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#define VLAN_HDR 0
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@ -232,8 +232,8 @@ int __init ar2313_probe(struct platform_device *pdev)
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return (-ENXIO);
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}
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/*
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* When there's only one MAC, PHY regs are typically on ENET0,
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/*
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* When there's only one MAC, PHY regs are typically on ENET0,
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* even though the MAC might be on ENET1.
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* Needto remap PHY regs separately in this case
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*/
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@ -270,7 +270,7 @@ int __init ar2313_probe(struct platform_device *pdev)
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sp->board_idx = BOARD_IDX_STATIC;
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if (ar2313_init(dev)) {
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/*
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/*
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* ar2313_init() calls ar2313_init_cleanup() on error.
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*/
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kfree(dev);
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@ -295,7 +295,7 @@ int __init ar2313_probe(struct platform_device *pdev)
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sp->mii_bus.id = 0;
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sp->mii_bus.irq = kmalloc(sizeof(int), GFP_KERNEL);
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*sp->mii_bus.irq = PHY_POLL;
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mdiobus_register(&sp->mii_bus);
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if (mdiobus_probe(dev) != 0) {
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@ -308,7 +308,7 @@ int __init ar2313_probe(struct platform_device *pdev)
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/* start link poll timer */
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ar2313_setup_timer(dev);
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}
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return 0;
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}
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@ -379,9 +379,9 @@ static void printMcList(struct net_device *dev)
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*/
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static void ar2313_multicast_list(struct net_device *dev)
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{
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/*
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* Always listen to broadcasts and
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* treat IFF bits independently
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/*
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* Always listen to broadcasts and
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* treat IFF bits independently
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*/
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struct ar2313_private *sp = (struct ar2313_private *) dev->priv;
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unsigned int recognise;
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@ -420,7 +420,7 @@ static void rx_tasklet_cleanup(struct net_device *dev)
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{
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struct ar2313_private *sp = dev->priv;
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/*
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/*
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* Tasklet may be scheduled. Need to get it removed from the list
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* since we're about to free the struct.
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*/
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@ -442,7 +442,7 @@ static int __exit ar2313_remove(struct platform_device *pdev)
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/*
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* Restart the AR2313 ethernet controller.
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* Restart the AR2313 ethernet controller.
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*/
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static int ar2313_restart(struct net_device *dev)
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{
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@ -606,7 +606,7 @@ static void ar2313_link_timer_fn(unsigned long data)
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// autonegotiated value of half or full duplex.
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ar2313_check_link(dev);
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// Loop faster when we don't have link.
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// Loop faster when we don't have link.
|
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// This was needed to speed up the AP bootstrap time.
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if (sp->link == 0) {
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mod_timer(&sp->link_timer, jiffies + HZ / 2);
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@ -728,7 +728,7 @@ static int ar2313_init(struct net_device *dev)
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struct ar2313_private *sp = dev->priv;
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int ecode = 0;
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/*
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/*
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* Allocate descriptors
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*/
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if (ar2313_allocate_descriptors(dev)) {
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@ -738,7 +738,7 @@ static int ar2313_init(struct net_device *dev)
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goto init_error;
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* Get the memory for the skb rings.
|
||||
*/
|
||||
if (sp->rx_skb == NULL) {
|
||||
@ -767,7 +767,7 @@ static int ar2313_init(struct net_device *dev)
|
||||
}
|
||||
memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Set tx_csm before we start receiving interrupts, otherwise
|
||||
* the interrupt handler might think it is supposed to process
|
||||
* tx ints before we are up and running, which may cause a null
|
||||
@ -778,23 +778,23 @@ static int ar2313_init(struct net_device *dev)
|
||||
sp->tx_prd = 0;
|
||||
sp->tx_csm = 0;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Zero the stats before starting the interface
|
||||
*/
|
||||
memset(&sp->stats, 0, sizeof(sp->stats));
|
||||
|
||||
/*
|
||||
/*
|
||||
* We load the ring here as there seem to be no way to tell the
|
||||
* firmware to wipe the ring without re-initializing it.
|
||||
*/
|
||||
ar2313_load_rx_ring(dev, RX_RING_SIZE);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Init hardware
|
||||
*/
|
||||
ar2313_reset_reg(dev);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Get the IRQ
|
||||
*/
|
||||
ecode =
|
||||
@ -852,7 +852,7 @@ static void ar2313_load_rx_ring(struct net_device *dev, int nr_bufs)
|
||||
// partha: create additional room in the front for tx pkt capture
|
||||
skb_reserve(skb, 32);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Make sure IP header starts on a fresh cache line.
|
||||
*/
|
||||
skb->dev = dev;
|
||||
@ -899,7 +899,7 @@ static int ar2313_rx_int(struct net_device *dev)
|
||||
|
||||
idx = sp->cur_rx;
|
||||
|
||||
/* process at most the entire ring and then wait for another interrupt
|
||||
/* process at most the entire ring and then wait for another interrupt
|
||||
*/
|
||||
while (1) {
|
||||
|
||||
@ -1081,7 +1081,7 @@ static irqreturn_t ar2313_interrupt(int irq, void *dev_id)
|
||||
unsigned int status, enabled;
|
||||
|
||||
/* clear interrupt */
|
||||
/*
|
||||
/*
|
||||
* Don't clear RI bit if currently disabled.
|
||||
*/
|
||||
status = sp->dma_regs->status;
|
||||
@ -1090,7 +1090,7 @@ static irqreturn_t ar2313_interrupt(int irq, void *dev_id)
|
||||
|
||||
if (status & DMA_STATUS_NIS) {
|
||||
/* normal status */
|
||||
/*
|
||||
/*
|
||||
* Don't schedule rx processing if interrupt
|
||||
* is already disabled.
|
||||
*/
|
||||
@ -1178,12 +1178,12 @@ static void ar2313_halt(struct net_device *dev)
|
||||
static int ar2313_close(struct net_device *dev)
|
||||
{
|
||||
#if 0
|
||||
/*
|
||||
/*
|
||||
* Disable interrupts
|
||||
*/
|
||||
disable_irq(dev->irq);
|
||||
|
||||
/*
|
||||
/*
|
||||
* Without (or before) releasing irq and stopping hardware, this
|
||||
* is an absolute non-sense, by the way. It will be reset instantly
|
||||
* by the first irq.
|
||||
@ -1251,7 +1251,7 @@ static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
|
||||
struct ar2313_private *sp = dev->priv;
|
||||
int ret;
|
||||
|
||||
|
||||
switch (cmd) {
|
||||
|
||||
case SIOCETHTOOL:
|
||||
@ -1271,12 +1271,12 @@ static int ar2313_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
|
||||
return -EFAULT;
|
||||
return 0;
|
||||
|
||||
|
||||
case SIOCGMIIPHY:
|
||||
case SIOCGMIIREG:
|
||||
case SIOCSMIIREG:
|
||||
return phy_mii_ioctl(sp->phy_dev, data, cmd);
|
||||
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -1314,7 +1314,7 @@ static void ar2313_adjust_link(struct net_device *dev)
|
||||
#define MII_ADDR(phy, reg) \
|
||||
((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
|
||||
|
||||
static int
|
||||
static int
|
||||
mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
|
||||
{
|
||||
struct net_device *const dev = bus->priv;
|
||||
@ -1326,7 +1326,7 @@ mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
|
||||
return (ethernet->mii_data >> MII_DATA_SHIFT);
|
||||
}
|
||||
|
||||
static int
|
||||
static int
|
||||
mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
|
||||
u16 value)
|
||||
{
|
||||
|
||||
@ -64,7 +64,7 @@ typedef struct {
|
||||
} ETHERNET_STRUCT;
|
||||
|
||||
/********************************************************************
|
||||
* Interrupt controller
|
||||
* Interrupt controller
|
||||
********************************************************************/
|
||||
|
||||
typedef struct {
|
||||
@ -118,7 +118,7 @@ struct ar2313_private {
|
||||
|
||||
spinlock_t lock; /* Serialise access to device */
|
||||
|
||||
/*
|
||||
/*
|
||||
* RX and TX descriptors, must be adjacent
|
||||
*/
|
||||
ar2313_descr_t *rx_ring;
|
||||
@ -128,19 +128,19 @@ struct ar2313_private {
|
||||
struct sk_buff **rx_skb;
|
||||
struct sk_buff **tx_skb;
|
||||
|
||||
/*
|
||||
/*
|
||||
* RX elements
|
||||
*/
|
||||
u32 rx_skbprd;
|
||||
u32 cur_rx;
|
||||
|
||||
/*
|
||||
/*
|
||||
* TX elements
|
||||
*/
|
||||
u32 tx_prd;
|
||||
u32 tx_csm;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Misc elements
|
||||
*/
|
||||
int board_idx;
|
||||
|
||||
@ -16,13 +16,13 @@
|
||||
* $Log: dma.h,v $
|
||||
* Revision 1.3 2002/06/06 18:34:03 astichte
|
||||
* Added XXX_PhysicalAddress and XXX_VirtualAddress
|
||||
*
|
||||
*
|
||||
* Revision 1.2 2002/06/05 18:30:46 astichte
|
||||
* Removed IDTField
|
||||
*
|
||||
*
|
||||
* Revision 1.1 2002/05/29 17:33:21 sysarch
|
||||
* jba File moved from vcode/include/idt/acacia
|
||||
*
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
@ -53,7 +53,7 @@
|
||||
#define AR531X_RADIO_MASK_OFF 0xc8
|
||||
#define AR531X_RADIO0_MASK 0x0003
|
||||
#define AR531X_RADIO1_MASK 0x000c
|
||||
#define AR531X_RADIO1_S 2
|
||||
#define AR531X_RADIO1_S 2
|
||||
|
||||
/*
|
||||
* AR531X_NUM_WMAC defines the number of Wireless MACs that\
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#ifndef AR5315_H
|
||||
#define AR5315_H
|
||||
|
||||
/*
|
||||
/*
|
||||
* IRQs
|
||||
*/
|
||||
#define AR5315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
|
||||
@ -106,7 +106,7 @@
|
||||
#define AR5315_CONFIG_CPU_DRAM 0x00010000
|
||||
#define AR5315_CONFIG_CPU_PCI 0x00020000
|
||||
#define AR5315_CONFIG_CPU_MMR 0x00040000
|
||||
#define AR5315_CONFIG_BIG 0x00000400
|
||||
#define AR5315_CONFIG_BIG 0x00000400
|
||||
|
||||
|
||||
/*
|
||||
@ -141,13 +141,13 @@
|
||||
#define IF_PCI_HOST 0x00000010
|
||||
#define IF_PCI_INTR 0x00000020
|
||||
#define IF_PCI_CLK_MASK 0x00030000
|
||||
#define IF_PCI_CLK_INPUT 0
|
||||
#define IF_PCI_CLK_INPUT 0
|
||||
#define IF_PCI_CLK_OUTPUT_LOW 1
|
||||
#define IF_PCI_CLK_OUTPUT_CLK 2
|
||||
#define IF_PCI_CLK_OUTPUT_HIGH 3
|
||||
#define IF_PCI_CLK_SHIFT 16
|
||||
|
||||
|
||||
#define IF_PCI_CLK_SHIFT 16
|
||||
|
||||
|
||||
/* Major revision numbers, bits 7..4 of Revision ID register */
|
||||
#define REV_MAJ_AR5311 0x01
|
||||
#define REV_MAJ_AR5312 0x04
|
||||
@ -170,7 +170,7 @@
|
||||
#define AR5315_ISR_GPIO 0x0040 /* GPIO */
|
||||
#define AR5315_ISR_WD 0x0080 /* watchdog */
|
||||
#define AR5315_ISR_IR_RSVD 0x0100 /* IR */
|
||||
|
||||
|
||||
#define AR5315_GISR_MISC 0x0001
|
||||
#define AR5315_GISR_WLAN0 0x0002
|
||||
#define AR5315_GISR_MPEGTS_RSVD 0x0004
|
||||
@ -215,7 +215,7 @@
|
||||
#define PERF_ACTIVE 0x0010 /* Count Active Processor Cycles */
|
||||
#define PERF_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
|
||||
#define PERF_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
|
||||
|
||||
|
||||
#define PERF_EB_ARDY 0x0001 /* Count EB_ARdy signal */
|
||||
#define PERF_EB_AVALID 0x0002 /* Count EB_AValid signal */
|
||||
#define PERF_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
|
||||
@ -246,7 +246,7 @@
|
||||
#define PROCERR_HMAST_LOCAL 4
|
||||
#define PROCERR_HMAST_CPU 5
|
||||
#define PROCERR_HMAST_PCITGT 6
|
||||
|
||||
|
||||
#define PROCERR_HMAST_S 0
|
||||
#define PROCERR_HWRITE 0x00000010
|
||||
#define PROCERR_HSIZE 0x00000060
|
||||
@ -325,7 +325,7 @@
|
||||
*/
|
||||
#define ASSOC_STATUS_M 0x00000003
|
||||
#define ASSOC_STATUS_NONE 0
|
||||
#define ASSOC_STATUS_PENDING 1
|
||||
#define ASSOC_STATUS_PENDING 1
|
||||
#define ASSOC_STATUS_ASSOCIATED 2
|
||||
#define LED_MODE_M 0x0000001c
|
||||
#define LED_BLINK_THRESHOLD_M 0x000000e0
|
||||
@ -358,28 +358,28 @@
|
||||
#define AR5315_RESET_GPIO 5
|
||||
#define AR5315_NUM_GPIO 22
|
||||
|
||||
|
||||
/*
|
||||
|
||||
/*
|
||||
* PCI Clock Control
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
#define AR5315_PCICLK (AR5315_DSLBASE + 0x00a4)
|
||||
|
||||
#define AR5315_PCICLK_INPUT_M 0x3
|
||||
#define AR5315_PCICLK_INPUT_S 0
|
||||
|
||||
|
||||
#define AR5315_PCICLK_PLLC_CLKM 0
|
||||
#define AR5315_PCICLK_PLLC_CLKM1 1
|
||||
#define AR5315_PCICLK_PLLC_CLKC 2
|
||||
#define AR5315_PCICLK_REF_CLK 3
|
||||
#define AR5315_PCICLK_REF_CLK 3
|
||||
|
||||
#define AR5315_PCICLK_DIV_M 0xc
|
||||
#define AR5315_PCICLK_DIV_S 2
|
||||
|
||||
|
||||
#define AR5315_PCICLK_IN_FREQ 0
|
||||
#define AR5315_PCICLK_IN_FREQ_DIV_6 1
|
||||
#define AR5315_PCICLK_IN_FREQ_DIV_8 2
|
||||
#define AR5315_PCICLK_IN_FREQ_DIV_10 3
|
||||
#define AR5315_PCICLK_IN_FREQ_DIV_10 3
|
||||
|
||||
/*
|
||||
* Observation Control Register
|
||||
@ -389,10 +389,10 @@
|
||||
#define OCR_GPIO1_IROUT 0x0080
|
||||
#define OCR_GPIO3_RXCLR 0x0200
|
||||
|
||||
/*
|
||||
/*
|
||||
* General Clock Control
|
||||
*/
|
||||
|
||||
*/
|
||||
|
||||
#define AR5315_MISCCLK (AR5315_DSLBASE + 0x00b4)
|
||||
#define MISCCLK_PLLBYPASS_EN 0x00000001
|
||||
#define MISCCLK_PROCREFCLK 0x00000002
|
||||
@ -435,10 +435,10 @@
|
||||
#define SPI_CTL_CLK_SEL_MASK 0x03000000
|
||||
#define SPI_OPCODE_MASK 0x000000ff
|
||||
|
||||
/*
|
||||
* PCI-MAC Configuration registers
|
||||
/*
|
||||
* PCI-MAC Configuration registers
|
||||
*/
|
||||
#define PCI_MAC_RC (AR5315_PCI + 0x4000)
|
||||
#define PCI_MAC_RC (AR5315_PCI + 0x4000)
|
||||
#define PCI_MAC_SCR (AR5315_PCI + 0x4004)
|
||||
#define PCI_MAC_INTPEND (AR5315_PCI + 0x4008)
|
||||
#define PCI_MAC_SFR (AR5315_PCI + 0x400C)
|
||||
@ -449,16 +449,16 @@
|
||||
#define PCI_MAC_RC_BB 0x00000002
|
||||
|
||||
#define PCI_MAC_SCR_SLMODE_M 0x00030000
|
||||
#define PCI_MAC_SCR_SLMODE_S 16
|
||||
#define PCI_MAC_SCR_SLM_FWAKE 0
|
||||
#define PCI_MAC_SCR_SLM_FSLEEP 1
|
||||
#define PCI_MAC_SCR_SLM_NORMAL 2
|
||||
#define PCI_MAC_SCR_SLMODE_S 16
|
||||
#define PCI_MAC_SCR_SLM_FWAKE 0
|
||||
#define PCI_MAC_SCR_SLM_FSLEEP 1
|
||||
#define PCI_MAC_SCR_SLM_NORMAL 2
|
||||
|
||||
#define PCI_MAC_SFR_SLEEP 0x00000001
|
||||
|
||||
#define PCI_MAC_PCICFG_SPWR_DN 0x00010000
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* PCI Bus Interface Registers
|
||||
*/
|
||||
@ -516,8 +516,8 @@
|
||||
#define AR5315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
|
||||
#define AR5315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
|
||||
#define AR5315_PCI_MASK 0x0000FFFF /* Desc Mask */
|
||||
#define AR5315_PCI_EXT_INT 0x02000000
|
||||
#define AR5315_PCI_ABORT_INT 0x04000000
|
||||
#define AR5315_PCI_EXT_INT 0x02000000
|
||||
#define AR5315_PCI_ABORT_INT 0x04000000
|
||||
|
||||
#define AR5315_PCI_INT_MASK (AR5315_PCI + 0x0504) /* same as INT_STATUS */
|
||||
|
||||
@ -658,10 +658,10 @@
|
||||
* sysLib.c/sysTlbInit(), in that it assumes that 2 pages of size
|
||||
* PCI_TLB_PAGE_SIZE are set up in the TLB for each PCI memory space.
|
||||
*/
|
||||
|
||||
|
||||
#define CPU_TO_PCI_MEM_BASE1 0xE0000000
|
||||
#define CPU_TO_PCI_MEM_SIZE1 (2*PCI_TLB_PAGE_SIZE)
|
||||
|
||||
|
||||
|
||||
/* TLB attributes for PCI transactions */
|
||||
|
||||
|
||||
@ -30,11 +30,11 @@ static inline int clz(unsigned long val)
|
||||
: "=r" (ret)
|
||||
: "r" (val)
|
||||
);
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
|
||||
* using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
|
||||
*/
|
||||
@ -157,7 +157,7 @@ extern void ar5315_pci_irq(int irq);
|
||||
static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
||||
reg = sysRegRead(phys);
|
||||
reg &= ~mask;
|
||||
reg |= value & mask;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user