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[brcm63xx] switch to 2.6.39

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27232 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
florian 2011-06-19 20:12:45 +00:00
parent 2abeba9674
commit df49c5b247
26 changed files with 1302 additions and 47 deletions
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2
target/linux/brcm63xx/Makefile
View File

@ -10,7 +10,7 @@ ARCH:=mips
BOARD:=brcm63xx
BOARDNAME:=Broadcom BCM63xx
FEATURES:=squashfs jffs2 usb atm pci pcmcia
LINUX_VERSION:=2.6.37.6
LINUX_VERSION:=2.6.39.1
MAINTAINER:=Florian Fainelli <florian@openwrt.org>
include $(INCLUDE_DIR)/target.mk

74
target/linux/brcm63xx/patches-2.6.37/001-6345_cpu.patch Normal file
View File

@ -0,0 +1,74 @@
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
u32 val;
- if (BCMCPU_IS_6345())
- return (8 * 1024 * 1024);
+ if (BCMCPU_IS_6345()) {
+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
+ return (val * 8 * 1024 * 1024);
+ }
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
val = bcm_sdram_readl(SDRAM_CFG_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -735,6 +735,8 @@
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+#define SDRAM_MBASE_REG 0xc
+
#define SDRAM_PRIO_REG 0x2C
#define SDRAM_PRIO_MIPS_SHIFT 29
#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -698,15 +698,9 @@ void __init board_prom_init(void)
char cfe_version[32];
u32 val;
- /* read base address of boot chip select (0)
- * 6345 does not have MPI but boots from standard
- * MIPS Flash address */
- if (BCMCPU_IS_6345())
- val = 0x1fc00000;
- else {
- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- val &= MPI_CSBASE_BASE_MASK;
- }
+ /* read base address of boot chip select (0) */
+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+ val &= MPI_CSBASE_BASE_MASK;
boot_addr = (u8 *)KSEG1ADDR(val);
/* dump cfe version */
@@ -881,12 +875,9 @@ int __init board_register_devices(void)
bcm63xx_dsp_register(&board.dsp);
/* read base address of boot chip select (0) */
- if (BCMCPU_IS_6345())
- val = 0x1fc00000;
- else {
- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- val &= MPI_CSBASE_BASE_MASK;
- }
+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+ val &= MPI_CSBASE_BASE_MASK;
+
mtd_resources[0].start = val;
mtd_resources[0].end = 0x1FFFFFFF;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_ENET0_BASE (0xfffe1800)
#define BCM_6345_ENETDMA_BASE (0xfffe2800)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
-#define BCM_6345_MPI_BASE (0xdeadbeef)
+#define BCM_6345_MPI_BASE (0xfffe2000)
#define BCM_6345_OHCI0_BASE (0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)

530
target/linux/brcm63xx/patches-2.6.37/080-bcm6345_enet.patch Normal file
View File

@ -0,0 +1,530 @@
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -29,16 +29,15 @@
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
-#define CKCTL_6345_CPU_EN (1 << 0)
-#define CKCTL_6345_BUS_EN (1 << 1)
-#define CKCTL_6345_EBI_EN (1 << 2)
-#define CKCTL_6345_UART_EN (1 << 3)
-#define CKCTL_6345_ADSLPHY_EN (1 << 4)
-#define CKCTL_6345_ENET_EN (1 << 7)
-#define CKCTL_6345_USBH_EN (1 << 8)
+#define CKCTL_6345_CPU_EN (1 << 16)
+#define CKCTL_6345_BUS_EN (1 << 17)
+#define CKCTL_6345_EBI_EN (1 << 18)
+#define CKCTL_6345_UART_EN (1 << 19)
+#define CKCTL_6345_ADSLPHY_EN (1 << 20)
+#define CKCTL_6345_ENET_EN (1 << 23)
+#define CKCTL_6345_USBH_EN (1 << 24)
-#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
- CKCTL_6345_USBH_EN | \
+#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_USBH_EN | \
CKCTL_6345_ADSLPHY_EN)
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
@@ -548,6 +547,39 @@
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG(x) (0x00 + (x) * 0x40)
+#define ENETDMA_6345_CHANCFG_EN_SHIFT 0
+#define ENETDMA_6345_CHANCFG_EN_MASK (1 << ENETDMA_6345_CHANCFG_EN_SHIFT)
+#define ENETDMA_6345_PKTHALT_SHIFT 1
+#define ENETDMA_6345_PKTHALT_MASK (1 << ENETDMA_6345_PKTHALT_SHIFT)
+#define ENETDMA_6345_CHAINING_SHIFT 2
+#define ENETDMA_6345_CHAINING_MASK (1 << ENETDMA_6345_CHAINING_SHIFT)
+#define ENETDMA_6345_WRAP_EN_SHIFT 3
+#define ENETDMA_6345_WRAP_EN_MASK (1 << ENETDMA_6345_WRAP_EN_SHIFT)
+#define ENETDMA_6345_FLOWC_EN_SHIFT 4
+#define ENETDMA_6345_FLOWC_EN_MASK (1 << ENETDMA_6345_FLOWC_EN_SHIFT)
+
+#define ENETDMA_6345_MAXBURST_REG(x) (0x04 + (x) * 0x40)
+
+#define ENETDMA_6345_RSTART_REG(x) (0x08 + (x) * 0x40)
+
+#define ENETDMA_6345_LEN_REG(x) (0x0C + (x) * 0x40)
+
+#define ENETDMA_6345_BSTAT_REG(x) (0x10 + (x) * 0x40)
+
+#define ENETDMA_6345_IR_REG(x) (0x14 + (x) * 0x40)
+#define ENETDMA_6345_IR_BUFDONE_MASK (1 << 0)
+#define ENETDMA_6345_IR_PKTDONE_MASK (1 << 1)
+#define ENETDMA_6345_IR_NOTOWNER_MASK (1 << 2)
+
+#define ENETDMA_6345_IRMASK_REG(x) (0x18 + (x) * 0x40)
+
+#define ENETDMA_6345_FC_REG(x) (0x1C + (x) * 0x40)
+
+#define ENETDMA_6345_BUFALLOC_REG(x) (0x20 + (x) * 0x40)
+
+
/*************************************************************************
* _REG relative to RSET_OHCI_PRIV
*************************************************************************/
--- a/drivers/net/bcm63xx_enet.c
+++ b/drivers/net/bcm63xx_enet.c
@@ -31,6 +31,7 @@
#include <linux/if_vlan.h>
#include <bcm63xx_dev_enet.h>
+#include <bcm63xx_cpu.h>
#include "bcm63xx_enet.h"
static char bcm_enet_driver_name[] = "bcm63xx_enet";
@@ -177,6 +178,7 @@ static void bcm_enet_mdio_write_mii(stru
static int bcm_enet_refill_rx(struct net_device *dev)
{
struct bcm_enet_priv *priv;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
@@ -205,7 +207,7 @@ static int bcm_enet_refill_rx(struct net
len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
len_stat |= DMADESC_OWNER_MASK;
if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
- len_stat |= DMADESC_WRAP_MASK;
+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
priv->rx_dirty_desc = 0;
} else {
priv->rx_dirty_desc++;
@@ -216,7 +218,10 @@ static int bcm_enet_refill_rx(struct net
priv->rx_desc_count++;
/* tell dma engine we allocated one buffer */
- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, 1, ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
}
/* If rx ring is still empty, set a timer to try allocating
@@ -254,6 +259,7 @@ static int bcm_enet_receive_queue(struct
struct bcm_enet_priv *priv;
struct device *kdev;
int processed;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
kdev = &priv->pdev->dev;
@@ -292,7 +298,7 @@ static int bcm_enet_receive_queue(struct
/* if the packet does not have start of packet _and_
* end of packet flag set, then just recycle it */
- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
+ if ((len_stat & (DMADESC_ESOP_MASK >> desc_shift)) != (DMADESC_ESOP_MASK >> desc_shift)) {
dev->stats.rx_dropped++;
continue;
}
@@ -352,8 +358,15 @@ static int bcm_enet_receive_queue(struct
bcm_enet_refill_rx(dev);
/* kick rx dma */
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
}
return processed;
@@ -428,10 +441,21 @@ static int bcm_enet_poll(struct napi_str
dev = priv->net_dev;
/* ack interrupts */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->tx_chan));
+ }
/* reclaim sent skb */
tx_work_done = bcm_enet_tx_reclaim(dev, 0);
@@ -450,10 +474,21 @@ static int bcm_enet_poll(struct napi_str
napi_complete(napi);
/* restore rx/tx interrupt */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
return rx_work_done;
}
@@ -496,8 +531,13 @@ static irqreturn_t bcm_enet_isr_dma(int
priv = netdev_priv(dev);
/* mask rx/tx interrupts */
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
napi_schedule(&priv->napi);
@@ -513,6 +553,7 @@ static int bcm_enet_start_xmit(struct sk
struct bcm_enet_desc *desc;
u32 len_stat;
int ret;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
@@ -538,14 +579,13 @@ static int bcm_enet_start_xmit(struct sk
DMA_TO_DEVICE);
len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
- len_stat |= DMADESC_ESOP_MASK |
- DMADESC_APPEND_CRC |
- DMADESC_OWNER_MASK;
+ len_stat |= ((DMADESC_ESOP_MASK >> desc_shift) |
+ DMADESC_APPEND_CRC | DMADESC_OWNER_MASK);
priv->tx_curr_desc++;
if (priv->tx_curr_desc == priv->tx_ring_size) {
priv->tx_curr_desc = 0;
- len_stat |= DMADESC_WRAP_MASK;
+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
}
priv->tx_desc_count--;
@@ -556,8 +596,15 @@ static int bcm_enet_start_xmit(struct sk
wmb();
/* kick tx dma */
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->tx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->tx_chan));
/* stop queue if no more desc available */
if (!priv->tx_desc_count)
@@ -685,6 +732,9 @@ static void bcm_enet_set_flow(struct bcm
val &= ~ENET_RXCFG_ENFLOW_MASK;
enet_writel(priv, val, ENET_RXCFG_REG);
+ if (BCMCPU_IS_6345())
+ return;
+
/* tx flow control (pause frame generation) */
val = enet_dma_readl(priv, ENETDMA_CFG_REG);
if (tx_en)
@@ -832,8 +882,13 @@ static int bcm_enet_open(struct net_devi
/* mask all interrupts and request them */
enet_writel(priv, 0, ENET_IRMASK_REG);
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
if (ret)
@@ -912,8 +967,12 @@ static int bcm_enet_open(struct net_devi
priv->rx_curr_desc = 0;
/* initialize flow control buffer allocation */
- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
- ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
+ ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
if (bcm_enet_refill_rx(dev)) {
dev_err(kdev, "cannot allocate rx skb queue\n");
@@ -922,37 +981,62 @@ static int bcm_enet_open(struct net_devi
}
/* write rx & tx ring addresses */
- enet_dma_writel(priv, priv->rx_desc_dma,
- ENETDMA_RSTART_REG(priv->rx_chan));
- enet_dma_writel(priv, priv->tx_desc_dma,
- ENETDMA_RSTART_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, priv->rx_desc_dma,
+ ENETDMA_RSTART_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_desc_dma,
+ ENETDMA_RSTART_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, priv->rx_desc_dma,
+ ENETDMA_6345_RSTART_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_desc_dma,
+ ENETDMA_6345_RSTART_REG(priv->tx_chan));
+ }
/* clear remaining state ram for rx & tx channel */
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->tx_chan));
+ }
/* set max rx/tx length */
enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
/* set dma maximum burst len */
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
- ENETDMA_MAXBURST_REG(priv->rx_chan));
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
- ENETDMA_MAXBURST_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_MAXBURST_REG(priv->rx_chan));
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_MAXBURST_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_6345_MAXBURST_REG(priv->rx_chan));
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_6345_MAXBURST_REG(priv->tx_chan));
+ }
/* set correct transmit fifo watermark */
enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
/* set flow control low/high threshold to 1/3 / 2/3 */
- val = priv->rx_ring_size / 3;
- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
- val = (priv->rx_ring_size * 2) / 3;
- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345()) {
+ val = priv->rx_ring_size / 3;
+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
+ val = (priv->rx_ring_size * 2) / 3;
+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
+ } else {
+ enet_dma_writel(priv, 5, ENETDMA_6345_FC_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->rx_ring_size, ENETDMA_6345_LEN_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_ring_size, ENETDMA_6345_LEN_REG(priv->tx_chan));
+ }
/* all set, enable mac and interrupts, start dma engine and
* kick rx dma channel */
@@ -960,27 +1044,58 @@ static int bcm_enet_open(struct net_devi
val = enet_readl(priv, ENET_CTL_REG);
val |= ENET_CTL_ENABLE_MASK;
enet_writel(priv, val, ENET_CTL_REG);
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->rx_chan));
+
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->rx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
+ }
/* watch "mib counters about to overflow" interrupt */
enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
/* watch "packet transferred" interrupt in rx and tx */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->tx_chan));
+ }
/* make sure we enable napi before rx interrupt */
napi_enable(&priv->napi);
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
if (priv->has_phy)
phy_start(priv->phydev);
@@ -1060,13 +1175,19 @@ static void bcm_enet_disable_dma(struct
{
int limit;
- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
+ else
+ enet_dma_writel(priv, 0, ENETDMA_6345_CHANCFG_REG(chan));
limit = 1000;
do {
u32 val;
- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+ if (!BCMCPU_IS_6345())
+ val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+ else
+ val = enet_dma_readl(priv, ENETDMA_6345_CHANCFG_REG(chan));
if (!(val & ENETDMA_CHANCFG_EN_MASK))
break;
udelay(1);
@@ -1093,8 +1214,13 @@ static int bcm_enet_stop(struct net_devi
/* mask all interrupts */
enet_writel(priv, 0, ENET_IRMASK_REG);
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
/* make sure no mib update is scheduled */
flush_scheduled_work();
@@ -1622,6 +1748,7 @@ static int __devinit bcm_enet_probe(stru
const char *clk_name;
unsigned int iomem_size;
int i, ret;
+ unsigned int chan_offset = 0;
/* stop if shared driver failed, assume driver->probe will be
* called in the same order we register devices (correct ?) */
@@ -1661,10 +1788,13 @@ static int __devinit bcm_enet_probe(stru
priv->irq_tx = res_irq_tx->start;
priv->mac_id = pdev->id;
+ if (BCMCPU_IS_6345())
+ chan_offset = 1;
+
/* get rx & tx dma channel id for this mac */
if (priv->mac_id == 0) {
- priv->rx_chan = 0;
- priv->tx_chan = 1;
+ priv->rx_chan = 0 + chan_offset;
+ priv->tx_chan = 1 + chan_offset;
clk_name = "enet0";
} else {
priv->rx_chan = 2;
--- a/drivers/net/bcm63xx_enet.h
+++ b/drivers/net/bcm63xx_enet.h
@@ -46,6 +46,9 @@ struct bcm_enet_desc {
#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
#define DMADESC_WRAP_MASK (1 << 12)
+/* Shift down for EOP, SOP and WRAP bits */
+#define DMADESC_6345_SHIFT (3)
+
#define DMADESC_UNDER_MASK (1 << 9)
#define DMADESC_APPEND_CRC (1 << 8)
#define DMADESC_OVSIZE_MASK (1 << 4)
--- a/arch/mips/bcm63xx/dev-enet.c
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -104,7 +104,7 @@ int __init bcm63xx_enet_register(int uni
if (unit > 1)
return -ENODEV;
- if (unit == 1 && BCMCPU_IS_6338())
+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
return -ENODEV;
if (!shared_device_registered) {

24
target/linux/brcm63xx/patches-2.6.37/456-board-RTA770BW.patch Normal file
View File

@ -0,0 +1,24 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -227,6 +227,13 @@ static struct board_info __initdata boar
.has_uart0 = 1,
};
+
+static struct board_info __initdata board_ra770bw = {
+ .name = "RTA770BW",
+ .expected_cpu_id = 0x6345,
+
+ .has_uart0 = 1,
+};
#endif
/*
@@ -2050,6 +2057,7 @@ static const struct board_info __initdat
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2,
+ &board_ra770bw,
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r,

74
target/linux/brcm63xx/patches-2.6.39/001-6345_cpu.patch Normal file
View File

@ -0,0 +1,74 @@
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
u32 val;
- if (BCMCPU_IS_6345())
- return (8 * 1024 * 1024);
+ if (BCMCPU_IS_6345()) {
+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
+ return (val * 8 * 1024 * 1024);
+ }
if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
val = bcm_sdram_readl(SDRAM_CFG_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -735,6 +735,8 @@
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+#define SDRAM_MBASE_REG 0xc
+
#define SDRAM_PRIO_REG 0x2C
#define SDRAM_PRIO_MIPS_SHIFT 29
#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -698,15 +698,9 @@ void __init board_prom_init(void)
char cfe_version[32];
u32 val;
- /* read base address of boot chip select (0)
- * 6345 does not have MPI but boots from standard
- * MIPS Flash address */
- if (BCMCPU_IS_6345())
- val = 0x1fc00000;
- else {
- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- val &= MPI_CSBASE_BASE_MASK;
- }
+ /* read base address of boot chip select (0) */
+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+ val &= MPI_CSBASE_BASE_MASK;
boot_addr = (u8 *)KSEG1ADDR(val);
/* dump cfe version */
@@ -881,12 +875,9 @@ int __init board_register_devices(void)
bcm63xx_dsp_register(&board.dsp);
/* read base address of boot chip select (0) */
- if (BCMCPU_IS_6345())
- val = 0x1fc00000;
- else {
- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
- val &= MPI_CSBASE_BASE_MASK;
- }
+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+ val &= MPI_CSBASE_BASE_MASK;
+
mtd_resources[0].start = val;
mtd_resources[0].end = 0x1FFFFFFF;
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_ENET0_BASE (0xfffe1800)
#define BCM_6345_ENETDMA_BASE (0xfffe2800)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
-#define BCM_6345_MPI_BASE (0xdeadbeef)
+#define BCM_6345_MPI_BASE (0xfffe2000)
#define BCM_6345_OHCI0_BASE (0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)

2
target/linux/brcm63xx/patches-2.6.39/007-usb-ohci-support.patch
View File

@ -52,7 +52,7 @@ Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
@@ -877,6 +878,9 @@ int __init board_register_devices(void)
@@ -871,6 +872,9 @@ int __init board_register_devices(void)
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);

2
target/linux/brcm63xx/patches-2.6.39/008-usb-ehci-support.patch
View File

@ -44,7 +44,7 @@ Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
@@ -878,6 +879,9 @@ int __init board_register_devices(void)
@@ -872,6 +873,9 @@ int __init board_register_devices(void)
!board_get_mac_address(board.enet1.mac_addr))
bcm63xx_enet_register(1, &board.enet1);

2
target/linux/brcm63xx/patches-2.6.39/010-add_bcm63xx_ohci_controller.patch
View File

@ -177,7 +177,7 @@ Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+MODULE_ALIAS("platform:bcm63xx_ohci");
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1054,6 +1054,11 @@ MODULE_LICENSE ("GPL");
@@ -1056,6 +1056,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER ohci_hcd_da8xx_driver
#endif

2
target/linux/brcm63xx/patches-2.6.39/011-add_bcm63xx_ehci_controller.patch
View File

@ -164,7 +164,7 @@ Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
+MODULE_ALIAS("platform:bcm63xx_ehci");
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1265,6 +1265,11 @@ MODULE_LICENSE ("GPL");
@@ -1267,6 +1267,11 @@ MODULE_LICENSE ("GPL");
#define PLATFORM_DRIVER tegra_ehci_driver
#endif

4
target/linux/brcm63xx/patches-2.6.39/040-bcm963xx_flashmap.patch
View File

@ -12,7 +12,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -816,20 +816,6 @@ void __init board_setup(void)
@@ -810,20 +810,6 @@ void __init board_setup(void)
panic("unexpected CPU for bcm963xx board");
}
@ -33,7 +33,7 @@ Signed-off-by: Axel Gembe <ago@bastart.eu.org>
static struct resource mtd_resources[] = {
{
.start = 0, /* filled at runtime */
@@ -839,12 +825,9 @@ static struct resource mtd_resources[] =
@@ -833,12 +819,9 @@ static struct resource mtd_resources[] =
};
static struct platform_device mtd_dev = {

530
target/linux/brcm63xx/patches-2.6.39/080-bcm6345_enet.patch Normal file
View File

@ -0,0 +1,530 @@
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -29,16 +29,15 @@
CKCTL_6338_SAR_EN | \
CKCTL_6338_SPI_EN)
-#define CKCTL_6345_CPU_EN (1 << 0)
-#define CKCTL_6345_BUS_EN (1 << 1)
-#define CKCTL_6345_EBI_EN (1 << 2)
-#define CKCTL_6345_UART_EN (1 << 3)
-#define CKCTL_6345_ADSLPHY_EN (1 << 4)
-#define CKCTL_6345_ENET_EN (1 << 7)
-#define CKCTL_6345_USBH_EN (1 << 8)
+#define CKCTL_6345_CPU_EN (1 << 16)
+#define CKCTL_6345_BUS_EN (1 << 17)
+#define CKCTL_6345_EBI_EN (1 << 18)
+#define CKCTL_6345_UART_EN (1 << 19)
+#define CKCTL_6345_ADSLPHY_EN (1 << 20)
+#define CKCTL_6345_ENET_EN (1 << 23)
+#define CKCTL_6345_USBH_EN (1 << 24)
-#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
- CKCTL_6345_USBH_EN | \
+#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_USBH_EN | \
CKCTL_6345_ADSLPHY_EN)
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
@@ -548,6 +547,39 @@
#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
+/* Broadcom 6345 ENET DMA definitions */
+#define ENETDMA_6345_CHANCFG_REG(x) (0x00 + (x) * 0x40)
+#define ENETDMA_6345_CHANCFG_EN_SHIFT 0
+#define ENETDMA_6345_CHANCFG_EN_MASK (1 << ENETDMA_6345_CHANCFG_EN_SHIFT)
+#define ENETDMA_6345_PKTHALT_SHIFT 1
+#define ENETDMA_6345_PKTHALT_MASK (1 << ENETDMA_6345_PKTHALT_SHIFT)
+#define ENETDMA_6345_CHAINING_SHIFT 2
+#define ENETDMA_6345_CHAINING_MASK (1 << ENETDMA_6345_CHAINING_SHIFT)
+#define ENETDMA_6345_WRAP_EN_SHIFT 3
+#define ENETDMA_6345_WRAP_EN_MASK (1 << ENETDMA_6345_WRAP_EN_SHIFT)
+#define ENETDMA_6345_FLOWC_EN_SHIFT 4
+#define ENETDMA_6345_FLOWC_EN_MASK (1 << ENETDMA_6345_FLOWC_EN_SHIFT)
+
+#define ENETDMA_6345_MAXBURST_REG(x) (0x04 + (x) * 0x40)
+
+#define ENETDMA_6345_RSTART_REG(x) (0x08 + (x) * 0x40)
+
+#define ENETDMA_6345_LEN_REG(x) (0x0C + (x) * 0x40)
+
+#define ENETDMA_6345_BSTAT_REG(x) (0x10 + (x) * 0x40)
+
+#define ENETDMA_6345_IR_REG(x) (0x14 + (x) * 0x40)
+#define ENETDMA_6345_IR_BUFDONE_MASK (1 << 0)
+#define ENETDMA_6345_IR_PKTDONE_MASK (1 << 1)
+#define ENETDMA_6345_IR_NOTOWNER_MASK (1 << 2)
+
+#define ENETDMA_6345_IRMASK_REG(x) (0x18 + (x) * 0x40)
+
+#define ENETDMA_6345_FC_REG(x) (0x1C + (x) * 0x40)
+
+#define ENETDMA_6345_BUFALLOC_REG(x) (0x20 + (x) * 0x40)
+
+
/*************************************************************************
* _REG relative to RSET_OHCI_PRIV
*************************************************************************/
--- a/drivers/net/bcm63xx_enet.c
+++ b/drivers/net/bcm63xx_enet.c
@@ -31,6 +31,7 @@
#include <linux/if_vlan.h>
#include <bcm63xx_dev_enet.h>
+#include <bcm63xx_cpu.h>
#include "bcm63xx_enet.h"
static char bcm_enet_driver_name[] = "bcm63xx_enet";
@@ -177,6 +178,7 @@ static void bcm_enet_mdio_write_mii(stru
static int bcm_enet_refill_rx(struct net_device *dev)
{
struct bcm_enet_priv *priv;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
@@ -205,7 +207,7 @@ static int bcm_enet_refill_rx(struct net
len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
len_stat |= DMADESC_OWNER_MASK;
if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
- len_stat |= DMADESC_WRAP_MASK;
+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
priv->rx_dirty_desc = 0;
} else {
priv->rx_dirty_desc++;
@@ -216,7 +218,10 @@ static int bcm_enet_refill_rx(struct net
priv->rx_desc_count++;
/* tell dma engine we allocated one buffer */
- enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, 1, ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
}
/* If rx ring is still empty, set a timer to try allocating
@@ -254,6 +259,7 @@ static int bcm_enet_receive_queue(struct
struct bcm_enet_priv *priv;
struct device *kdev;
int processed;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
kdev = &priv->pdev->dev;
@@ -292,7 +298,7 @@ static int bcm_enet_receive_queue(struct
/* if the packet does not have start of packet _and_
* end of packet flag set, then just recycle it */
- if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
+ if ((len_stat & (DMADESC_ESOP_MASK >> desc_shift)) != (DMADESC_ESOP_MASK >> desc_shift)) {
dev->stats.rx_dropped++;
continue;
}
@@ -352,8 +358,15 @@ static int bcm_enet_receive_queue(struct
bcm_enet_refill_rx(dev);
/* kick rx dma */
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
}
return processed;
@@ -428,10 +441,21 @@ static int bcm_enet_poll(struct napi_str
dev = priv->net_dev;
/* ack interrupts */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->tx_chan));
+ }
/* reclaim sent skb */
tx_work_done = bcm_enet_tx_reclaim(dev, 0);
@@ -450,10 +474,21 @@ static int bcm_enet_poll(struct napi_str
napi_complete(napi);
/* restore rx/tx interrupt */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
return rx_work_done;
}
@@ -496,8 +531,13 @@ static irqreturn_t bcm_enet_isr_dma(int
priv = netdev_priv(dev);
/* mask rx/tx interrupts */
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
napi_schedule(&priv->napi);
@@ -513,6 +553,7 @@ static int bcm_enet_start_xmit(struct sk
struct bcm_enet_desc *desc;
u32 len_stat;
int ret;
+ unsigned int desc_shift = BCMCPU_IS_6345() ? DMADESC_6345_SHIFT : 0;
priv = netdev_priv(dev);
@@ -538,14 +579,13 @@ static int bcm_enet_start_xmit(struct sk
DMA_TO_DEVICE);
len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
- len_stat |= DMADESC_ESOP_MASK |
- DMADESC_APPEND_CRC |
- DMADESC_OWNER_MASK;
+ len_stat |= ((DMADESC_ESOP_MASK >> desc_shift) |
+ DMADESC_APPEND_CRC | DMADESC_OWNER_MASK);
priv->tx_curr_desc++;
if (priv->tx_curr_desc == priv->tx_ring_size) {
priv->tx_curr_desc = 0;
- len_stat |= DMADESC_WRAP_MASK;
+ len_stat |= (DMADESC_WRAP_MASK >> desc_shift);
}
priv->tx_desc_count--;
@@ -556,8 +596,15 @@ static int bcm_enet_start_xmit(struct sk
wmb();
/* kick tx dma */
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->tx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->tx_chan));
/* stop queue if no more desc available */
if (!priv->tx_desc_count)
@@ -685,6 +732,9 @@ static void bcm_enet_set_flow(struct bcm
val &= ~ENET_RXCFG_ENFLOW_MASK;
enet_writel(priv, val, ENET_RXCFG_REG);
+ if (BCMCPU_IS_6345())
+ return;
+
/* tx flow control (pause frame generation) */
val = enet_dma_readl(priv, ENETDMA_CFG_REG);
if (tx_en)
@@ -832,8 +882,13 @@ static int bcm_enet_open(struct net_devi
/* mask all interrupts and request them */
enet_writel(priv, 0, ENET_IRMASK_REG);
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
if (ret)
@@ -912,8 +967,12 @@ static int bcm_enet_open(struct net_devi
priv->rx_curr_desc = 0;
/* initialize flow control buffer allocation */
- enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
- ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
+ ENETDMA_BUFALLOC_REG(priv->rx_chan));
+ else
+ enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
+ ENETDMA_6345_BUFALLOC_REG(priv->rx_chan));
if (bcm_enet_refill_rx(dev)) {
dev_err(kdev, "cannot allocate rx skb queue\n");
@@ -922,37 +981,62 @@ static int bcm_enet_open(struct net_devi
}
/* write rx & tx ring addresses */
- enet_dma_writel(priv, priv->rx_desc_dma,
- ENETDMA_RSTART_REG(priv->rx_chan));
- enet_dma_writel(priv, priv->tx_desc_dma,
- ENETDMA_RSTART_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, priv->rx_desc_dma,
+ ENETDMA_RSTART_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_desc_dma,
+ ENETDMA_RSTART_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, priv->rx_desc_dma,
+ ENETDMA_6345_RSTART_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_desc_dma,
+ ENETDMA_6345_RSTART_REG(priv->tx_chan));
+ }
/* clear remaining state ram for rx & tx channel */
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_FC_REG(priv->tx_chan));
+ }
/* set max rx/tx length */
enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
/* set dma maximum burst len */
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
- ENETDMA_MAXBURST_REG(priv->rx_chan));
- enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
- ENETDMA_MAXBURST_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_MAXBURST_REG(priv->rx_chan));
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_MAXBURST_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_6345_MAXBURST_REG(priv->rx_chan));
+ enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
+ ENETDMA_6345_MAXBURST_REG(priv->tx_chan));
+ }
/* set correct transmit fifo watermark */
enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
/* set flow control low/high threshold to 1/3 / 2/3 */
- val = priv->rx_ring_size / 3;
- enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
- val = (priv->rx_ring_size * 2) / 3;
- enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
+ if (!BCMCPU_IS_6345()) {
+ val = priv->rx_ring_size / 3;
+ enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
+ val = (priv->rx_ring_size * 2) / 3;
+ enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
+ } else {
+ enet_dma_writel(priv, 5, ENETDMA_6345_FC_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->rx_ring_size, ENETDMA_6345_LEN_REG(priv->rx_chan));
+ enet_dma_writel(priv, priv->tx_ring_size, ENETDMA_6345_LEN_REG(priv->tx_chan));
+ }
/* all set, enable mac and interrupts, start dma engine and
* kick rx dma channel */
@@ -960,27 +1044,58 @@ static int bcm_enet_open(struct net_devi
val = enet_readl(priv, ENET_CTL_REG);
val |= ENET_CTL_ENABLE_MASK;
enet_writel(priv, val, ENET_CTL_REG);
- enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
- enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
- ENETDMA_CHANCFG_REG(priv->rx_chan));
+
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
+ enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
+ ENETDMA_CHANCFG_REG(priv->rx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_6345_CHANCFG_EN_MASK |
+ ENETDMA_6345_CHAINING_MASK |
+ ENETDMA_6345_WRAP_EN_MASK |
+ ENETDMA_6345_FLOWC_EN_MASK,
+ ENETDMA_6345_CHANCFG_REG(priv->rx_chan));
+ }
/* watch "mib counters about to overflow" interrupt */
enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
/* watch "packet transferred" interrupt in rx and tx */
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IR_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IR_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IR_REG(priv->tx_chan));
+ }
/* make sure we enable napi before rx interrupt */
napi_enable(&priv->napi);
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
- ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
+ ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, ENETDMA_IR_BUFDONE_MASK |
+ ENETDMA_IR_PKTDONE_MASK |
+ ENETDMA_IR_NOTOWNER_MASK,
+ ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
if (priv->has_phy)
phy_start(priv->phydev);
@@ -1060,13 +1175,19 @@ static void bcm_enet_disable_dma(struct
{
int limit;
- enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
+ if (!BCMCPU_IS_6345())
+ enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
+ else
+ enet_dma_writel(priv, 0, ENETDMA_6345_CHANCFG_REG(chan));
limit = 1000;
do {
u32 val;
- val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+ if (!BCMCPU_IS_6345())
+ val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
+ else
+ val = enet_dma_readl(priv, ENETDMA_6345_CHANCFG_REG(chan));
if (!(val & ENETDMA_CHANCFG_EN_MASK))
break;
udelay(1);
@@ -1093,8 +1214,13 @@ static int bcm_enet_stop(struct net_devi
/* mask all interrupts */
enet_writel(priv, 0, ENET_IRMASK_REG);
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
- enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ if (!BCMCPU_IS_6345()) {
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
+ } else {
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->rx_chan));
+ enet_dma_writel(priv, 0, ENETDMA_6345_IRMASK_REG(priv->tx_chan));
+ }
/* make sure no mib update is scheduled */
cancel_work_sync(&priv->mib_update_task);
@@ -1622,6 +1748,7 @@ static int __devinit bcm_enet_probe(stru
const char *clk_name;
unsigned int iomem_size;
int i, ret;
+ unsigned int chan_offset = 0;
/* stop if shared driver failed, assume driver->probe will be
* called in the same order we register devices (correct ?) */
@@ -1661,10 +1788,13 @@ static int __devinit bcm_enet_probe(stru
priv->irq_tx = res_irq_tx->start;
priv->mac_id = pdev->id;
+ if (BCMCPU_IS_6345())
+ chan_offset = 1;
+
/* get rx & tx dma channel id for this mac */
if (priv->mac_id == 0) {
- priv->rx_chan = 0;
- priv->tx_chan = 1;
+ priv->rx_chan = 0 + chan_offset;
+ priv->tx_chan = 1 + chan_offset;
clk_name = "enet0";
} else {
priv->rx_chan = 2;
--- a/drivers/net/bcm63xx_enet.h
+++ b/drivers/net/bcm63xx_enet.h
@@ -46,6 +46,9 @@ struct bcm_enet_desc {
#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
#define DMADESC_WRAP_MASK (1 << 12)
+/* Shift down for EOP, SOP and WRAP bits */
+#define DMADESC_6345_SHIFT (3)
+
#define DMADESC_UNDER_MASK (1 << 9)
#define DMADESC_APPEND_CRC (1 << 8)
#define DMADESC_OVSIZE_MASK (1 << 4)
--- a/arch/mips/bcm63xx/dev-enet.c
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -104,7 +104,7 @@ int __init bcm63xx_enet_register(int uni
if (unit > 1)
return -ENODEV;
- if (unit == 1 && BCMCPU_IS_6338())
+ if (unit == 1 && (BCMCPU_IS_6338() || BCMCPU_IS_6345()))
return -ENODEV;
if (!shared_device_registered) {

4
target/linux/brcm63xx/patches-2.6.39/100-reset_buttons.patch
View File

@ -43,7 +43,7 @@
};
static struct board_info __initdata board_FAST2404 = {
@@ -838,12 +860,23 @@ static struct platform_device bcm63xx_gp
@@ -832,12 +854,23 @@ static struct platform_device bcm63xx_gp
.dev.platform_data = &bcm63xx_led_data,
};
@ -67,7 +67,7 @@
if (board.has_uart0)
bcm63xx_uart_register(0);
@@ -888,5 +921,16 @@ int __init board_register_devices(void)
@@ -879,5 +912,16 @@ int __init board_register_devices(void)
platform_device_register(&bcm63xx_gpio_leds);

4
target/linux/brcm63xx/patches-2.6.39/110-gpiodev.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -852,6 +852,10 @@ static struct platform_device mtd_dev =
@@ -846,6 +846,10 @@ static struct platform_device mtd_dev =
.num_resources = ARRAY_SIZE(mtd_resources),
};
@ -11,7 +11,7 @@
static struct gpio_led_platform_data bcm63xx_led_data;
static struct platform_device bcm63xx_gpio_leds = {
@@ -916,6 +920,8 @@ int __init board_register_devices(void)
@@ -907,6 +911,8 @@ int __init board_register_devices(void)
platform_device_register(&mtd_dev);

4
target/linux/brcm63xx/patches-2.6.39/141-led_count.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -881,6 +881,7 @@ int __init board_register_devices(void)
@@ -875,6 +875,7 @@ int __init board_register_devices(void)
{
u32 val;
int button_count = 0;
@ -8,7 +8,7 @@
if (board.has_uart0)
bcm63xx_uart_register(0);
@@ -922,7 +923,11 @@ int __init board_register_devices(void)
@@ -913,7 +914,11 @@ int __init board_register_devices(void)
platform_device_register_simple("GPIODEV", 0, &gpiodev_resource, 1);

6
target/linux/brcm63xx/patches-2.6.39/180-udc_preliminary_support.patch
View File

@ -17,7 +17,7 @@
};
static struct board_info __initdata board_rta1025w_16 = {
@@ -909,6 +912,9 @@ int __init board_register_devices(void)
@@ -903,6 +906,9 @@ int __init board_register_devices(void)
if (board.has_dsp)
bcm63xx_dsp_register(&board.dsp);
@ -25,8 +25,8 @@
+ bcm63xx_udc_register();
+
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-usb-udc.c
@@ -0,0 +1,58 @@

6
target/linux/brcm63xx/patches-2.6.39/200-extended-platform-devices.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -915,6 +915,9 @@ int __init board_register_devices(void)
@@ -909,6 +909,9 @@ int __init board_register_devices(void)
if (board.has_udc0)
bcm63xx_udc_register();
@ -8,8 +8,8 @@
+ platform_add_devices(board.devs, board.num_devs);
+
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -61,6 +61,10 @@ struct board_info {

6
target/linux/brcm63xx/patches-2.6.39/200-spi-board-info.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -918,6 +918,9 @@ int __init board_register_devices(void)
@@ -912,6 +912,9 @@ int __init board_register_devices(void)
if (board.num_devs)
platform_add_devices(board.devs, board.num_devs);
@ -8,8 +8,8 @@
+ spi_register_board_info(board.spis, board.num_spis);
+
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -65,6 +65,10 @@ struct board_info {

2
target/linux/brcm63xx/patches-2.6.39/220-wl_exports.patch
View File

@ -14,7 +14,7 @@
* known 6338 boards
*/
#ifdef CONFIG_BCM63XX_CPU_6338
@@ -747,6 +754,7 @@ void __init board_prom_init(void)
@@ -741,6 +748,7 @@ void __init board_prom_init(void)
/* extract nvram data */
memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram));

4
target/linux/brcm63xx/patches-2.6.39/230-6358-enet1-external-mii-clk.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -818,6 +818,8 @@ void __init board_prom_init(void)
@@ -812,6 +812,8 @@ void __init board_prom_init(void)
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G3_EXT_MII |
GPIO_MODE_6348_G0_EXT_MII;
@ -11,7 +11,7 @@
bcm_gpio_writel(val, GPIO_MODE_REG);
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -402,6 +402,8 @@
@@ -401,6 +401,8 @@
#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
#define GPIO_MODE_6358_UTOPIA (1 << 12)

8
target/linux/brcm63xx/patches-2.6.39/240-spi.patch
View File

@ -200,7 +200,7 @@
#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -771,4 +771,116 @@
@@ -805,4 +805,116 @@
#define DMIPSPLLCFG_N2_SHIFT 29
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
@ -990,7 +990,7 @@
#include <board_bcm963xx.h>
#define PFX "board_bcm963xx: "
@@ -931,6 +932,9 @@ int __init board_register_devices(void)
@@ -925,6 +926,9 @@ int __init board_register_devices(void)
if (board.num_spis)
spi_register_board_info(board.spis, board.num_spis);
@ -998,5 +998,5 @@
+ bcm63xx_spi_register();
+
/* read base address of boot chip select (0) */
if (BCMCPU_IS_6345())
val = 0x1fc00000;
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;

2
target/linux/brcm63xx/patches-2.6.39/250-boardid_fixup.patch
View File

@ -44,7 +44,7 @@
/*
* early init callback, read nvram data from flash and checksum it
*/
@@ -771,6 +798,11 @@ void __init board_prom_init(void)
@@ -765,6 +792,11 @@ void __init board_prom_init(void)
return;
}

2
target/linux/brcm63xx/patches-2.6.39/441-board-NB4.patch
View File

@ -557,7 +557,7 @@
/*
* Register a sane SPROMv2 to make the on-board
* bcm4318 WLAN work
@@ -959,6 +1485,9 @@ void __init board_prom_init(void)
@@ -953,6 +1479,9 @@ void __init board_prom_init(void)
boardid_fixup(boot_addr);
}

23
target/linux/brcm63xx/patches-2.6.39/452-board_V2500V.patch
View File

@ -72,9 +72,9 @@
#endif
#ifdef CONFIG_BCM63XX_CPU_6358
@@ -2057,6 +2115,22 @@ void __init board_prom_init(void)
val &= MPI_CSBASE_BASE_MASK;
}
@@ -2051,6 +2109,22 @@ void __init board_prom_init(void)
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
boot_addr = (u8 *)KSEG1ADDR(val);
+ printk(KERN_INFO PFX "Boot address 0x%08x\n",(unsigned int)boot_addr);
+
@ -95,17 +95,16 @@
/* dump cfe version */
cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
@@ -2264,6 +2338,14 @@ int __init board_register_devices(void)
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
}
+
+ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */
+ /* Loading from CFE always uses Bank 0 */
@@ -2255,6 +2329,13 @@ int __init board_register_devices(void)
val = bcm_mpi_readl(MPI_CSBASE_REG(0));
val &= MPI_CSBASE_BASE_MASK;
+ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks
+ * Loading from CFE always uses Bank 0 */
+ if (!strcmp(board.name, "V2500V_BB")) {
+ printk(KERN_INFO PFX "V2500V: Start in Bank 0\n");
+ val = val + 0x400000; // Select Bank 0 start address
+ }
+ val = val + 0x400000; /* Select Bank 0 start address */
+ }
+
mtd_resources[0].start = val;
mtd_resources[0].end = 0x1FFFFFFF;

24
target/linux/brcm63xx/patches-2.6.39/456-board-RTA770BW.patch Normal file
View File

@ -0,0 +1,24 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -227,6 +227,13 @@ static struct board_info __initdata boar
.has_uart0 = 1,
};
+
+static struct board_info __initdata board_ra770bw = {
+ .name = "RTA770BW",
+ .expected_cpu_id = 0x6345,
+
+ .has_uart0 = 1,
+};
#endif
/*
@@ -2050,6 +2057,7 @@ static const struct board_info __initdat
#endif
#ifdef CONFIG_BCM63XX_CPU_6345
&board_96345gw2,
+ &board_ra770bw,
#endif
#ifdef CONFIG_BCM63XX_CPU_6348
&board_96348r,

4
target/linux/brcm63xx/patches-2.6.39/500-ssb-add-callback-for-sprom.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -2128,6 +2128,17 @@ static struct ssb_sprom bcm63xx_sprom =
@@ -2136,6 +2136,17 @@ static struct ssb_sprom bcm63xx_sprom =
.boardflags_lo = 0x2848,
.boardflags_hi = 0x0000,
};
@ -18,7 +18,7 @@
#endif
/*
@@ -2328,8 +2339,9 @@ void __init board_prom_init(void)
@@ -2330,8 +2341,9 @@ void __init board_prom_init(void)
if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);

4
target/linux/brcm63xx/patches-2.6.39/977-ssb_export_fallback_sprom.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -2108,7 +2108,7 @@ static void __init nb4_nvram_fixup(void)
@@ -2116,7 +2116,7 @@ static void __init nb4_nvram_fixup(void)
* bcm4318 WLAN work
*/
#ifdef CONFIG_SSB_PCIHOST
@ -9,7 +9,7 @@
.revision = 0x02,
.board_rev = 0x17,
.country_code = 0x0,
@@ -2128,6 +2128,7 @@ static struct ssb_sprom bcm63xx_sprom =
@@ -2136,6 +2136,7 @@ static struct ssb_sprom bcm63xx_sprom =
.boardflags_lo = 0x2848,
.boardflags_hi = 0x0000,
};