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ar71xx: dynamically set AR8327's PAD configuration on AP136
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34882 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -56,40 +56,16 @@
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static struct gpio_led ap136_leds_gpio[] __initdata = {
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{
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@@ -98,63 +104,106 @@ static struct gpio_keys_button ap136_gpi
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@@ -98,63 +104,103 @@ static struct gpio_keys_button ap136_gpi
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},
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};
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-static struct ath79_spi_controller_data ap136_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
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+ .mode = AR8327_PAD_MAC_RGMII,
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+ .txclk_delay_en = true,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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-static struct spi_board_info ap136_spi_info[] = {
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- {
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "mx25l6405d",
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- .controller_data = &ap136_spi0_data,
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- }
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+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = {
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+ .mode = AR8327_PAD_MAC_SGMII,
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+ .txclk_delay_en = false,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
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};
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-static struct ath79_spi_platform_data ap136_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
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+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
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+
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+static struct ar8327_platform_data ap136_ar8327_data = {
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+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
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+ .pad6_cfg = &ap136_ar8327_pad6_cfg,
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@ -109,37 +85,49 @@
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+ },
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data ap136_ath9k_data;
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-static struct spi_board_info ap136_spi_info[] = {
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+static struct mdio_board_info ap136_mdio0_info[] = {
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+ {
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{
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "mx25l6405d",
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- .controller_data = &ap136_spi0_data,
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- }
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &ap136_ar8327_data,
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+ },
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+};
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};
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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-static struct ath79_spi_platform_data ap136_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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-};
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+static void __init ap136_gmac_setup(void)
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{
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- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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- dev->dev.platform_data = &ap136_ath9k_data;
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+{
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+ void __iomem *base;
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+ u32 t;
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data ap136_ath9k_data;
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+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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-{
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- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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- dev->dev.platform_data = &ap136_ath9k_data;
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+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
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- return 0;
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-}
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+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
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+ t |= QCA955X_ETH_CFG_RGMII_EN;
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-static void __init ap136_pci_init(u8 *eeprom)
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-{
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- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
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- sizeof(ap136_ath9k_data.eeprom_data));
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+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
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+
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+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
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+ t |= QCA955X_ETH_CFG_RGMII_EN;
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+
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+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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@ -179,6 +167,16 @@
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+ mdiobus_register_board_info(ap136_mdio0_info,
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+ ARRAY_SIZE(ap136_mdio0_info));
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+
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+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
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+ ap136_ar8327_pad0_cfg.txclk_delay_en = true;
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+ ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
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+ ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
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+
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+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
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+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
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+
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+ /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = BIT(0);
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