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[ramips] uart_clk on Rt3352F is always 40MHz

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Currently, sys_clk/10 is used which is just wrong.
cpu_clk/10 would work for systems with 400MHz CPU clock.

Signed-off-by: Daniel Golle <dgolle@allnet.de>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32812 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
blogic 2012-07-24 20:37:50 +00:00
parent fe61983ee0
commit ea6e386f6f
1 changed files with 1 additions and 1 deletions
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2
target/linux/ramips/files/arch/mips/ralink/rt305x/clock.c
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@ -60,7 +60,7 @@ void __init rt305x_clocks_init(void)
break;
}
rt305x_sys_clk.rate = rt305x_cpu_clk.rate / 3;
rt305x_uart_clk.rate = rt305x_sys_clk.rate / 10;
rt305x_uart_clk.rate = 40000000;
rt305x_wdt_clk.rate = rt305x_sys_clk.rate;
} else {
BUG();