qi-hardware/openwrt-xburst
1
0
Fork 0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-12-25 00:13:54 +02:00
Code

[ar71xx] rename reset register definitions

Browse Source 
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13516 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2008-12-04 16:55:43 +00:00
parent fdce38b54b
commit efbbbe4abd
5 changed files with 39 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/linux/ar71xx/files/arch/mips/ar71xx/ar71xx.c
View File

@ -35,8 +35,8 @@ void ar71xx_device_stop(u32 mask)
unsigned long flags;
local_irq_save(flags);
ar71xx_reset_wr(RESET_REG_RESET_MODULE,
ar71xx_reset_rr(RESET_REG_RESET_MODULE) | mask);
ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE,
ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE) | mask);
local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(ar71xx_device_stop);
@ -46,8 +46,8 @@ void ar71xx_device_start(u32 mask)
unsigned long flags;
local_irq_save(flags);
ar71xx_reset_wr(RESET_REG_RESET_MODULE,
ar71xx_reset_rr(RESET_REG_RESET_MODULE) & ~mask);
ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE,
ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE) & ~mask);
local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(ar71xx_device_start);

32
target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
View File

@ -26,8 +26,8 @@ static void ar71xx_pci_irq_dispatch(void)
{
u32 pending;
pending = ar71xx_reset_rr(RESET_REG_PCI_INT_STATUS) &
ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE);
pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
if (pending & PCI_INT_DEV0)
do_IRQ(AR71XX_PCI_IRQ_DEV0);
@ -45,15 +45,15 @@ static void ar71xx_pci_irq_dispatch(void)
static void ar71xx_pci_irq_unmask(unsigned int irq)
{
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) | (1 << irq));
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
}
static void ar71xx_pci_irq_mask(unsigned int irq)
{
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
}
static struct irq_chip ar71xx_pci_irq_chip = {
@ -72,8 +72,8 @@ static void __init ar71xx_pci_irq_init(void)
{
int i;
ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, 0);
ar71xx_reset_wr(RESET_REG_PCI_INT_STATUS, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
for (i = AR71XX_PCI_IRQ_BASE;
i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
@ -167,8 +167,8 @@ static void ar71xx_misc_irq_dispatch(void)
{
u32 pending;
pending = ar71xx_reset_rr(RESET_REG_MISC_INT_STATUS)
& ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE);
pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
& ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
if (pending & MISC_INT_UART)
do_IRQ(AR71XX_MISC_IRQ_UART);
@ -201,15 +201,15 @@ static void ar71xx_misc_irq_dispatch(void)
static void ar71xx_misc_irq_unmask(unsigned int irq)
{
irq -= AR71XX_MISC_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) | (1 << irq));
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
}
static void ar71xx_misc_irq_mask(unsigned int irq)
{
irq -= AR71XX_MISC_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
}
struct irq_chip ar71xx_misc_irq_chip = {
@ -228,8 +228,8 @@ static void __init ar71xx_misc_irq_init(void)
{
int i;
ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE, 0);
ar71xx_reset_wr(RESET_REG_MISC_INT_STATUS, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
for (i = AR71XX_MISC_IRQ_BASE;
i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {

2
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
View File

@ -108,7 +108,7 @@ static void __init ar71xx_detect_sys_type(void)
u32 id;
u32 rev;
id = ar71xx_reset_rr(RESET_REG_REV_ID) & REV_ID_MASK;
id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
switch (id & REV_ID_CHIP_MASK) {

8
target/linux/ar71xx/files/drivers/watchdog/ar71xx_wdt.c
View File

@ -56,20 +56,20 @@ static int max_timeout;
static void inline ar71xx_wdt_keepalive(void)
{
ar71xx_reset_wr(RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout);
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout);
}
static void inline ar71xx_wdt_enable(void)
{
printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n");
ar71xx_wdt_keepalive();
ar71xx_reset_wr(RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
}
static void inline ar71xx_wdt_disable(void)
{
printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n");
ar71xx_reset_wr(RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
}
static int ar71xx_wdt_set_timeout(int val)
@ -216,7 +216,7 @@ static int __devinit ar71xx_wdt_probe(struct platform_device *pdev)
wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT;
boot_status =
(ar71xx_reset_rr(RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ?
(ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ?
WDIOF_CARDRESET : 0;
ret = misc_register(&ar71xx_wdt_miscdev);

28
target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
View File

@ -296,20 +296,20 @@ extern void ar71xx_ddr_flush(u32 reg);
/*
* RESET block
*/
#define RESET_REG_TIMER 0x00
#define RESET_REG_TIMER_RELOAD 0x04
#define RESET_REG_WDOG_CTRL 0x08
#define RESET_REG_WDOG 0x0c
#define RESET_REG_MISC_INT_STATUS 0x10
#define RESET_REG_MISC_INT_ENABLE 0x14
#define RESET_REG_PCI_INT_STATUS 0x18
#define RESET_REG_PCI_INT_ENABLE 0x1c
#define RESET_REG_GLOBAL_INT_STATUS 0x20
#define RESET_REG_RESET_MODULE 0x24
#define RESET_REG_PERFC_CTRL 0x2c
#define RESET_REG_PERFC0 0x30
#define RESET_REG_PERFC1 0x34
#define RESET_REG_REV_ID 0x90
#define AR71XX_RESET_REG_TIMER 0x00
#define AR71XX_RESET_REG_TIMER_RELOAD 0x04
#define AR71XX_RESET_REG_WDOG_CTRL 0x08
#define AR71XX_RESET_REG_WDOG 0x0c
#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
#define AR71XX_RESET_REG_RESET_MODULE 0x24
#define AR71XX_RESET_REG_PERFC_CTRL 0x2c
#define AR71XX_RESET_REG_PERFC0 0x30
#define AR71XX_RESET_REG_PERFC1 0x34
#define AR71XX_RESET_REG_REV_ID 0x90
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3