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Code

jz4740: irq and dma cleanups.

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This commit is contained in:
Lars-Peter Clausen 2009-09-14 15:07:26 +02:00 committed by Xiangfu Liu
parent d763dfdb80
commit fdeff24f83
4 changed files with 309 additions and 182 deletions
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56
target/linux/xburst/files-2.6.31/arch/mips/include/asm/mach-jz4740/regs.h
View File

@ -69,35 +69,37 @@
#define REG_INTC_IPR REG32(INTC_IPR)
// 1st-level interrupts
#define IRQ_I2C 1
#define IRQ_UHC 3
#define IRQ_UART1 8
#define IRQ_UART0 9
#define IRQ_SADC 12
#define IRQ_MSC 14
#define IRQ_RTC 15
#define IRQ_SSI 16
#define IRQ_CIM 17
#define IRQ_AIC 18
#define IRQ_ETH 19
#define IRQ_DMAC 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_UDC 24
#define IRQ_GPIO3 25
#define IRQ_GPIO2 26
#define IRQ_GPIO1 27
#define IRQ_GPIO0 28
#define IRQ_IPU 29
#define IRQ_LCD 30
#define JZ_IRQ_BASE 8
#define JZ_IRQ(x) (JZ_IRQ_BASE + (x))
#define JZ_IRQ_I2C JZ_IRQ(1)
#define JZ_IRQ_UHC JZ_IRQ(3)
#define JZ_IRQ_UART1 JZ_IRQ(8)
#define JZ_IRQ_UART0 JZ_IRQ(9)
#define JZ_IRQ_SADC JZ_IRQ(12)
#define JZ_IRQ_MSC JZ_IRQ(14)
#define JZ_IRQ_RTC JZ_IRQ(15)
#define JZ_IRQ_SSI JZ_IRQ(16)
#define JZ_IRQ_CIM JZ_IRQ(17)
#define JZ_IRQ_AIC JZ_IRQ(18)
#define JZ_IRQ_ETH JZ_IRQ(19)
#define JZ_IRQ_DMAC JZ_IRQ(20)
#define JZ_IRQ_TCU2 JZ_IRQ(21)
#define JZ_IRQ_TCU1 JZ_IRQ(22)
#define JZ_IRQ_TCU0 JZ_IRQ(23)
#define JZ_IRQ_UDC JZ_IRQ(24)
#define JZ_IRQ_GPIO3 JZ_IRQ(25)
#define JZ_IRQ_GPIO2 JZ_IRQ(26)
#define JZ_IRQ_GPIO1 JZ_IRQ(27)
#define JZ_IRQ_GPIO0 JZ_IRQ(28)
#define JZ_IRQ_IPU JZ_IRQ(29)
#define JZ_IRQ_LCD JZ_IRQ(30)
// 2nd-level interrupts
#define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
#define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
/* 2nd-level interrupts */
#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
#define IRQ_GPIO_0 JZ_IRQ(48) /* 48 to 175 for GPIO pin 0 to 127 */
#define JZ_IRQ_INTC_GPIO(x) (28 - x)
#define JZ_IRQ_GPIO(x) (48 + x)
#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
#define JZ_IRQ_GPIO(x) (IRQ_GPIO_0 + (x))
#define NUM_DMA 6
#define NUM_GPIO 128

186
target/linux/xburst/files-2.6.31/arch/mips/jz4740/dma.c
View File

@ -30,6 +30,56 @@
#include <asm/addrspace.h>
#include <asm/jzsoc.h>
#define JZ_REG_DMA_SRC_ADDR(x) ((x) * 0x20 + 0x00)
#define JZ_REG_DMA_DEST_ADDR(x) ((x) * 0x20 + 0x04)
#define JZ_REG_DMA_COUNT(x) ((x) * 0x20 + 0x08)
#define JZ_REG_DMA_TYPE(x) ((x) * 0x20 + 0x0c)
#define JZ_REG_DMA_STATUS(x) ((x) * 0x20 + 0x10)
#define JZ_REG_DMA_CMD(x) ((x) * 0x20 + 0x14)
#define JZ_REG_DMA_DESC_ADDR(x) ((x) * 0x20 + 0x18)
#define JZ_REG_DMA_CTRL 0x300
#define JZ_REG_DMA_IRQ 0x304
#define JZ_REG_DMA_DOORBELL 0x308
#define JZ_REG_DMA_DOORBELL_SET 0x30C
#define JZ_DMA_STATUS_NO_DESC BIT(31)
#define JZ_DMA_STATUS_CDOA_MASK (0xff << 16)
#define JZ_DMA_STATUS_INV_DESC BIT(6)
#define JZ_DMA_STATUS_ADDR_ERROR BIT(4)
#define JZ_DMA_STATUS_TERMINATE_TRANSFER BIT(3)
#define JZ_DMA_STATUS_HALT BIT(2)
#define JZ_DMA_STATUS_CT BIT(1)
#define JZ_DMA_STATUS_ENABLE BIT(0)
#define JZ_DMA_CMD_SAI BIT(23)
#define JZ_DMA_CMD_DAI BIT(22)
#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
#define JZ_DMA_CMD_DEST_WIDTH_MASK (0x3 << 12)
#define JZ_DMA_CMD_TRANSFER_SIZE_MASK (0x7 << 8)
#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
#define JZ_DMA_CMD_VALID BIT(4)
#define JZ_DMA_CMD_VALID_MODE BIT(3)
#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
#define JZ_DMA_CMD_LINK BIT(0)
static void __iomem *jz_dma_base;
static spinlock_t jz_dma_lock;
static inline uint32_t jz_dma_read(size_t reg)
{
return readl(jz_dma_base + reg);
}
static inline void jz_dma_write(size_t reg, uint32_t val)
{
writel(val, jz_dma_base + reg);
}
/*
* A note on resource allocation:
*
@ -163,7 +213,7 @@ int jz_request_dma(int dev_id, const char *dev_str,
chan = &jz_dma_table[i];
if (irqhandler) {
chan->irq = IRQ_DMA_0 + i; // allocate irq number
chan->irq = JZ_IRQ_DMA(i); // allocate irq number
chan->irq_dev = irq_dev_id;
if ((ret = request_irq(chan->irq, irqhandler, irqflags,
dev_str, chan->irq_dev))) {
@ -304,6 +354,7 @@ int jz_set_dma_mode(unsigned int dmanr, unsigned int mode,
if (dmanr > MAX_DMA_NUM)
return -ENODEV;
for (i = 0; i < MAX_DMA_NUM; i++) {
if (jz_dma_table[i].dev_id < 0)
break;
@ -398,8 +449,8 @@ void set_dma_mode(unsigned int dmanr, unsigned int mode)
} else {
printk(KERN_DEBUG "set_dma_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
}
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
REG_DMAC_DRSR(chan->io) = chan->source;
jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
}
void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
@ -412,11 +463,11 @@ void set_dma_addr(unsigned int dmanr, unsigned int phyaddr)
mode = chan->mode & DMA_MODE_MASK;
if (mode == DMA_MODE_READ) {
REG_DMAC_DSAR(chan->io) = chan->fifo_addr;
REG_DMAC_DTAR(chan->io) = phyaddr;
jz_dma_write(JZ_REG_DMA_SRC_ADDR(chan->io), chan->fifo_addr);
jz_dma_write(JZ_REG_DMA_DEST_ADDR(chan->io), phyaddr);
} else if (mode == DMA_MODE_WRITE) {
REG_DMAC_DSAR(chan->io) = phyaddr;
REG_DMAC_DTAR(chan->io) = chan->fifo_addr;
jz_dma_write(JZ_REG_DMA_SRC_ADDR(chan->io), phyaddr);
jz_dma_write(JZ_REG_DMA_DEST_ADDR(chan->io), chan->fifo_addr);
} else
printk(KERN_DEBUG "Driver should call set_dma_mode() ahead set_dma_addr()!\n");
}
@ -430,8 +481,9 @@ void set_dma_count(unsigned int dmanr, unsigned int bytecnt)
if (!chan)
return;
ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
REG_DMAC_DTCR(chan->io) = bytecnt / dma_ds[ds]; // transfer count
ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
jz_dma_write(JZ_REG_DMA_COUNT(chan->io), bytecnt / dma_ds[ds]);
}
unsigned int get_dma_residue(unsigned int dmanr)
@ -443,7 +495,7 @@ unsigned int get_dma_residue(unsigned int dmanr)
return 0;
ds = (chan->mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT;
count = REG_DMAC_DTCR(chan->io);
count = jz_dma_read(JZ_REG_DMA_COUNT(chan->io));
count = count * dma_ds[ds];
return count;
@ -476,9 +528,9 @@ void jz_set_oss_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_fm
chan->mode &= ~DMAC_DCMD_DAI;
} else
printk("oss_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
REG_DMAC_DRSR(chan->io) = chan->source;
jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
break;
}
}
@ -508,11 +560,13 @@ void jz_set_alsa_dma(unsigned int dmanr, unsigned int mode, unsigned int audio_f
mode &= DMA_MODE_MASK;
chan->mode |= DMAC_DCMD_SAI;
chan->mode &= ~DMAC_DCMD_DAI;
} else
} else {
printk("alsa_dma_burst_mode() just supports DMA_MODE_READ or DMA_MODE_WRITE!\n");
}
jz_dma_write(JZ_REG_DMA_CMD(chan->io), chan->mode & ~DMA_MODE_MASK);
jz_dma_write(JZ_REG_DMA_TYPE(chan->io), chan->source);
REG_DMAC_DCMD(chan->io) = chan->mode & ~DMA_MODE_MASK;
REG_DMAC_DRSR(chan->io) = chan->source;
break;
}
}
@ -749,6 +803,106 @@ void dma_desc_test(void)
#endif
static void jz_dma_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
{
int i;
uint32_t pending;
pending = jz_dma_read(JZ_REG_DMA_IRQ);
for (i = 0; i < 6; ++i) {
if (pending & BIT(i))
generic_handle_irq(JZ_IRQ_DMA(i));
}
}
#define IRQ_TO_DMA(irq) ((irq) - JZ_IRQ_DMA(0))
static void dma_irq_unmask(unsigned int irq)
{
unsigned long flags;
uint32_t mask;
unsigned int chan;
chan = IRQ_TO_DMA(irq);
spin_lock_irqsave(&jz_dma_lock, flags);
mask = jz_dma_read(JZ_REG_DMA_CMD(chan));
mask |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
jz_dma_write(JZ_REG_DMA_CMD(chan), mask);
spin_unlock_irqrestore(&jz_dma_lock, flags);
}
static void dma_irq_mask(unsigned int irq)
{
unsigned long flags;
uint32_t mask;
unsigned int chan;
chan = IRQ_TO_DMA(irq);
spin_lock_irqsave(&jz_dma_lock, flags);
mask = jz_dma_read(JZ_REG_DMA_CMD(chan));
mask &= ~JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
jz_dma_write(JZ_REG_DMA_CMD(chan), mask);
spin_unlock_irqrestore(&jz_dma_lock, flags);
}
static void dma_irq_ack(unsigned int irq)
{
unsigned long flags;
uint32_t pending;
spin_lock_irqsave(&jz_dma_lock, flags);
pending = jz_dma_read(JZ_REG_DMA_IRQ);
pending &= ~BIT(irq);
jz_dma_write(JZ_REG_DMA_IRQ, pending);
spin_unlock_irqrestore(&jz_dma_lock, flags);
}
static void dma_irq_end(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
dma_irq_unmask(irq);
}
}
static struct irq_chip dma_irq_type = {
.name = "DMA",
.unmask = dma_irq_unmask,
.mask = dma_irq_mask,
.ack = dma_irq_ack,
.end = dma_irq_end,
};
static int jz_dma_init(void)
{
int i;
jz_dma_base = ioremap(CPHYSADDR(DMAC_BASE), 0x400);
if (!jz_dma_base)
return -EBUSY;
spin_lock_init(&jz_dma_lock);
set_irq_chained_handler(JZ_IRQ_DMAC, jz_dma_irq_demux_handler);
for (i = 0; i < NUM_DMA; i++) {
dma_irq_mask(JZ_IRQ_DMA(i));
set_irq_chip_and_handler(JZ_IRQ_DMA(i), &dma_irq_type, handle_level_irq);
}
return 0;
}
arch_initcall(jz_dma_init);
//EXPORT_SYMBOL_NOVERS(jz_dma_table);
EXPORT_SYMBOL(jz_dma_table);
EXPORT_SYMBOL(jz_request_dma);

86
target/linux/xburst/files-2.6.31/arch/mips/jz4740/irq.c
View File

@ -32,6 +32,8 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/jzsoc.h>
#include <asm/mach-generic/irq.h>
#include <asm/irq_cpu.h>
static void __iomem *jz_intc_base;
@ -43,23 +45,21 @@ static void __iomem *jz_intc_base;
#define JZ_REG_INTC_CLEAR_MASK 0x0c
#define JZ_REG_INTC_PENDING 0x10
/*
* INTC irq type
*/
#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
static void intc_irq_unmask(unsigned int irq)
{
writel(BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
}
static void intc_irq_mask(unsigned int irq)
{
writel(BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
}
static void intc_irq_ack(unsigned int irq)
{
writel(BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
}
static void intc_irq_end(unsigned int irq)
@ -77,74 +77,46 @@ static struct irq_chip intc_irq_type = {
.end = intc_irq_end,
};
/*
* DMA irq type
*/
static void enable_dma_irq(unsigned int irq)
static irqreturn_t jz4740_cascade(int irq, void *data)
{
__intc_unmask_irq(IRQ_DMAC);
__dmac_channel_enable_irq(irq - IRQ_DMA_0);
uint32_t irq_reg;
irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
if (irq_reg) {
generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
return IRQ_HANDLED;
}
return 0;
}
static void disable_dma_irq(unsigned int irq)
{
__dmac_channel_disable_irq(irq - IRQ_DMA_0);
}
static void mask_and_ack_dma_irq(unsigned int irq)
{
__intc_ack_irq(IRQ_DMAC);
__dmac_channel_disable_irq(irq - IRQ_DMA_0);
}
static void end_dma_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
enable_dma_irq(irq);
}
}
static struct irq_chip dma_irq_type = {
.name = "DMA",
.unmask = enable_dma_irq,
.mask = disable_dma_irq,
.ack = mask_and_ack_dma_irq,
.end = end_dma_irq,
static struct irqaction jz4740_cascade_action = {
.handler = jz4740_cascade,
.name = "JZ4740 cascade interrupt"
};
//----------------------------------------------------------------------
void __init arch_init_irq(void)
{
int i;
clear_c0_status(0xff04); /* clear ERL */
set_c0_status(0x0400); /* set IP2 */
mips_cpu_irq_init();
jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
for (i = 0; i < 32; i++) {
for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
intc_irq_mask(i);
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
/* Set up DMAC irq
*/
for (i = 0; i < NUM_DMA; i++) {
disable_dma_irq(IRQ_DMA_0 + i);
set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
}
setup_irq(2, &jz4740_cascade_action);
}
asmlinkage void plat_irq_dispatch(void)
{
uint32_t irq_reg;
irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
if (irq_reg)
do_IRQ(ffs(irq_reg) - 1);
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
if (pending & STATUSF_IP2)
jz4740_cascade(2, NULL);
else if(pending & STATUSF_IP3)
do_IRQ(3);
else
spurious_interrupt();
}

163
target/linux/xburst/files-2.6.31/arch/mips/jz4740/platform.c
View File

@ -26,14 +26,14 @@
/* OHCI (USB full speed host controller) */
static struct resource jz_usb_ohci_resources[] = {
[0] = {
.start = CPHYSADDR(UHC_BASE), // phys addr for ioremap
.end = CPHYSADDR(UHC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(UHC_BASE),
.end = CPHYSADDR(UHC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UHC,
.end = IRQ_UHC,
.flags = IORESOURCE_IRQ,
.start = JZ_IRQ_UHC,
.end = JZ_IRQ_UHC,
.flags = IORESOURCE_IRQ,
},
};
@ -51,44 +51,18 @@ static struct platform_device jz_usb_ohci_device = {
.resource = jz_usb_ohci_resources,
};
/*** LCD controller ***/
static struct resource jz_lcd_resources[] = {
[0] = {
.start = CPHYSADDR(LCD_BASE),
.end = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD,
.end = IRQ_LCD,
.flags = IORESOURCE_IRQ,
}
};
static u64 jz_lcd_dmamask = ~(u32)0;
static struct platform_device jz_lcd_device = {
.name = "jz-lcd",
.id = 0,
.dev = {
.dma_mask = &jz_lcd_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(jz_lcd_resources),
.resource = jz_lcd_resources,
};
/* UDC (USB gadget controller) */
static struct resource jz_usb_gdt_resources[] = {
[0] = {
.start = CPHYSADDR(UDC_BASE),
.end = CPHYSADDR(UDC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(UDC_BASE),
.end = CPHYSADDR(UDC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_UDC,
.end = IRQ_UDC,
.flags = IORESOURCE_IRQ,
.start = JZ_IRQ_UDC,
.end = JZ_IRQ_UDC,
.flags = IORESOURCE_IRQ,
},
};
@ -96,7 +70,7 @@ static u64 udc_dmamask = ~(u32)0;
static struct platform_device jz_usb_gdt_device = {
.name = "jz-udc",
.id = 0,
.id = -1,
.dev = {
.dma_mask = &udc_dmamask,
.coherent_dma_mask = 0xffffffff,
@ -104,18 +78,24 @@ static struct platform_device jz_usb_gdt_device = {
.num_resources = ARRAY_SIZE(jz_usb_gdt_resources),
.resource = jz_usb_gdt_resources,
};
/*
static struct jz_mmc_platform_data jz_mmc_pdata = {
.card_detect_gpio = JZ_GPIO_PORTD(0),
.read_only_gpio = JZ_GPIO_PORTD(16),
.power_gpio = JZ_GPIO_PORTD(2),
};*/
/** MMC/SD controller **/
static struct resource jz_mmc_resources[] = {
[0] = {
.start = CPHYSADDR(MSC_BASE),
.end = CPHYSADDR(MSC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(MSC_BASE),
.end = CPHYSADDR(MSC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_MSC,
.end = IRQ_MSC,
.flags = IORESOURCE_IRQ,
.start = JZ_IRQ_MSC,
.end = JZ_IRQ_MSC,
.flags = IORESOURCE_IRQ,
}
};
@ -127,6 +107,7 @@ static struct platform_device jz_mmc_device = {
.dev = {
.dma_mask = &jz_mmc_dmamask,
.coherent_dma_mask = 0xffffffff,
/* .platform_data = &jz_mmc_pdata,*/
},
.num_resources = ARRAY_SIZE(jz_mmc_resources),
.resource = jz_mmc_resources,
@ -135,14 +116,14 @@ static struct platform_device jz_mmc_device = {
/** I2C controller **/
static struct resource jz_i2c_resources[] = {
[0] = {
.start = CPHYSADDR(I2C_BASE),
.end = CPHYSADDR(I2C_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(I2C_BASE),
.end = CPHYSADDR(I2C_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_I2C,
.end = IRQ_I2C,
.flags = IORESOURCE_IRQ,
.start = JZ_IRQ_I2C,
.end = JZ_IRQ_I2C,
.flags = IORESOURCE_IRQ,
}
};
@ -161,9 +142,9 @@ static struct platform_device jz_i2c_device = {
static struct resource jz_nand_resources[] = {
[0] = {
.start = CPHYSADDR(EMC_BASE),
.end = CPHYSADDR(EMC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(EMC_BASE),
.end = CPHYSADDR(EMC_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
};
@ -282,7 +263,7 @@ static const uint32_t qi_lb60_keymap[] = {
KEY(6, 7, KEY_RIGHT), /* S57 */
#ifndef KEEP_UART_ALIVE
KEY(7, 0, KEY_LEFTSHIFT), /* S58 */
KEY(7, 0, KEY_QI_LEFTSHIFT), /* S58 */
KEY(7, 1, KEY_LEFTALT), /* S59 */
KEY(7, 2, KEY_FN), /* S60 */
#endif
@ -313,7 +294,7 @@ static struct matrix_keypad_platform_data qi_lb60_pdata = {
.col_scan_delay_us = 10,
.debounce_ms = 10,
.wakeup = 1,
.active_low = 1,
.active_low = 1,
};
static struct platform_device qi_lb60_keypad = {
@ -333,7 +314,7 @@ static struct fb_videomode qi_lb60_video_modes[] = {
.left_margin = 140,
.right_margin = 273,
.upper_margin = 20,
.lower_margin = 1,
.lower_margin = 2,
.hsync_len = 1,
.vsync_len = 1,
.sync = 0,
@ -342,53 +323,55 @@ static struct fb_videomode qi_lb60_video_modes[] = {
};
static struct jz4740_fb_platform_data qi_lb60_fb_data = {
.width = 60,
.height = 45,
.num_modes = ARRAY_SIZE(qi_lb60_video_modes),
.modes = qi_lb60_video_modes,
.bpp = 24,
.lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
.width = 60,
.height = 45,
.num_modes = ARRAY_SIZE(qi_lb60_video_modes),
.modes = qi_lb60_video_modes,
.bpp = 24,
.lcd_type = JZ_LCD_TYPE_8BIT_SERIAL,
};
static struct resource fb_resources[] = {
[0] = {
.start = CPHYSADDR(LCD_BASE),
.end = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(LCD_BASE),
.end = CPHYSADDR(LCD_BASE) + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
};
static u64 jz_fb_dmamask = ~(u32)0;
static struct platform_device qi_lb60_fb = {
.name = "jz4740-fb",
.id = -1,
.num_resources = ARRAY_SIZE(fb_resources),
.resource = fb_resources,
.dev = {
.dma_mask = &jz_lcd_dmamask,
.coherent_dma_mask = 0xffffffff,
.dma_mask = &jz_fb_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &qi_lb60_fb_data,
},
};
struct spi_gpio_platform_data spigpio_platform_data = {
.sck = 32 * 2 + 23,
.mosi = 32 * 2 + 22,
.miso = 32 * 2 + 22,
.num_chipselect = 1,
.sck = JZ_GPIO_PORTC(23),
.mosi = JZ_GPIO_PORTC(22),
.miso = JZ_GPIO_PORTC(22),
.num_chipselect = 1,
};
static struct platform_device spigpio_device = {
.name = "spi_gpio",
.id = 1,
.dev = {
.platform_data = &spigpio_platform_data,
},
.name = "spi_gpio",
.id = 1,
.dev = {
.platform_data = &spigpio_platform_data,
},
};
static struct spi_board_info qi_lb60_spi_board_info[] = {
{
.modalias = "gpm940b0",
.controller_data = (void*)(32 * 2 + 21),
.controller_data = (void*)JZ_GPIO_PORTC(21),
.chip_select = 0,
.bus_num = 1,
.max_speed_hz = 30 * 1000,
@ -397,9 +380,9 @@ static struct spi_board_info qi_lb60_spi_board_info[] = {
static struct resource i2s_resources[] = {
[0] = {
.start = CPHYSADDR(AIC_BASE),
.end = CPHYSADDR(AIC_BASE) + 0x38 - 1,
.flags = IORESOURCE_MEM,
.start = CPHYSADDR(AIC_BASE),
.end = CPHYSADDR(AIC_BASE) + 0x38 - 1,
.flags = IORESOURCE_MEM,
},
};
@ -410,6 +393,21 @@ static struct platform_device jz_i2s_device = {
.resource = i2s_resources,
};
static struct resource codec_resources[] = {
[0] = {
.start = CPHYSADDR(AIC_BASE) + 0x80,
.end = CPHYSADDR(AIC_BASE) + 0x88 - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device jz_codec_device = {
.name = "jz4740-codec",
.id = -1,
.num_resources = ARRAY_SIZE(codec_resources),
.resource = codec_resources,
};
/* All */
static struct platform_device *jz_platform_devices[] __initdata = {
&jz_usb_ohci_device,
@ -418,9 +416,10 @@ static struct platform_device *jz_platform_devices[] __initdata = {
&jz_nand_device,
&jz_i2c_device,
&qi_lb60_keypad,
&qi_lb60_fb,
&spigpio_device,
&qi_lb60_fb,
&jz_i2s_device,
&jz_codec_device,
};
static int __init jz_platform_init(void)