juhosg
|
e96ea88268
|
ar71xx: define NAND controller base address and register size for AR934X/QCA955x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33382 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-09-12 19:06:38 +00:00 |
|
juhosg
|
e1ee097247
|
ar71xx: fix QCA955X_EHCI_SIZE
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33360 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-09-10 14:32:54 +00:00 |
|
juhosg
|
527f8049cd
|
ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33343 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-09-09 14:05:20 +00:00 |
|
juhosg
|
41be3a0bd3
|
ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33335 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-09-08 13:39:09 +00:00 |
|
juhosg
|
74d33b7b96
|
ar71xx: add initial support for the QCA955X SoCs
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32606 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-07-05 08:26:47 +00:00 |
|
juhosg
|
97e6f60806
|
ar71xx: refactor PCI code to allow registering multiple PCI controllers
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32605 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-07-05 08:26:45 +00:00 |
|
juhosg
|
1c9cad5dce
|
ar71xx: update 3.3 patches
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31602 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-05-05 13:56:35 +00:00 |
|
juhosg
|
1a9e33b337
|
ar71xx: add AR934x specific interface speed setup for ge0
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31017 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-03-19 11:11:20 +00:00 |
|
juhosg
|
33ec8951f8
|
ar71xx: add preliminary support for 3.3
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30410 3c298f89-4303-0410-b956-a3cf2f4a3e73
|
2012-02-10 11:53:56 +00:00 |
|