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git://projects.qi-hardware.com/openwrt-xburst.git
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240bf1625e
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11601 3c298f89-4303-0410-b956-a3cf2f4a3e73
424 lines
10 KiB
C
424 lines
10 KiB
C
/*
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* DANUBE internal switch ethernet driver.
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*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
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&& defined(CONFIG_DANUBE_SWITCH)
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#include <malloc.h>
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#include <net.h>
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#include <asm/danube.h>
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#include <asm/addrspace.h>
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#include <asm/pinstrap.h>
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#define MII_MODE 1
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#define REV_MII_MODE 2
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#define TX_CHAN_NO 7
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#define RX_CHAN_NO 6
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 8
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#define MAX_PACKET_SIZE 1536
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#define TOUT_LOOP 100
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#define PHY0_ADDR 1 /*fixme: set the correct value here*/
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#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value
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#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
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#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value
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#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
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typedef struct
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{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 reserved :3;
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volatile u32 Byteoffset :2;
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volatile u32 reserve :7;
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volatile u32 DataLen :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 DataPtr;
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} danube_rx_descriptor_t;
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typedef struct
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{
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union
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{
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struct
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{
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volatile u32 OWN :1;
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volatile u32 C :1;
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volatile u32 Sop :1;
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volatile u32 Eop :1;
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volatile u32 Byteoffset :5;
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volatile u32 reserved :7;
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volatile u32 DataLen :16;
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}field;
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volatile u32 word;
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}status;
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volatile u32 DataPtr;
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} danube_tx_descriptor_t;
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static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8)));
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static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8)));
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static int tx_num, rx_num;
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int danube_switch_init(struct eth_device *dev, bd_t * bis);
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int danube_switch_send(struct eth_device *dev, volatile void *packet,int length);
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int danube_switch_recv(struct eth_device *dev);
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void danube_switch_halt(struct eth_device *dev);
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static void danube_init_switch_chip(int mode);
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static void danube_dma_init(void);
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int danube_switch_initialize(bd_t * bis)
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{
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struct eth_device *dev;
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#if 0
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printf("Entered danube_switch_initialize()\n");
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#endif
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if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
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{
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printf("Failed to allocate memory\n");
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return 0;
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}
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memset(dev, 0, sizeof(*dev));
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danube_dma_init();
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danube_init_switch_chip(REV_MII_MODE);
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#ifdef CLK_OUT2_25MHZ
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*DANUBE_GPIO_P0_DIR=0x0000ae78;
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*DANUBE_GPIO_P0_ALTSEL0=0x00008078;
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//joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
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*DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
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*DANUBE_CGU_IFCCR=0x00400010;
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*DANUBE_GPIO_P0_OD=0x0000ae78;
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#endif
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/*patch for 6996*/
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*DANUBE_RCU_RST_REQ |=1;
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mdelay(200);
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*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
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mdelay(1);
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/*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
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*/
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/*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
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*/
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/***************/
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sprintf(dev->name, "danube Switch");
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dev->init = danube_switch_init;
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dev->halt = danube_switch_halt;
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dev->send = danube_switch_send;
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dev->recv = danube_switch_recv;
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eth_register(dev);
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#if 0
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printf("Leaving danube_switch_initialize()\n");
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#endif
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
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while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F;
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F;
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//while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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//*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F;
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F;
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F;
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F;
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80123602;
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#ifdef CLK_OUT2_25MHZ
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while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000);
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*DANUBE_PPE_ETOP_MDIO_ACC =0x80334000;
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#endif
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return 1;
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}
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int danube_switch_init(struct eth_device *dev, bd_t * bis)
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{
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int i;
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tx_num=0;
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rx_num=0;
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/* Reset DMA
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*/
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// serial_puts("i \n\0");
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*DANUBE_DMA_CS=RX_CHAN_NO;
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*DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
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*DANUBE_DMA_CPOLL= 0x80000040;
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/*set descriptor base*/
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*DANUBE_DMA_CDBA=(u32)rx_des_ring;
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*DANUBE_DMA_CDLEN=NUM_RX_DESC;
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*DANUBE_DMA_CIE = 0;
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*DANUBE_DMA_CCTRL=0x30000;
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*DANUBE_DMA_CS=TX_CHAN_NO;
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*DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
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*DANUBE_DMA_CPOLL= 0x80000040;
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*DANUBE_DMA_CDBA=(u32)tx_des_ring;
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*DANUBE_DMA_CDLEN=NUM_TX_DESC;
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*DANUBE_DMA_CIE = 0;
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*DANUBE_DMA_CCTRL=0x30100;
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for(i=0;i < NUM_RX_DESC; i++)
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{
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danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]);
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rx_desc->status.word=0;
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rx_desc->status.field.OWN=1;
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rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */
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rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]);
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}
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for(i=0;i < NUM_TX_DESC; i++)
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{
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danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]);
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memset(tx_desc, 0, sizeof(tx_des_ring[0]));
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}
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/* turn on DMA rx & tx channel
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*/
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*DANUBE_DMA_CS=RX_CHAN_NO;
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*DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/
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return 0;
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}
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void danube_switch_halt(struct eth_device *dev)
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{
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int i;
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for(i=0;i<8;i++)
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{
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*DANUBE_DMA_CS=i;
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*DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/
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}
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// udelay(1000000);
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}
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int danube_switch_send(struct eth_device *dev, volatile void *packet,int length)
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{
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int i;
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int res = -1;
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danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]);
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if (length <= 0)
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{
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printf ("%s: bad packet size: %d\n", dev->name, length);
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goto Done;
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}
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for(i=0; tx_desc->status.field.OWN==1; i++)
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{
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if(i>=TOUT_LOOP)
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{
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printf("NO Tx Descriptor...");
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goto Done;
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}
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}
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//serial_putc('s');
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tx_desc->status.field.Sop=1;
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tx_desc->status.field.Eop=1;
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tx_desc->status.field.C=0;
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tx_desc->DataPtr = (u32)KSEG1ADDR(packet);
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if(length<60)
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tx_desc->status.field.DataLen = 60;
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else
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tx_desc->status.field.DataLen = (u32)length;
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asm("SYNC");
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tx_desc->status.field.OWN=1;
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res=length;
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tx_num++;
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if(tx_num==NUM_TX_DESC) tx_num=0;
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*DANUBE_DMA_CS=TX_CHAN_NO;
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if(!(*DANUBE_DMA_CCTRL & 1))
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*DANUBE_DMA_CCTRL|=1;
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Done:
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return res;
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}
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int danube_switch_recv(struct eth_device *dev)
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{
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int length = 0;
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danube_rx_descriptor_t * rx_desc;
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int anchor_num=0;
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int i;
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for (;;)
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{
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rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
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if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1))
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{
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break;
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}
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length = rx_desc->status.field.DataLen;
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if (length)
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{
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NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4);
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// serial_putc('*');
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}
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else
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{
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printf("Zero length!!!\n");
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}
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rx_desc->status.field.Sop=0;
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rx_desc->status.field.Eop=0;
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rx_desc->status.field.C=0;
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rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
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rx_desc->status.field.OWN=1;
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rx_num++;
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if(rx_num==NUM_RX_DESC) rx_num=0;
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}
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return length;
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}
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static void danube_init_switch_chip(int mode)
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{
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int i;
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/*get and set mac address for MAC*/
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static unsigned char addr[6];
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char *tmp,*end;
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tmp = getenv ("ethaddr");
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if (NULL == tmp) {
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printf("Can't get environment ethaddr!!!\n");
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// return NULL;
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} else {
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printf("ethaddr=%s\n", tmp);
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}
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*DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF;
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*DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6;
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*DANUBE_PPE32_ENET_MAC_CFG = 0x187;
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// turn on port0, set to rmii and turn off port1.
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if(mode==REV_MII_MODE)
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{
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*DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a;
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}
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else if (mode == MII_MODE)
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{
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*DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008;
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}
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*DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen.
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*ENET_MAC_CFG|=1<<11;/*enable the crc*/
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return;
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}
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static void danube_dma_init(void)
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{
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int i;
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// serial_puts("d \n\0");
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*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
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/* Reset DMA
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*/
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*DANUBE_DMA_CTRL|=1;
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*DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/
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/* Clear Interrupt Status Register
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*/
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*DANUBE_DMA_IRNCR=0xfffff;
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/*disable all the dma interrupts*/
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*DANUBE_DMA_IRNEN=0;
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/*disable channel 0 and channel 1 interrupts*/
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*DANUBE_DMA_CS=RX_CHAN_NO;
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*DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
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*DANUBE_DMA_CPOLL= 0x80000040;
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/*set descriptor base*/
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*DANUBE_DMA_CDBA=(u32)rx_des_ring;
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*DANUBE_DMA_CDLEN=NUM_RX_DESC;
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*DANUBE_DMA_CIE = 0;
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*DANUBE_DMA_CCTRL=0x30000;
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*DANUBE_DMA_CS=TX_CHAN_NO;
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*DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/
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*DANUBE_DMA_CPOLL= 0x80000040;
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*DANUBE_DMA_CDBA=(u32)tx_des_ring;
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*DANUBE_DMA_CDLEN=NUM_TX_DESC;
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*DANUBE_DMA_CIE = 0;
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*DANUBE_DMA_CCTRL=0x30100;
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/*enable the poll function and set the poll counter*/
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//*DANUBE_DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4);
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/*set port properties, enable endian conversion for switch*/
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*DANUBE_DMA_PS=0;
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*DANUBE_DMA_PCTRL|=0xf<<8;/*enable 32 bit endian conversion*/
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return;
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}
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#endif
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