mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e0e5bd88de
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22463 3c298f89-4303-0410-b956-a3cf2f4a3e73
239 lines
7.5 KiB
Diff
239 lines
7.5 KiB
Diff
From ad817ad0a57d0fa6041071395d4cf0d2e9a44635 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 19 Jun 2010 04:08:09 +0000
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Subject: [PATCH] MIPS: JZ4740: Add timer support
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Add support for the timer/counter unit on a JZ4740 SoC. This code is used
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as a common base for the JZ4740 clocksource/clockevent implementation and
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PWM support.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/1396/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/mach-jz4740/timer.h | 22 +++++
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arch/mips/jz4740/timer.c | 48 ++++++++++
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arch/mips/jz4740/timer.h | 136 +++++++++++++++++++++++++++++
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3 files changed, 206 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-jz4740/timer.h
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create mode 100644 arch/mips/jz4740/timer.c
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create mode 100644 arch/mips/jz4740/timer.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/timer.h
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@@ -0,0 +1,22 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 platform timer support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#ifndef __ASM_MACH_JZ4740_TIMER
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+#define __ASM_MACH_JZ4740_TIMER
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+
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+void jz4740_timer_enable_watchdog(void);
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+void jz4740_timer_disable_watchdog(void);
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/jz4740/timer.c
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@@ -0,0 +1,48 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 platform timer support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+
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+#include "timer.h"
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+
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+#include <asm/mach-jz4740/base.h>
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+
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+void __iomem *jz4740_timer_base;
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+
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+void jz4740_timer_enable_watchdog(void)
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+{
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+ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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+}
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+
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+void jz4740_timer_disable_watchdog(void)
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+{
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+ writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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+}
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+
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+void __init jz4740_timer_init(void)
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+{
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+ jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
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+
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+ if (!jz4740_timer_base)
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+ panic("Failed to ioremap timer registers");
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+
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+ /* Disable all timer clocks except for those used as system timers */
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+ writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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+
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+ /* Timer irqs are unmasked by default, mask them */
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+ writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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+}
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--- /dev/null
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+++ b/arch/mips/jz4740/timer.h
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@@ -0,0 +1,136 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 platform timer support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#ifndef __MIPS_JZ4740_TIMER_H__
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+#define __MIPS_JZ4740_TIMER_H__
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+
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+#include <linux/module.h>
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+#include <linux/io.h>
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+
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+#define JZ_REG_TIMER_STOP 0x0C
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+#define JZ_REG_TIMER_STOP_SET 0x1C
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+#define JZ_REG_TIMER_STOP_CLEAR 0x2C
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+#define JZ_REG_TIMER_ENABLE 0x00
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+#define JZ_REG_TIMER_ENABLE_SET 0x04
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+#define JZ_REG_TIMER_ENABLE_CLEAR 0x08
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+#define JZ_REG_TIMER_FLAG 0x10
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+#define JZ_REG_TIMER_FLAG_SET 0x14
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+#define JZ_REG_TIMER_FLAG_CLEAR 0x18
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+#define JZ_REG_TIMER_MASK 0x20
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+#define JZ_REG_TIMER_MASK_SET 0x24
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+#define JZ_REG_TIMER_MASK_CLEAR 0x28
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+
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+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
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+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
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+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
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+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
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+
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+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
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+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
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+
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+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)
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+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
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+#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
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+#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
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+#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
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+#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
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+#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
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+#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
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+#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
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+#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
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+#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
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+
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+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
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+
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+#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
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+#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
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+#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
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+
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+extern void __iomem *jz4740_timer_base;
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+void __init jz4740_timer_init(void);
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+
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+static inline void jz4740_timer_stop(unsigned int timer)
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+{
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+ writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
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+}
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+
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+static inline void jz4740_timer_start(unsigned int timer)
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+{
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+ writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
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+}
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+
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+static inline bool jz4740_timer_is_enabled(unsigned int timer)
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+{
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+ return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
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+}
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+
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+static inline void jz4740_timer_enable(unsigned int timer)
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+{
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+ writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
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+}
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+
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+static inline void jz4740_timer_disable(unsigned int timer)
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+{
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+ writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
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+}
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+
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+
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+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
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+{
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+ writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
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+}
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+
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+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
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+{
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+ writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
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+}
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+
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+static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
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+{
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+ writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
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+}
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+
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+static inline uint16_t jz4740_timer_get_count(unsigned int timer)
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+{
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+ return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
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+}
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+
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+static inline void jz4740_timer_ack_full(unsigned int timer)
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+{
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+ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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+}
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+
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+static inline void jz4740_timer_irq_full_enable(unsigned int timer)
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+{
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+ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
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+ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
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+}
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+
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+static inline void jz4740_timer_irq_full_disable(unsigned int timer)
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+{
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+ writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
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+}
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+
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+static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
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+{
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+ writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
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+}
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+
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+static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
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+{
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+ return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
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+}
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+
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+#endif
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