mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-05 15:03:08 +02:00
28dec42aa3
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20832 3c298f89-4303-0410-b956-a3cf2f4a3e73
560 lines
13 KiB
C
560 lines
13 KiB
C
/*
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* Jz4740 common routines
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*
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* Copyright (c) 2006
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* Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#ifdef CONFIG_JZ4740
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#include <common.h>
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#include <command.h>
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#include <asm/jz4740.h>
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extern void board_early_init(void);
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/* PLL output clock = EXTAL * NF / (NR * NO)
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*
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* NF = FD + 2, NR = RD + 2
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* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
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*/
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void pll_init(void)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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CPM_CPCCR_PCS |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
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/* Init USB Host clock, pllout2 must be n*48MHz */
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REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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void pll_add_test(int new_freq)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
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/* Init UHC clock */
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REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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/* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */
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nf = new_freq / 1000000; /* step length is 1M */
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(10 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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void calc_clocks_add_test(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int pllout;
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unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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pllout = __cpm_get_pllout();
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gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
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gd->sys_clk = pllout / div[__cpm_get_hdiv()];
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gd->per_clk = pllout / div[__cpm_get_pdiv()];
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gd->mem_clk = pllout / div[__cpm_get_mdiv()];
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gd->dev_clk = CONFIG_SYS_EXTAL;
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}
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void sdram_add_test(int new_freq)
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{
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register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = new_freq;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
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REG_EMC_RTCOR = 0;
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REG_EMC_RTCNT = 0;
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/* Basic DMCR register value. */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg parameters */
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ns = 1000000000 / mem_clk;
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#if 0
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tmp = SDRAM_TRAS/ns;
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if (tmp < 4) tmp = 4;
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if (tmp > 11) tmp = 11;
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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tmp = SDRAM_RCD/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = SDRAM_TPC/ns;
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if (tmp > 7) tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = SDRAM_TRWL/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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if (tmp > 14) tmp = 14;
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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#else
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dmcr |= 0xfffc;
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#endif
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/* First, precharge phase */
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REG_EMC_DMCR = dmcr;
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/* Set refresh registers */
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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REG_EMC_RTCOR = tmp;
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REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
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/* SDRAM mode values */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* precharge all chip-selects */
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REG8(EMC_SDMR0|sdmode) = 0;
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/* wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 200;
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while (tmp--);
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/* enable refresh and set SDRAM mode */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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/* write sdram mode register for each chip-select */
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REG8(EMC_SDMR0|sdmode) = 0;
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/* everything is ok now */
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}
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void sdram_init(void)
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{
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CONFIG_SYS_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS/ns;
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if (tmp < 4) tmp = 4;
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if (tmp > 11) tmp = 11;
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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tmp = SDRAM_RCD/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = SDRAM_TPC/ns;
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if (tmp > 7) tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = SDRAM_TRWL/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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if (tmp > 14) tmp = 14;
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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REG_EMC_DMCR = dmcr;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 2. Enable auto-refresh */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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REG_EMC_RTCOR = tmp;
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REG_EMC_RTCNT = 0;
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REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 3. Mode Register Set */
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REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Set back to basic DMCR value */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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/* everything is ok now */
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}
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#ifndef CONFIG_NAND_SPL
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static void calc_clocks(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int pllout;
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unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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pllout = __cpm_get_pllout();
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gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
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gd->sys_clk = pllout / div[__cpm_get_hdiv()];
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gd->per_clk = pllout / div[__cpm_get_pdiv()];
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gd->mem_clk = pllout / div[__cpm_get_mdiv()];
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gd->dev_clk = CONFIG_SYS_EXTAL;
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}
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static void rtc_init(void)
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{
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unsigned long rtcsta;
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while ( !__rtc_write_ready()) ;
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__rtc_enable_alarm(); /* enable alarm */
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while ( !__rtc_write_ready())
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;
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REG_RTC_RGR = 0x00007fff; /* type value */
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while ( !__rtc_write_ready())
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;
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REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
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while ( !__rtc_write_ready())
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;
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REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
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#if 0
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while ( !__rtc_write_ready())
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;
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rtcsta = REG_RTC_HWRSR;
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while ( !__rtc_write_ready())
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;
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if (rtcsta & 0x33) {
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if (rtcsta & 0x10) {
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while ( !__rtc_write_ready())
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;
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REG_RTC_RSR = 0x0;
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}
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while ( !__rtc_write_ready())
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;
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REG_RTC_HWRSR = 0x0;
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}
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#endif
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}
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/*
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* jz4740 board init routine
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*/
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int jz_board_init(void)
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{
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board_early_init(); /* init gpio, pll etc. */
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#ifndef CONFIG_NAND_U_BOOT
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pll_init(); /* init PLL */
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sdram_init(); /* init sdram memory */
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#endif
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calc_clocks(); /* calc the clocks */
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rtc_init(); /* init rtc on any reset: */
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return 0;
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}
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/* U-Boot common routines */
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phys_size_t initdram(int board_type)
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{
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u32 dmcr;
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u32 rows, cols, dw, banks;
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ulong size;
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dmcr = REG_EMC_DMCR;
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rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
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cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
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dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
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banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
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size = (1 << (rows + cols)) * dw * banks;
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return size;
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}
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/*
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* Timer routines
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*/
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#define TIMER_CHAN 0
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#define TIMER_FDATA 0xffff /* Timer full data value */
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#define TIMER_HZ CONFIG_SYS_HZ
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#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
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static ulong timestamp;
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static ulong lastdec;
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void reset_timer_masked (void);
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ulong get_timer_masked (void);
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void udelay_masked (unsigned long usec);
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/*
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* timer without interrupts
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*/
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int timer_init(void)
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{
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REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
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REG_TCU_TCNT(TIMER_CHAN) = 0;
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REG_TCU_TDHR(TIMER_CHAN) = 0;
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REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
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REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
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REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
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REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
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lastdec = 0;
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timestamp = 0;
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return 0;
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}
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void reset_timer(void)
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{
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reset_timer_masked ();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked () - base;
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}
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void set_timer(ulong t)
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{
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timestamp = t;
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}
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void udelay (unsigned long usec)
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{
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ulong tmo,tmp;
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/* normalize */
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if (usec >= 1000) {
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tmo = usec / 1000;
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tmo *= TIMER_HZ;
|
|
tmo /= 1000;
|
|
}
|
|
else {
|
|
if (usec >= 1) {
|
|
tmo = usec * TIMER_HZ;
|
|
tmo /= (1000*1000);
|
|
}
|
|
else
|
|
tmo = 1;
|
|
}
|
|
|
|
/* check for rollover during this delay */
|
|
tmp = get_timer (0);
|
|
if ((tmp + tmo) < tmp )
|
|
reset_timer_masked(); /* timer would roll over */
|
|
else
|
|
tmo += tmp;
|
|
|
|
while (get_timer_masked () < tmo);
|
|
}
|
|
|
|
void reset_timer_masked (void)
|
|
{
|
|
/* reset time */
|
|
lastdec = READ_TIMER;
|
|
timestamp = 0;
|
|
}
|
|
|
|
ulong get_timer_masked (void)
|
|
{
|
|
ulong now = READ_TIMER;
|
|
|
|
if (lastdec <= now) {
|
|
/* normal mode */
|
|
timestamp += (now - lastdec);
|
|
} else {
|
|
/* we have an overflow ... */
|
|
timestamp += TIMER_FDATA + now - lastdec;
|
|
}
|
|
lastdec = now;
|
|
|
|
return timestamp;
|
|
}
|
|
|
|
void udelay_masked (unsigned long usec)
|
|
{
|
|
ulong tmo;
|
|
ulong endtime;
|
|
signed long diff;
|
|
|
|
/* normalize */
|
|
if (usec >= 1000) {
|
|
tmo = usec / 1000;
|
|
tmo *= TIMER_HZ;
|
|
tmo /= 1000;
|
|
} else {
|
|
if (usec > 1) {
|
|
tmo = usec * TIMER_HZ;
|
|
tmo /= (1000*1000);
|
|
} else {
|
|
tmo = 1;
|
|
}
|
|
}
|
|
|
|
endtime = get_timer_masked () + tmo;
|
|
|
|
do {
|
|
ulong now = get_timer_masked ();
|
|
diff = endtime - now;
|
|
} while (diff >= 0);
|
|
}
|
|
|
|
/*
|
|
* This function is derived from PowerPC code (read timebase as long long).
|
|
* On MIPS it just returns the timer value.
|
|
*/
|
|
unsigned long long get_ticks(void)
|
|
{
|
|
return get_timer(0);
|
|
}
|
|
|
|
/*
|
|
* This function is derived from PowerPC code (timebase clock frequency).
|
|
* On MIPS it returns the number of timer ticks per second.
|
|
*/
|
|
ulong get_tbclk (void)
|
|
{
|
|
return TIMER_HZ;
|
|
}
|
|
|
|
#endif /* CONFIG_NAND_SPL */
|
|
|
|
/* End of timer routine. */
|
|
|
|
#endif
|