mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 21:36:16 +02:00
cf6dac9a38
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9821 3c298f89-4303-0410-b956-a3cf2f4a3e73
320 lines
9.2 KiB
C
320 lines
9.2 KiB
C
#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/mm.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/addrspace.h>
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#include <linux/vmalloc.h>
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#define IFXMIPS_PCI_MEM_BASE 0x18000000
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#define IFXMIPS_PCI_MEM_SIZE 0x02000000
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#define IFXMIPS_PCI_IO_BASE 0x1AE00000
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#define IFXMIPS_PCI_IO_SIZE 0x00200000
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#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16
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#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11
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#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
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static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
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struct pci_ops danube_pci_ops = {
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.read = danube_pci_read_config_dword,
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.write = danube_pci_write_config_dword
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};
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static struct resource pci_io_resource = {
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.name = "io pci IO space",
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.start = IFXMIPS_PCI_IO_BASE,
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.end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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.name = "ext pci memory space",
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.start = IFXMIPS_PCI_MEM_BASE,
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.end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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static struct pci_controller danube_pci_controller = {
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.pci_ops = &danube_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &pci_io_resource,
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.io_offset = 0x00000000UL,
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};
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static u32 danube_pci_mapped_cfg;
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static int
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danube_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data)
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{
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unsigned long cfg_base;
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unsigned long flags;
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u32 temp;
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/* Danube support slot from 0 to 15 */
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/* dev_fn 0&0x68 (AD29) is danube itself */
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if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
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|| ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
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return 1;
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local_irq_save(flags);
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cfg_base = danube_pci_mapped_cfg;
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cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn <<
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IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
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/* Perform access */
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if (access_type == PCI_ACCESS_WRITE)
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{
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#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
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writel(swab32(*data), ((u32*)cfg_base));
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#else
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writel(*data, ((u32*)cfg_base));
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#endif
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} else {
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*data = readl(((u32*)(cfg_base)));
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#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
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*data = swab32(*data);
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#endif
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}
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wmb();
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/* clean possible Master abort */
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cfg_base = (danube_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
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temp = readl(((u32*)(cfg_base)));
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#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
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temp = swab32 (temp);
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#endif
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cfg_base = (danube_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4;
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writel(temp, ((u32*)cfg_base));
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local_irq_restore(flags);
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if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
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return 1;
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return 0;
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}
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static int danube_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int danube_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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{
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data = val;
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} else {
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if (danube_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (danube_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev){
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u8 pin;
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pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
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switch(pin) {
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case 0:
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break;
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case 1:
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//falling edge level triggered:0x4, low level:0xc, rising edge:0x2
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printk("%s:%s[%d] %08X \n", __FILE__, __func__, __LINE__, dev->irq);
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writel(readl(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
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writel(readl(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
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break;
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case 2:
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case 3:
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case 4:
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printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
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default:
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printk ("WARNING: invalid interrupt pin %d\n", pin);
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return 1;
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}
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return 0;
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}
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static void __init danube_pci_startup (void){
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/*initialize the first PCI device--danube itself */
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u32 temp_buffer;
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/*TODO: trigger reset */
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writel(readl(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
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writel(readl(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
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/* PCIS of IF_CLK of CGU : 1 =>PCI Clock output
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0 =>clock input
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PADsel of PCI_CR of CGU : 1 =>From CGU
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: 0 =>From pad
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*/
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writel(readl(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
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writel((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
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/* prepare GPIO */
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/* PCI_RST: P1.5 ALT 01 */
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//pliu20060613: start
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writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
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writel(readl(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
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writel(readl(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
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writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
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writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
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//pliu20060613: end
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/* PCI_REQ1: P1.13 ALT 01 */
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/* PCI_GNT1: P1.14 ALT 01 */
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writel(readl(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
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writel(readl(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
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writel(readl(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
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writel(readl(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
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/* PCI_REQ2: P1.15 ALT 10 */
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/* PCI_GNT2: P1.7 ALT 10 */
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/* enable auto-switching between PCI and EBU */
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writel(0xa, PCI_CR_CLK_CTRL);
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/* busy, i.e. configuration is not done, PCI access has to be retried */
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writel(readl(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
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wmb ();
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/* BUS Master/IO/MEM access */
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writel(readl(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
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temp_buffer = readl(PCI_CR_PC_ARB);
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/* enable external 2 PCI masters */
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temp_buffer &= (~(0xf << 16));
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/* enable internal arbiter */
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temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
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/* enable internal PCI master reqest */
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temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
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/* enable EBU reqest */
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temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
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/* enable all external masters request */
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temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
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writel(temp_buffer, PCI_CR_PC_ARB);
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wmb ();
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/* FPI ==> PCI MEM address mapping */
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/* base: 0xb8000000 == > 0x18000000 */
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/* size: 8x4M = 32M */
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writel(0x18000000, PCI_CR_FCI_ADDR_MAP0);
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writel(0x18400000, PCI_CR_FCI_ADDR_MAP1);
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writel(0x18800000, PCI_CR_FCI_ADDR_MAP2);
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writel(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
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writel(0x19000000, PCI_CR_FCI_ADDR_MAP4);
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writel(0x19400000, PCI_CR_FCI_ADDR_MAP5);
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writel(0x19800000, PCI_CR_FCI_ADDR_MAP6);
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writel(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
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/* FPI ==> PCI IO address mapping */
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/* base: 0xbAE00000 == > 0xbAE00000 */
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/* size: 2M */
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writel(0xbae00000, PCI_CR_FCI_ADDR_MAP11hg);
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/* PCI ==> FPI address mapping */
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/* base: 0x0 ==> 0x0 */
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/* size: 32M */
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/* BAR1 32M map to SDR address */
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writel(0x0e000008, PCI_CR_BAR11MASK);
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writel(0, PCI_CR_PCI_ADDR_MAP11);
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writel(0, PCI_CS_BASE_ADDR1);
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#ifdef CONFIG_IFXMIPS_PCI_HW_SWAP
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/* both TX and RX endian swap are enabled */
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IFXMIPS_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3;
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wmb ();
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#endif
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/*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
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writel(readl(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
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writel(readl(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
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/*use 8 dw burse length */
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writel(0x303, PCI_CR_FCI_BURST_LENGTH);
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writel(readl(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
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wmb();
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writel(readl(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
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wmb();
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mdelay (1);
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writel(readl(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
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printk("\n\n\n%s:%s[%d] %d %d\n", __FILE__, __func__, __LINE__, slot, pin);
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switch (slot) {
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case 13:
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/* IDSEL = AD29 --> USB Host Controller */
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return (INT_NUM_IM1_IRL0 + 17);
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case 14:
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/* IDSEL = AD30 --> mini PCI connector */
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//return (INT_NUM_IM1_IRL0 + 14);
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return (INT_NUM_IM0_IRL0 + 22);
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default:
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printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
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return 0;
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}
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}
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int pcibios_init(void){
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extern int pci_probe_only;
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pci_probe_only = 0;
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printk ("PCI: Probing PCI hardware on host bus 0.\n");
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danube_pci_startup ();
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// IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
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danube_pci_mapped_cfg = ioremap_nocache(0x17000000, 0x800 * 16);
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printk("Danube PCI mapped to 0x%08X\n", (unsigned long)danube_pci_mapped_cfg);
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danube_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
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printk("Danube PCI I/O mapped to 0x%08X\n", (unsigned long)danube_pci_controller.io_map_base);
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register_pci_controller(&danube_pci_controller);
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return 0;
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}
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arch_initcall(pcibios_init);
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