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git://projects.qi-hardware.com/openwrt-xburst.git
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e0e5bd88de
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22463 3c298f89-4303-0410-b956-a3cf2f4a3e73
353 lines
9.0 KiB
Diff
353 lines
9.0 KiB
Diff
From c7efc7b27ca91012c99618ad5efeec705671bd66 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 17 Jul 2010 11:13:29 +0000
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Subject: [PATCH] MIPS: JZ4740: Add platform devices
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Add platform devices for all the JZ4740 platform drivers.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/1469/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/mach-jz4740/platform.h | 36 ++++
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arch/mips/jz4740/platform.c | 291 ++++++++++++++++++++++++++
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2 files changed, 327 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-jz4740/platform.h
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create mode 100644 arch/mips/jz4740/platform.c
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/platform.h
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@@ -0,0 +1,36 @@
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+/*
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+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 platform device definitions
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+
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+#ifndef __JZ4740_PLATFORM_H
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+#define __JZ4740_PLATFORM_H
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+
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+#include <linux/platform_device.h>
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+
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+extern struct platform_device jz4740_usb_ohci_device;
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+extern struct platform_device jz4740_udc_device;
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+extern struct platform_device jz4740_mmc_device;
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+extern struct platform_device jz4740_rtc_device;
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+extern struct platform_device jz4740_i2c_device;
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+extern struct platform_device jz4740_nand_device;
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+extern struct platform_device jz4740_framebuffer_device;
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+extern struct platform_device jz4740_i2s_device;
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+extern struct platform_device jz4740_pcm_device;
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+extern struct platform_device jz4740_codec_device;
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+extern struct platform_device jz4740_adc_device;
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+
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+void jz4740_serial_device_register(void);
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/jz4740/platform.c
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@@ -0,0 +1,291 @@
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+/*
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+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 platform devices
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/platform_device.h>
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+#include <linux/resource.h>
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+
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+#include <linux/dma-mapping.h>
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+
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+#include <asm/mach-jz4740/platform.h>
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+#include <asm/mach-jz4740/base.h>
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+#include <asm/mach-jz4740/irq.h>
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+
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+#include <linux/serial_core.h>
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+#include <linux/serial_8250.h>
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+
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+#include "serial.h"
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+#include "clock.h"
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+
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+/* OHCI controller */
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+static struct resource jz4740_usb_ohci_resources[] = {
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+ {
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+ .start = JZ4740_UHC_BASE_ADDR,
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+ .end = JZ4740_UHC_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_UHC,
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+ .end = JZ4740_IRQ_UHC,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+struct platform_device jz4740_usb_ohci_device = {
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+ .name = "jz4740-ohci",
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+ .id = -1,
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+ .dev = {
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+ .dma_mask = &jz4740_usb_ohci_device.dev.coherent_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+ .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
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+ .resource = jz4740_usb_ohci_resources,
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+};
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+
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+/* UDC (USB gadget controller) */
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+static struct resource jz4740_usb_gdt_resources[] = {
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+ {
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+ .start = JZ4740_UDC_BASE_ADDR,
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+ .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_UDC,
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+ .end = JZ4740_IRQ_UDC,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+struct platform_device jz4740_udc_device = {
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+ .name = "jz-udc",
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+ .id = -1,
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+ .dev = {
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+ .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+ .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
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+ .resource = jz4740_usb_gdt_resources,
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+};
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+
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+/* MMC/SD controller */
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+static struct resource jz4740_mmc_resources[] = {
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+ {
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+ .start = JZ4740_MSC_BASE_ADDR,
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+ .end = JZ4740_MSC_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_MSC,
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+ .end = JZ4740_IRQ_MSC,
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+ .flags = IORESOURCE_IRQ,
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+ }
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+};
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+
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+struct platform_device jz4740_mmc_device = {
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+ .name = "jz4740-mmc",
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+ .id = 0,
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+ .dev = {
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+ .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+ .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
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+ .resource = jz4740_mmc_resources,
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+};
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+
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+/* RTC controller */
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+static struct resource jz4740_rtc_resources[] = {
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+ {
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+ .start = JZ4740_RTC_BASE_ADDR,
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+ .end = JZ4740_RTC_BASE_ADDR + 0x38 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_RTC,
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+ .end = JZ4740_IRQ_RTC,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+struct platform_device jz4740_rtc_device = {
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+ .name = "jz4740-rtc",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
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+ .resource = jz4740_rtc_resources,
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+};
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+
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+/* I2C controller */
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+static struct resource jz4740_i2c_resources[] = {
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+ {
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+ .start = JZ4740_I2C_BASE_ADDR,
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+ .end = JZ4740_I2C_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_I2C,
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+ .end = JZ4740_IRQ_I2C,
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+ .flags = IORESOURCE_IRQ,
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+ }
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+};
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+
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+struct platform_device jz4740_i2c_device = {
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+ .name = "jz4740-i2c",
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+ .id = 0,
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+ .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
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+ .resource = jz4740_i2c_resources,
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+};
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+
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+/* NAND controller */
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+static struct resource jz4740_nand_resources[] = {
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+ {
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+ .name = "mmio",
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+ .start = JZ4740_EMC_BASE_ADDR,
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+ .end = JZ4740_EMC_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "bank",
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+ .start = 0x18000000,
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+ .end = 0x180C0000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+struct platform_device jz4740_nand_device = {
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+ .name = "jz4740-nand",
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+ .num_resources = ARRAY_SIZE(jz4740_nand_resources),
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+ .resource = jz4740_nand_resources,
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+};
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+
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+/* LCD controller */
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+static struct resource jz4740_framebuffer_resources[] = {
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+ {
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+ .start = JZ4740_LCD_BASE_ADDR,
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+ .end = JZ4740_LCD_BASE_ADDR + 0x1000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+struct platform_device jz4740_framebuffer_device = {
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+ .name = "jz4740-fb",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
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+ .resource = jz4740_framebuffer_resources,
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+ .dev = {
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+ .dma_mask = &jz4740_framebuffer_device.dev.coherent_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+/* I2S controller */
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+static struct resource jz4740_i2s_resources[] = {
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+ {
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+ .start = JZ4740_AIC_BASE_ADDR,
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+ .end = JZ4740_AIC_BASE_ADDR + 0x38 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+struct platform_device jz4740_i2s_device = {
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+ .name = "jz4740-i2s",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
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+ .resource = jz4740_i2s_resources,
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+};
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+
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+/* PCM */
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+struct platform_device jz4740_pcm_device = {
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+ .name = "jz4740-pcm",
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+ .id = -1,
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+};
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+
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+/* Codec */
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+static struct resource jz4740_codec_resources[] = {
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+ {
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+ .start = JZ4740_AIC_BASE_ADDR + 0x80,
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+ .end = JZ4740_AIC_BASE_ADDR + 0x88 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+struct platform_device jz4740_codec_device = {
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+ .name = "jz4740-codec",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(jz4740_codec_resources),
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+ .resource = jz4740_codec_resources,
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+};
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+
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+/* ADC controller */
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+static struct resource jz4740_adc_resources[] = {
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+ {
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+ .start = JZ4740_SADC_BASE_ADDR,
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+ .end = JZ4740_SADC_BASE_ADDR + 0x30,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = JZ4740_IRQ_SADC,
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+ .end = JZ4740_IRQ_SADC,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .start = JZ4740_IRQ_ADC_BASE,
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+ .end = JZ4740_IRQ_ADC_BASE,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+struct platform_device jz4740_adc_device = {
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+ .name = "jz4740-adc",
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+ .id = -1,
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+ .num_resources = ARRAY_SIZE(jz4740_adc_resources),
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+ .resource = jz4740_adc_resources,
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+};
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+
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+/* Serial */
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+#define JZ4740_UART_DATA(_id) \
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+ { \
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+ .flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE, \
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+ .iotype = UPIO_MEM, \
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+ .regshift = 2, \
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+ .serial_out = jz4740_serial_out, \
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+ .type = PORT_16550, \
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+ .mapbase = JZ4740_UART ## _id ## _BASE_ADDR, \
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+ .irq = JZ4740_IRQ_UART ## _id, \
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+ }
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+
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+static struct plat_serial8250_port jz4740_uart_data[] = {
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+ JZ4740_UART_DATA(0),
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+ JZ4740_UART_DATA(1),
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+ {},
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+};
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+
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+static struct platform_device jz4740_uart_device = {
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+ .name = "serial8250",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = jz4740_uart_data,
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+ },
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+};
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+
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+void jz4740_serial_device_register(void)
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+{
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+ struct plat_serial8250_port *p;
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+
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+ for (p = jz4740_uart_data; p->flags != 0; ++p)
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+ p->uartclk = jz4740_clock_bdata.ext_rate;
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+
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+ platform_device_register(&jz4740_uart_device);
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+}
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