mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20832 3c298f89-4303-0410-b956-a3cf2f4a3e73
485 lines
13 KiB
C
485 lines
13 KiB
C
/*
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* JzRISC lcd controller
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*
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* xiangfu liu <xiangfu.z@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Fallowing macro may be used:
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* CONFIG_LCD : LCD support
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* LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
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* CONFIG_LCD_LOGO : show logo
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*/
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#include <config.h>
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#include <common.h>
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#include <lcd.h>
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#include <asm/io.h> /* virt_to_phys() */
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#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
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#if defined(CONFIG_JZ4740)
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#include <asm/jz4740.h>
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#endif
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#include "jz_lcd.h"
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struct jzfb_info {
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unsigned int cfg; /* panel mode and pin usage etc. */
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unsigned int w;
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unsigned int h;
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unsigned int bpp; /* bit per pixel */
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unsigned int fclk; /* frame clk */
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unsigned int hsw; /* hsync width, in pclk */
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unsigned int vsw; /* vsync width, in line count */
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unsigned int elw; /* end of line, in pclk */
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unsigned int blw; /* begin of line, in pclk */
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unsigned int efw; /* end of frame, in line count */
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unsigned int bfw; /* begin of frame, in line count */
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};
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static struct jzfb_info jzfb = {
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#if defined(CONFIG_NANONOTE)
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MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
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320, 240, 32, 70, 1, 1, 273, 140, 1, 20
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#endif
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};
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/************************************************************************/
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vidinfo_t panel_info = {
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#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
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320, 240, LCD_BPP,
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#endif
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};
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/*----------------------------------------------------------------------*/
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int lcd_line_length;
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int lcd_color_fg;
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int lcd_color_bg;
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/*
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* Frame buffer memory information
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*/
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void *lcd_base; /* Start of framebuffer memory */
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void *lcd_console_address; /* Start of console buffer */
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short console_col;
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short console_row;
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/*----------------------------------------------------------------------*/
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void lcd_ctrl_init (void *lcdbase);
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void lcd_enable (void);
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void lcd_disable (void);
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/*----------------------------------------------------------------------*/
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static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
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static void jz_lcd_desc_init(vidinfo_t *vid);
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static int jz_lcd_hw_init( vidinfo_t *vid );
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extern int flush_cache_all(void);
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#if LCD_BPP == LCD_COLOR8
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void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
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#endif
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#if LCD_BPP == LCD_MONOCHROME
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void lcd_initcolregs (void);
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#endif
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/*-----------------------------------------------------------------------*/
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void lcd_ctrl_init (void *lcdbase)
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{
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__lcd_display_pin_init();
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jz_lcd_init_mem(lcdbase, &panel_info);
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jz_lcd_desc_init(&panel_info);
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jz_lcd_hw_init(&panel_info);
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__lcd_display_on() ;
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}
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_COLOR8
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void
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lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
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{
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}
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#endif
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_MONOCHROME
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static
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void lcd_initcolregs (void)
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{
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}
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#endif
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/*
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* Before enabled lcd controller, lcd registers should be configured correctly.
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*/
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void lcd_enable (void)
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{
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REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
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REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
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}
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void lcd_disable (void)
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{
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REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
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/* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
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}
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static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
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{
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u_long palette_mem_size;
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struct jz_fb_info *fbi = &vid->jz_fb;
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int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
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fbi->screen = (u_long)lcdbase;
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fbi->palette_size = 256;
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palette_mem_size = fbi->palette_size * sizeof(u16);
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debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
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/* locate palette and descs at end of page following fb */
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fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
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return 0;
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}
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static void jz_lcd_desc_init(vidinfo_t *vid)
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{
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struct jz_fb_info * fbi;
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fbi = &vid->jz_fb;
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fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
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fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
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fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
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#define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
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/* populate descriptors */
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fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
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fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
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fbi->dmadesc_fblow->fidr = 0;
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fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
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fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
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fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
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fbi->dmadesc_fbhigh->fidr = 0;
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fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
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fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
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fbi->dmadesc_palette->fidr = 0;
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fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
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if( NBITS(vid->vl_bpix) < 12)
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{
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/* assume any mode with <12 bpp is palette driven */
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fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
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fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
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/* flips back and forth between pal and fbhigh */
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fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
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} else {
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/* palette shouldn't be loaded in true-color mode */
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fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
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fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
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}
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flush_cache_all();
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}
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static int jz_lcd_hw_init(vidinfo_t *vid)
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{
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struct jz_fb_info *fbi = &vid->jz_fb;
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unsigned int val = 0;
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unsigned int pclk;
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unsigned int stnH;
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#if defined(CONFIG_MIPS_JZ4740)
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int pll_div;
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#endif
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/* Setting Control register */
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switch (jzfb.bpp) {
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case 1:
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val |= LCD_CTRL_BPP_1;
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break;
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case 2:
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val |= LCD_CTRL_BPP_2;
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break;
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case 4:
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val |= LCD_CTRL_BPP_4;
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break;
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case 8:
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val |= LCD_CTRL_BPP_8;
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break;
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case 15:
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val |= LCD_CTRL_RGB555;
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case 16:
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val |= LCD_CTRL_BPP_16;
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break;
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#if defined(CONFIG_MIPS_JZ4740)
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case 17 ... 32:
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val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
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break;
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#endif
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default:
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printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
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val |= LCD_CTRL_BPP_16;
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break;
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}
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switch (jzfb.cfg & MODE_MASK) {
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case MODE_STN_MONO_DUAL:
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case MODE_STN_COLOR_DUAL:
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case MODE_STN_MONO_SINGLE:
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case MODE_STN_COLOR_SINGLE:
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switch (jzfb.bpp) {
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case 1:
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/* val |= LCD_CTRL_PEDN; */
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case 2:
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val |= LCD_CTRL_FRC_2;
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break;
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case 4:
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val |= LCD_CTRL_FRC_4;
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break;
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case 8:
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default:
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val |= LCD_CTRL_FRC_16;
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break;
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}
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break;
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}
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val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
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val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
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switch (jzfb.cfg & MODE_MASK) {
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case MODE_STN_MONO_DUAL:
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case MODE_STN_COLOR_DUAL:
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case MODE_STN_MONO_SINGLE:
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case MODE_STN_COLOR_SINGLE:
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switch (jzfb.cfg & STN_DAT_PINMASK) {
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#define align2(n) (n)=((((n)+1)>>1)<<1)
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#define align4(n) (n)=((((n)+3)>>2)<<2)
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#define align8(n) (n)=((((n)+7)>>3)<<3)
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case STN_DAT_PIN1:
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/* Do not adjust the hori-param value. */
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break;
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case STN_DAT_PIN2:
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align2(jzfb.hsw);
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align2(jzfb.elw);
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align2(jzfb.blw);
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break;
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case STN_DAT_PIN4:
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align4(jzfb.hsw);
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align4(jzfb.elw);
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align4(jzfb.blw);
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break;
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case STN_DAT_PIN8:
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align8(jzfb.hsw);
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align8(jzfb.elw);
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align8(jzfb.blw);
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break;
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}
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break;
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}
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REG_LCD_CTRL = val;
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switch (jzfb.cfg & MODE_MASK) {
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case MODE_STN_MONO_DUAL:
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case MODE_STN_COLOR_DUAL:
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case MODE_STN_MONO_SINGLE:
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case MODE_STN_COLOR_SINGLE:
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if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
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((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
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stnH = jzfb.h >> 1;
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else
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stnH = jzfb.h;
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REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
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REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
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/* Screen setting */
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REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
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REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
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REG_LCD_DAV = (0 << 16) | (stnH);
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/* AC BIAs signal */
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REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
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break;
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case MODE_TFT_GEN:
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case MODE_TFT_SHARP:
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case MODE_TFT_CASIO:
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case MODE_TFT_SAMSUNG:
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case MODE_8BIT_SERIAL_TFT:
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case MODE_TFT_18BIT:
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REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
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REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
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#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
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REG_LCD_DAV = (0 << 16) | ( jzfb.h );
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#else
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REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
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#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
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REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
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REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
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| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
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break;
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}
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switch (jzfb.cfg & MODE_MASK) {
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case MODE_TFT_SAMSUNG:
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{
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unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
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unsigned int rev_s, rev_e, inv_s, inv_e;
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pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
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(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
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total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
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tp_s = jzfb.blw + jzfb.w + 1;
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tp_e = tp_s + 1;
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/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
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ckv_s = tp_s - pclk/(1000000000/4100);
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ckv_e = tp_s + total;
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rev_s = tp_s - 11; /* -11.5 clk */
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rev_e = rev_s + total;
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inv_s = tp_s;
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inv_e = inv_s + total;
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REG_LCD_CLS = (tp_s << 16) | tp_e;
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REG_LCD_PS = (ckv_s << 16) | ckv_e;
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REG_LCD_SPL = (rev_s << 16) | rev_e;
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REG_LCD_REV = (inv_s << 16) | inv_e;
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jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
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break;
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}
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case MODE_TFT_SHARP:
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{
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unsigned int total, cls_s, cls_e, ps_s, ps_e;
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unsigned int spl_s, spl_e, rev_s, rev_e;
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total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
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#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
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spl_s = 1;
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spl_e = spl_s + 1;
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cls_s = 0;
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cls_e = total - 60; /* > 4us (pclk = 80ns) */
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ps_s = cls_s;
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ps_e = cls_e;
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rev_s = total - 40; /* > 3us (pclk = 80ns) */
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rev_e = rev_s + total;
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jzfb.cfg |= STFT_PSHI;
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#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
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spl_s = total - 5; /* LD */
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spl_e = total -3;
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cls_s = 32; /* CKV */
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cls_e = 145;
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ps_s = 0; /* OEV */
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ps_e = 45;
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rev_s = 0; /* POL */
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rev_e = 0;
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#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
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REG_LCD_SPL = (spl_s << 16) | spl_e;
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REG_LCD_CLS = (cls_s << 16) | cls_e;
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REG_LCD_PS = (ps_s << 16) | ps_e;
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REG_LCD_REV = (rev_s << 16) | rev_e;
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break;
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}
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case MODE_TFT_CASIO:
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break;
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}
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/* Configure the LCD panel */
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REG_LCD_CFG = jzfb.cfg;
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/* Timing setting */
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__cpm_stop_lcd();
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val = jzfb.fclk; /* frame clk */
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if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
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pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
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(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
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}
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else {
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/* serial mode: Hsync period = 3*Width_Pixel */
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pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
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(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
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}
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if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
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((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
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pclk = (pclk * 3);
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if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
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((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
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((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
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((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
|
pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
|
|
|
|
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
|
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
|
pclk >>= 1;
|
|
|
|
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
|
|
pll_div = pll_div ? 1 : 2 ;
|
|
val = ( __cpm_get_pllout()/pll_div ) / pclk;
|
|
val--;
|
|
if ( val > 0x1ff ) {
|
|
printf("CPM_LPCDR too large, set it to 0x1ff\n");
|
|
val = 0x1ff;
|
|
}
|
|
__cpm_set_pixdiv(val);
|
|
|
|
val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
|
|
if ( val > 150000000 ) {
|
|
printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
|
|
printf("Change LCDClock to 150MHz\n");
|
|
val = 150000000;
|
|
}
|
|
val = ( __cpm_get_pllout()/pll_div ) / val;
|
|
val--;
|
|
if ( val > 0x1f ) {
|
|
printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
|
|
val = 0x1f;
|
|
}
|
|
__cpm_set_ldiv( val );
|
|
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
|
|
|
|
__cpm_start_lcd();
|
|
udelay(1000);
|
|
|
|
REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
|
|
|
|
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
|
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
|
REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
|
|
|
|
return 0;
|
|
}
|
|
|