mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 06:55:54 +02:00
4238a3aead
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@6276 3c298f89-4303-0410-b956-a3cf2f4a3e73
374 lines
8.3 KiB
C
374 lines
8.3 KiB
C
/*
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* Sonics Silicon Backplane
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* Bus scanning
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*
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* Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
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* Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
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* Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
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* Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
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* Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
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* Copyright (C) 2006 Broadcom Corporation.
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include "ssb_private.h"
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const char * ssb_core_name(u16 coreid)
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{
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switch (coreid) {
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case SSB_DEV_CHIPCOMMON:
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return "ChipCommon";
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case SSB_DEV_ILINE20:
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return "ILine 20";
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case SSB_DEV_SDRAM:
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return "SDRAM";
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case SSB_DEV_PCI:
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return "PCI";
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case SSB_DEV_MIPS:
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return "MIPS";
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case SSB_DEV_ETHERNET:
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return "Fast Ethernet";
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case SSB_DEV_V90:
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return "V90";
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case SSB_DEV_USB11_HOSTDEV:
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return "USB 1.1 Hostdev";
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case SSB_DEV_ADSL:
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return "ADSL";
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case SSB_DEV_ILINE100:
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return "ILine 100";
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case SSB_DEV_IPSEC:
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return "IPSEC";
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case SSB_DEV_PCMCIA:
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return "PCMCIA";
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case SSB_DEV_INTERNAL_MEM:
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return "Internal Memory";
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case SSB_DEV_MEMC_SDRAM:
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return "MEMC SDRAM";
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case SSB_DEV_EXTIF:
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return "EXTIF";
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case SSB_DEV_80211:
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return "IEEE 802.11";
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case SSB_DEV_MIPS_3302:
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return "MIPS 3302";
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case SSB_DEV_USB11_HOST:
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return "USB 1.1 Host";
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case SSB_DEV_USB11_DEV:
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return "USB 1.1 Device";
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case SSB_DEV_USB20_HOST:
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return "USB 2.0 Host";
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case SSB_DEV_USB20_DEV:
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return "USB 2.0 Device";
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case SSB_DEV_SDIO_HOST:
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return "SDIO Host";
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case SSB_DEV_ROBOSWITCH:
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return "Roboswitch";
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case SSB_DEV_PARA_ATA:
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return "PATA";
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case SSB_DEV_SATA_XORDMA:
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return "SATA XOR-DMA";
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case SSB_DEV_ETHERNET_GBIT:
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return "GBit Ethernet";
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case SSB_DEV_PCIE:
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return "PCI-E";
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case SSB_DEV_MIMO_PHY:
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return "MIMO PHY";
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case SSB_DEV_SRAM_CTRLR:
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return "SRAM Controller";
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case SSB_DEV_MINI_MACPHY:
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return "Mini MACPHY";
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case SSB_DEV_ARM_1176:
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return "ARM 1176";
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case SSB_DEV_ARM_7TDMI:
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return "ARM 7TDMI";
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}
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return "UNKNOWN";
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}
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static u16 pcidev_to_chipid(struct pci_dev *pci_dev)
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{
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u16 chipid_fallback = 0;
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switch (pci_dev->device) {
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case 0x4301:
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chipid_fallback = 0x4301;
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break;
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case 0x4305 ... 0x4307:
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chipid_fallback = 0x4307;
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break;
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case 0x4403:
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chipid_fallback = 0x4402;
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break;
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case 0x4610 ... 0x4615:
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chipid_fallback = 0x4610;
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break;
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case 0x4710 ... 0x4715:
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chipid_fallback = 0x4710;
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break;
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case 0x4320 ... 0x4325:
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chipid_fallback = 0x4309;
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break;
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case PCI_DEVICE_ID_BCM4401:
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case PCI_DEVICE_ID_BCM4401B0:
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case PCI_DEVICE_ID_BCM4401B1:
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chipid_fallback = 0x4401;
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break;
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default:
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ssb_printk(KERN_ERR PFX
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"PCI-ID not in fallback list\n");
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}
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return chipid_fallback;
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}
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static u8 chipid_to_nrcores(u16 chipid)
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{
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switch (chipid) {
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case 0x5365:
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return 7;
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case 0x4306:
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return 6;
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case 0x4310:
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return 8;
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case 0x4307:
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case 0x4301:
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return 5;
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case 0x4401:
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case 0x4402:
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return 3;
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case 0x4710:
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case 0x4610:
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case 0x4704:
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return 9;
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default:
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ssb_printk(KERN_ERR PFX
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"CHIPID not in nrcores fallback list\n");
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}
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return 1;
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}
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static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
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u16 offset)
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{
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switch (bus->bustype) {
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case SSB_BUSTYPE_SSB:
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offset += current_coreidx * SSB_CORE_SIZE;
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break;
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case SSB_BUSTYPE_PCI:
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break;
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case SSB_BUSTYPE_PCMCIA:
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if (offset >= 0x800) {
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ssb_pcmcia_switch_segment(bus, 1);
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offset -= 0x800;
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} else
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ssb_pcmcia_switch_segment(bus, 0);
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break;
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}
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return readl(bus->mmio + offset);
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}
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static int scan_switchcore(struct ssb_bus *bus, u8 coreidx)
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{
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switch (bus->bustype) {
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case SSB_BUSTYPE_SSB:
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break;
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case SSB_BUSTYPE_PCI:
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return ssb_pci_switch_coreidx(bus, coreidx);
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case SSB_BUSTYPE_PCMCIA:
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return ssb_pcmcia_switch_coreidx(bus, coreidx);
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}
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return 0;
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}
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void ssb_iounmap(struct ssb_bus *bus)
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{
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switch (bus->bustype) {
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case SSB_BUSTYPE_SSB:
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case SSB_BUSTYPE_PCMCIA:
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iounmap(bus->mmio);
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break;
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case SSB_BUSTYPE_PCI:
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pci_iounmap(bus->host_pci, bus->mmio);
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break;
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}
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bus->mmio = NULL;
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bus->mapped_device = NULL;
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}
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static void __iomem * ssb_ioremap(struct ssb_bus *bus,
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unsigned long baseaddr)
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{
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void __iomem *mmio = NULL;
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switch (bus->bustype) {
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case SSB_BUSTYPE_SSB:
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/* Only map the first core for now. */
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/* fallthrough... */
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case SSB_BUSTYPE_PCMCIA:
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mmio = ioremap(baseaddr, SSB_CORE_SIZE);
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break;
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case SSB_BUSTYPE_PCI:
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mmio = pci_iomap(bus->host_pci, 0, ~0UL);
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break;
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}
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return mmio;
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}
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int ssb_bus_scan(struct ssb_bus *bus,
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unsigned long baseaddr)
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{
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int err = -ENOMEM;
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void __iomem *mmio;
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u32 idhi, cc, rev, tmp;
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int i;
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struct ssb_device *dev;
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mmio = ssb_ioremap(bus, baseaddr);
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if (!mmio)
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goto out;
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bus->mmio = mmio;
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err = scan_switchcore(bus, 0); /* Switch to first core */
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if (err)
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goto err_unmap;
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idhi = scan_read32(bus, 0, SSB_IDHIGH);
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cc = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
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rev = (idhi & SSB_IDHIGH_RCLO);
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rev |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
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bus->nr_devices = 0;
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if (cc == SSB_DEV_CHIPCOMMON) {
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tmp = scan_read32(bus, 0, SSB_CHIPCO_CHIPID);
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bus->chip_id = (tmp & SSB_CHIPCO_IDMASK);
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bus->chip_rev = (tmp & SSB_CHIPCO_REVMASK) >>
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SSB_CHIPCO_REVSHIFT;
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bus->chip_package = (tmp & SSB_CHIPCO_PACKMASK) >>
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SSB_CHIPCO_PACKSHIFT;
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if (rev >= 4) {
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bus->nr_devices = (tmp & SSB_CHIPCO_NRCORESMASK) >>
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SSB_CHIPCO_NRCORESSHIFT;
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}
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tmp = scan_read32(bus, 0, SSB_CHIPCO_CAP);
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bus->chipco.capabilities = tmp;
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} else {
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if (bus->bustype == SSB_BUSTYPE_PCI) {
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bus->chip_id = pcidev_to_chipid(bus->host_pci);
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pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
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&bus->chip_rev);
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bus->chip_package = 0;
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} else {
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bus->chip_id = 0x4710;
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bus->chip_rev = 0;
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bus->chip_package = 0;
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}
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}
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if (!bus->nr_devices)
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bus->nr_devices = chipid_to_nrcores(bus->chip_id);
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if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
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ssb_printk(KERN_ERR PFX
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"More than %d ssb cores found (%d)\n",
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SSB_MAX_NR_CORES, bus->nr_devices);
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goto err_unmap;
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}
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if (bus->bustype == SSB_BUSTYPE_SSB) {
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/* Now that we know the number of cores,
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* remap the whole IO space for all cores.
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*/
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err = -ENOMEM;
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iounmap(mmio);
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mmio = ioremap(baseaddr, SSB_CORE_SIZE * bus->nr_devices);
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if (!mmio)
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goto out;
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bus->mmio = mmio;
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}
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/* Fetch basic information about each core/device */
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for (i = 0; i < bus->nr_devices; i++) {
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err = scan_switchcore(bus, i);
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if (err)
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goto err_unmap;
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dev = &(bus->devices[i]);
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idhi = scan_read32(bus, i, SSB_IDHIGH);
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dev->id.coreid = (idhi & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
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dev->id.revision = (idhi & SSB_IDHIGH_RCLO);
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dev->id.revision |= (idhi & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT;
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dev->id.vendor = (idhi & SSB_IDHIGH_VC) >> SSB_IDHIGH_VC_SHIFT;
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dev->core_index = i;
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dev->bus = bus;
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if ((dev->bus->bustype == SSB_BUSTYPE_PCI) && (bus->host_pci))
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dev->irq = bus->host_pci->irq;
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ssb_dprintk(KERN_INFO PFX
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"Core %d found: %s "
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"(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
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i, ssb_core_name(dev->id.coreid),
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dev->id.coreid, dev->id.revision, dev->id.vendor);
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dev->dev.bus = &ssb_bustype;
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snprintf(dev->dev.bus_id, sizeof(dev->dev.bus_id),
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"ssb%02x:%02x", bus->busnumber, i);
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switch (dev->id.coreid) {
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case SSB_DEV_EXTIF:
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#ifdef CONFIG_BCM947XX
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if (bus->extif.dev) {
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ssb_printk(KERN_WARNING PFX
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"WARNING: Multiple EXTIFs found\n");
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break;
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}
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bus->extif.dev = dev;
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#endif /* CONFIG_SSB_DRIVER_EXTIF */
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break;
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case SSB_DEV_CHIPCOMMON:
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if (bus->chipco.dev) {
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ssb_printk(KERN_WARNING PFX
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"WARNING: Multiple ChipCommon found\n");
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break;
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}
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bus->chipco.dev = dev;
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break;
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case SSB_DEV_MIPS:
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case SSB_DEV_MIPS_3302:
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#ifdef CONFIG_BCM947XX
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if (bus->mipscore.dev) {
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ssb_printk(KERN_WARNING PFX
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"WARNING: Multiple MIPS cores found\n");
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break;
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}
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bus->mipscore.dev = dev;
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#endif /* CONFIG_BCM947XX */
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break;
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case SSB_DEV_PCI:
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case SSB_DEV_PCIE:
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#ifdef CONFIG_SSB_DRIVER_PCICORE
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if (bus->pcicore.dev) {
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ssb_printk(KERN_WARNING PFX
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"WARNING: Multiple PCI(E) cores found\n");
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break;
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}
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bus->pcicore.dev = dev;
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#endif /* CONFIG_SSB_DRIVER_PCICORE */
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break;
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default:
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break;
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}
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}
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err = 0;
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out:
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return err;
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err_unmap:
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ssb_iounmap(bus);
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goto out;
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}
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