mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32588 3c298f89-4303-0410-b956-a3cf2f4a3e73
225 lines
7.1 KiB
Diff
225 lines
7.1 KiB
Diff
From 2b4e3da2e595e1c76f65f7da752ec1f037446bd2 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 2 Jul 2012 17:10:16 +0200
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Subject: [PATCH 09/20] ath9k: add mode register initialization code for AR9550
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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drivers/net/wireless/ath/ath9k/ar9003_hw.c | 86 ++++++++++++++++++++++++++-
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drivers/net/wireless/ath/ath9k/ar9003_phy.c | 61 +++++++++++++++++++-
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drivers/net/wireless/ath/ath9k/hw.h | 1 +
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3 files changed, 145 insertions(+), 3 deletions(-)
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--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
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@@ -328,7 +328,61 @@ static void ar9003_hw_init_mode_regs(str
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INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
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ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
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+ } else if (AR_SREV_9550(ah)) {
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+ /* mac */
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+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
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+ ar955x_1p0_mac_core,
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+ ARRAY_SIZE(ar955x_1p0_mac_core), 2);
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+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
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+ ar955x_1p0_mac_postamble,
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+ ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
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+
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+ /* bb */
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+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
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+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
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+ ar955x_1p0_baseband_core,
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+ ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
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+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
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+ ar955x_1p0_baseband_postamble,
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+ ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
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+
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+ /* radio */
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+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
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+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
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+ ar955x_1p0_radio_core,
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+ ARRAY_SIZE(ar955x_1p0_radio_core), 2);
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+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
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+ ar955x_1p0_radio_postamble,
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+ ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
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+
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+ /* soc */
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+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
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+ ar955x_1p0_soc_preamble,
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+ ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
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+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
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+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
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+ ar955x_1p0_soc_postamble,
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+ ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
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+ /* rx/tx gain */
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+ INIT_INI_ARRAY(&ah->iniModesRxGain,
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+ ar955x_1p0_common_wo_xlna_rx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
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+ 2);
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+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
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+ ar955x_1p0_common_wo_xlna_rx_gain_bounds,
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+ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
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+ 5);
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+ INIT_INI_ARRAY(&ah->iniModesTxGain,
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+ ar955x_1p0_modes_xpa_tx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
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+ 9);
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+
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+ /* Fast clock modal settings */
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+ INIT_INI_ARRAY(&ah->iniModesFastClock,
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+ ar955x_1p0_modes_fast_clock,
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+ ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
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} else if (AR_SREV_9580(ah)) {
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/* mac */
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INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
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@@ -471,6 +525,11 @@ static void ar9003_tx_gain_table_mode0(s
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ar9485_modes_lowest_ob_db_tx_gain_1_1,
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ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
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5);
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+ else if (AR_SREV_9550(ah))
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+ INIT_INI_ARRAY(&ah->iniModesTxGain,
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+ ar955x_1p0_modes_xpa_tx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
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+ 9);
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else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9580_1p0_lowest_ob_db_tx_gain_table,
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@@ -515,6 +574,11 @@ static void ar9003_tx_gain_table_mode1(s
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ar9580_1p0_high_ob_db_tx_gain_table,
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ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
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5);
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+ else if (AR_SREV_9550(ah))
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+ INIT_INI_ARRAY(&ah->iniModesTxGain,
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+ ar955x_1p0_modes_no_xpa_tx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
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+ 9);
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else if (AR_SREV_9462_20(ah))
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9462_modes_high_ob_db_tx_gain_table_2p0,
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@@ -636,7 +700,16 @@ static void ar9003_rx_gain_table_mode0(s
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ar9485Common_wo_xlna_rx_gain_1_1,
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ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
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2);
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- else if (AR_SREV_9580(ah))
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+ else if (AR_SREV_9550(ah)) {
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+ INIT_INI_ARRAY(&ah->iniModesRxGain,
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+ ar955x_1p0_common_rx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
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+ 2);
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+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
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+ ar955x_1p0_common_rx_gain_bounds,
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+ ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
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+ 5);
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+ } else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_rx_gain_table,
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ARRAY_SIZE(ar9580_1p0_rx_gain_table),
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@@ -680,7 +753,16 @@ static void ar9003_rx_gain_table_mode1(s
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ar9462_common_wo_xlna_rx_gain_table_2p0,
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ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
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2);
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- else if (AR_SREV_9580(ah))
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+ else if (AR_SREV_9550(ah)) {
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+ INIT_INI_ARRAY(&ah->iniModesRxGain,
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+ ar955x_1p0_common_wo_xlna_rx_gain_table,
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+ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
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+ 2);
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+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
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+ ar955x_1p0_common_wo_xlna_rx_gain_bounds,
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+ ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
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+ 5);
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+ } else if (AR_SREV_9580(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9580_1p0_wo_xlna_rx_gain_table,
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ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
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--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
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@@ -620,6 +620,50 @@ static void ar9003_hw_prog_ini(struct at
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}
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}
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+static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
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+ struct ath9k_channel *chan)
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+{
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+ int ret;
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+
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+ switch (chan->chanmode) {
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+ case CHANNEL_A:
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+ case CHANNEL_A_HT20:
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+ if (chan->channel <= 5350)
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+ ret = 1;
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+ else if ((chan->channel > 5350) && (chan->channel <= 5600))
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+ ret = 3;
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+ else
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+ ret = 5;
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+ break;
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+
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+ case CHANNEL_A_HT40PLUS:
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+ case CHANNEL_A_HT40MINUS:
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+ if (chan->channel <= 5350)
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+ ret = 2;
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+ else if ((chan->channel > 5350) && (chan->channel <= 5600))
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+ ret = 4;
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+ else
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+ ret = 6;
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+ break;
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+
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+ case CHANNEL_G:
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+ case CHANNEL_G_HT20:
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+ case CHANNEL_B:
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+ ret = 8;
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+ break;
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+
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+ case CHANNEL_G_HT40PLUS:
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+ case CHANNEL_G_HT40MINUS:
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+ ret = 7;
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+ break;
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+
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+ default:
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+ ret = -EINVAL;
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+ }
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+
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+ return ret;
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+}
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+
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static int ar9003_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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@@ -661,7 +705,22 @@ static int ar9003_hw_process_ini(struct
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}
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REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
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- REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
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+ if (AR_SREV_9550(ah))
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+ REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
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+ regWrites);
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+
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+ if (AR_SREV_9550(ah)) {
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+ int modes_txgain_index;
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+
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+ modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
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+ if (modes_txgain_index < 0)
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+ return -EINVAL;
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+
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+ REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
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+ regWrites);
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+ } else {
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+ REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
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+ }
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/*
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* For 5GHz channels requiring Fast Clock, apply
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--- a/drivers/net/wireless/ath/ath9k/hw.h
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+++ b/drivers/net/wireless/ath/ath9k/hw.h
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@@ -820,6 +820,7 @@ struct ath_hw {
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struct ar5416IniArray iniModesFastClock;
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struct ar5416IniArray iniAdditional;
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struct ar5416IniArray iniModesRxGain;
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+ struct ar5416IniArray ini_modes_rx_gain_bounds;
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struct ar5416IniArray iniModesTxGain;
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struct ar5416IniArray iniCckfirNormal;
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struct ar5416IniArray iniCckfirJapan2484;
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