mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e0e5bd88de
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22463 3c298f89-4303-0410-b956-a3cf2f4a3e73
243 lines
7.1 KiB
Diff
243 lines
7.1 KiB
Diff
From 2b3ca15058c974f2c20bd057a58a10c414b83fef Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 17 Jul 2010 11:07:51 +0000
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Subject: [PATCH] MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip
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Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
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It also adds the iomem addresses for the different components found on
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a JZ4740 SoC.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/1464/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/bootinfo.h | 6 ++
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arch/mips/include/asm/cpu.h | 9 +++-
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arch/mips/include/asm/mach-jz4740/base.h | 26 ++++++++++
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.../asm/mach-jz4740/cpu-feature-overrides.h | 51 ++++++++++++++++++++
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arch/mips/include/asm/mach-jz4740/war.h | 25 ++++++++++
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arch/mips/kernel/cpu-probe.c | 20 ++++++++
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arch/mips/mm/tlbex.c | 5 ++
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7 files changed, 141 insertions(+), 1 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-jz4740/base.h
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create mode 100644 arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
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create mode 100644 arch/mips/include/asm/mach-jz4740/war.h
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--- a/arch/mips/include/asm/bootinfo.h
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+++ b/arch/mips/include/asm/bootinfo.h
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@@ -71,6 +71,12 @@
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#define MACH_LEMOTE_LL2F 7
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#define MACH_LOONGSON_END 8
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+/*
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+ * Valid machtype for group INGENIC
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+ */
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+#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
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+#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
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+
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extern char *system_type;
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const char *get_system_type(void);
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--- a/arch/mips/include/asm/cpu.h
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+++ b/arch/mips/include/asm/cpu.h
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@@ -34,7 +34,7 @@
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#define PRID_COMP_LSI 0x080000
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#define PRID_COMP_LEXRA 0x0b0000
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#define PRID_COMP_CAVIUM 0x0d0000
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-
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+#define PRID_COMP_INGENIC 0xd00000
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/*
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* Assigned values for the product ID register. In order to detect a
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@@ -133,6 +133,12 @@
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#define PRID_IMP_CAVIUM_CN52XX 0x0700
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/*
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+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
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+ */
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+
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+#define PRID_IMP_JZRISC 0x0200
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+
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+/*
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* Definitions for 7:0 on legacy processors
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*/
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@@ -219,6 +225,7 @@ enum cpu_type_enum {
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
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+ CPU_JZRISC,
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/*
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* MIPS64 class processors
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/base.h
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@@ -0,0 +1,26 @@
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+#ifndef __ASM_MACH_JZ4740_BASE_H__
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+#define __ASM_MACH_JZ4740_BASE_H__
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+
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+#define JZ4740_CPM_BASE_ADDR 0x10000000
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+#define JZ4740_INTC_BASE_ADDR 0x10001000
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+#define JZ4740_WDT_BASE_ADDR 0x10002000
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+#define JZ4740_TCU_BASE_ADDR 0x10002010
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+#define JZ4740_RTC_BASE_ADDR 0x10003000
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+#define JZ4740_GPIO_BASE_ADDR 0x10010000
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+#define JZ4740_AIC_BASE_ADDR 0x10020000
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+#define JZ4740_MSC_BASE_ADDR 0x10021000
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+#define JZ4740_UART0_BASE_ADDR 0x10030000
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+#define JZ4740_UART1_BASE_ADDR 0x10031000
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+#define JZ4740_I2C_BASE_ADDR 0x10042000
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+#define JZ4740_SSI_BASE_ADDR 0x10043000
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+#define JZ4740_SADC_BASE_ADDR 0x10070000
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+#define JZ4740_EMC_BASE_ADDR 0x13010000
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+#define JZ4740_DMAC_BASE_ADDR 0x13020000
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+#define JZ4740_UHC_BASE_ADDR 0x13030000
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+#define JZ4740_UDC_BASE_ADDR 0x13040000
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+#define JZ4740_LCD_BASE_ADDR 0x13050000
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+#define JZ4740_SLCD_BASE_ADDR 0x13050000
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+#define JZ4740_CIM_BASE_ADDR 0x13060000
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+#define JZ4740_IPU_BASE_ADDR 0x13080000
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
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@@ -0,0 +1,51 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ */
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+#ifndef __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
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+#define __ASM_MACH_JZ4740_CPU_FEATURE_OVERRIDES_H
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+
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+#define cpu_has_tlb 1
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+#define cpu_has_4kex 1
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+#define cpu_has_3k_cache 0
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+#define cpu_has_4k_cache 1
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+#define cpu_has_tx39_cache 0
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+#define cpu_has_fpu 0
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+#define cpu_has_32fpr 0
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+#define cpu_has_counter 0
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+#define cpu_has_watch 1
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+#define cpu_has_divec 1
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+#define cpu_has_vce 0
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+#define cpu_has_cache_cdex_p 0
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+#define cpu_has_cache_cdex_s 0
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+#define cpu_has_prefetch 1
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+#define cpu_has_mcheck 1
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+#define cpu_has_ejtag 1
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+#define cpu_has_llsc 1
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+#define cpu_has_mips16 0
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+#define cpu_has_mdmx 0
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+#define cpu_has_mips3d 0
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+#define cpu_has_smartmips 0
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+#define kernel_uses_llsc 1
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+#define cpu_has_vtag_icache 1
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+#define cpu_has_dc_aliases 0
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+#define cpu_has_ic_fills_f_dc 0
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+#define cpu_has_pindexed_dcache 0
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+#define cpu_has_mips32r1 1
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+#define cpu_has_mips32r2 0
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+#define cpu_has_mips64r1 0
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+#define cpu_has_mips64r2 0
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+#define cpu_has_dsp 0
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+#define cpu_has_mipsmt 0
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+#define cpu_has_userlocal 0
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+#define cpu_has_nofpuex 0
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+#define cpu_has_64bits 0
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+#define cpu_has_64bit_zero_reg 0
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+#define cpu_has_inclusive_pcaches 0
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+
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+#define cpu_dcache_line_size() 32
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+#define cpu_icache_line_size() 32
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/war.h
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@@ -0,0 +1,25 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
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+ */
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+#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
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+#define __ASM_MIPS_MACH_JZ4740_WAR_H
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+
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+#define R4600_V1_INDEX_ICACHEOP_WAR 0
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+#define R4600_V1_HIT_CACHEOP_WAR 0
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+#define R4600_V2_HIT_CACHEOP_WAR 0
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+#define R5432_CP0_INTERRUPT_WAR 0
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+#define BCM1250_M3_WAR 0
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+#define SIBYTE_1956_WAR 0
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+#define MIPS4K_ICACHE_REFILL_WAR 0
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+#define MIPS_CACHE_SYNC_WAR 0
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+#define TX49XX_ICACHE_INDEX_INV_WAR 0
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+#define RM9000_CDEX_SMP_WAR 0
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+#define ICACHE_REFILLS_WORKAROUND_WAR 0
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+#define R10000_LLSC_WAR 0
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+#define MIPS34K_MISSED_ITLB_WAR 0
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+
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+#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -187,6 +187,7 @@ void __init check_wait(void)
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case CPU_BCM6358:
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case CPU_CAVIUM_OCTEON:
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case CPU_CAVIUM_OCTEON_PLUS:
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+ case CPU_JZRISC:
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cpu_wait = r4k_wait;
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break;
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@@ -956,6 +957,22 @@ platform:
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}
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}
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+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
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+{
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+ decode_configs(c);
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+ /* JZRISC does not implement the CP0 counter. */
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+ c->options &= ~MIPS_CPU_COUNTER;
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+ switch (c->processor_id & 0xff00) {
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+ case PRID_IMP_JZRISC:
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+ c->cputype = CPU_JZRISC;
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+ __cpu_name[cpu] = "Ingenic JZRISC";
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+ break;
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+ default:
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+ panic("Unknown Ingenic Processor ID!");
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+ break;
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+ }
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+}
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+
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const char *__cpu_name[NR_CPUS];
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const char *__elf_platform;
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@@ -994,6 +1011,9 @@ __cpuinit void cpu_probe(void)
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case PRID_COMP_CAVIUM:
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cpu_probe_cavium(c, cpu);
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break;
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+ case PRID_COMP_INGENIC:
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+ cpu_probe_ingenic(c, cpu);
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+ break;
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}
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BUG_ON(!__cpu_name[cpu]);
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_en
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tlbw(p);
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break;
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+ case CPU_JZRISC:
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+ tlbw(p);
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+ uasm_i_nop(p);
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+ break;
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+
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default:
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panic("No TLB refill handler yet (CPU type: %d)",
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current_cpu_data.cputype);
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