mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-28 22:03:18 +02:00
21b6860b2b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17227 3c298f89-4303-0410-b956-a3cf2f4a3e73
399 lines
12 KiB
C
399 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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const unsigned long *bcm63xx_regs_base;
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EXPORT_SYMBOL(bcm63xx_regs_base);
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const int *bcm63xx_irqs;
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EXPORT_SYMBOL(bcm63xx_irqs);
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const unsigned long *bcm63xx_regs_spi;
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EXPORT_SYMBOL(bcm63xx_regs_spi);
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static u16 bcm63xx_cpu_id;
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static u16 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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/*
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* 6338 register sets and irqs
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*/
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static const unsigned long bcm96338_regs_base[] = {
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[RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
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[RSET_PERF] = BCM_6338_PERF_BASE,
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[RSET_TIMER] = BCM_6338_TIMER_BASE,
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[RSET_WDT] = BCM_6338_WDT_BASE,
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[RSET_UART0] = BCM_6338_UART0_BASE,
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[RSET_GPIO] = BCM_6338_GPIO_BASE,
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[RSET_SPI] = BCM_6338_SPI_BASE,
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[RSET_OHCI0] = BCM_6338_OHCI0_BASE,
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[RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
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[RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
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[RSET_UDC0] = BCM_6338_UDC0_BASE,
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[RSET_MPI] = BCM_6338_MPI_BASE,
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[RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
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[RSET_SDRAM] = BCM_6338_SDRAM_BASE,
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[RSET_DSL] = BCM_6338_DSL_BASE,
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[RSET_ENET0] = BCM_6338_ENET0_BASE,
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[RSET_ENET1] = BCM_6338_ENET1_BASE,
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[RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
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[RSET_MEMC] = BCM_6338_MEMC_BASE,
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[RSET_DDR] = BCM_6338_DDR_BASE,
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};
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static const int bcm96338_irqs[] = {
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[IRQ_TIMER] = BCM_6338_TIMER_IRQ,
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[IRQ_SPI] = BCM_6338_SPI_IRQ,
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[IRQ_UART0] = BCM_6338_UART0_IRQ,
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[IRQ_DSL] = BCM_6338_DSL_IRQ,
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[IRQ_UDC0] = BCM_6338_UDC0_IRQ,
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[IRQ_ENET0] = BCM_6338_ENET0_IRQ,
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[IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
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[IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
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};
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static const unsigned long bcm96338_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6338_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6338_SPI_ST,
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[SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
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};
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/*
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* 6345 register sets and irqs
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*/
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static const unsigned long bcm96345_regs_base[] = {
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[RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
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[RSET_PERF] = BCM_6345_PERF_BASE,
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[RSET_TIMER] = BCM_6345_TIMER_BASE,
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[RSET_WDT] = BCM_6345_WDT_BASE,
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[RSET_UART0] = BCM_6345_UART0_BASE,
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[RSET_GPIO] = BCM_6345_GPIO_BASE,
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[RSET_SPI] = BCM_6345_SPI_BASE,
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[RSET_UDC0] = BCM_6345_UDC0_BASE,
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[RSET_OHCI0] = BCM_6345_OHCI0_BASE,
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[RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
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[RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
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[RSET_MPI] = BCM_6345_MPI_BASE,
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[RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
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[RSET_DSL] = BCM_6345_DSL_BASE,
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[RSET_ENET0] = BCM_6345_ENET0_BASE,
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[RSET_ENET1] = BCM_6345_ENET1_BASE,
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[RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
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[RSET_EHCI0] = BCM_6345_EHCI0_BASE,
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[RSET_SDRAM] = BCM_6345_SDRAM_BASE,
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[RSET_MEMC] = BCM_6345_MEMC_BASE,
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[RSET_DDR] = BCM_6345_DDR_BASE,
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};
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static const int bcm96345_irqs[] = {
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[IRQ_TIMER] = BCM_6345_TIMER_IRQ,
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[IRQ_UART0] = BCM_6345_UART0_IRQ,
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[IRQ_DSL] = BCM_6345_DSL_IRQ,
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[IRQ_UDC0] = BCM_6345_UDC0_IRQ,
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[IRQ_ENET0] = BCM_6345_ENET0_IRQ,
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[IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
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[IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
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};
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/*
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* 6348 register sets and irqs
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*/
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static const unsigned long bcm96348_regs_base[] = {
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[RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
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[RSET_PERF] = BCM_6348_PERF_BASE,
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[RSET_TIMER] = BCM_6348_TIMER_BASE,
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[RSET_WDT] = BCM_6348_WDT_BASE,
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[RSET_UART0] = BCM_6348_UART0_BASE,
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[RSET_GPIO] = BCM_6348_GPIO_BASE,
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[RSET_SPI] = BCM_6348_SPI_BASE,
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[RSET_OHCI0] = BCM_6348_OHCI0_BASE,
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[RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
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[RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
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[RSET_UDC0] = BCM_6348_UDC0_BASE,
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[RSET_MPI] = BCM_6348_MPI_BASE,
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[RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
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[RSET_SDRAM] = BCM_6348_SDRAM_BASE,
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[RSET_DSL] = BCM_6348_DSL_BASE,
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[RSET_ENET0] = BCM_6348_ENET0_BASE,
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[RSET_ENET1] = BCM_6348_ENET1_BASE,
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[RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
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[RSET_MEMC] = BCM_6348_MEMC_BASE,
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[RSET_DDR] = BCM_6348_DDR_BASE,
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};
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static const int bcm96348_irqs[] = {
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[IRQ_TIMER] = BCM_6348_TIMER_IRQ,
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[IRQ_SPI] = BCM_6348_SPI_IRQ,
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[IRQ_UART0] = BCM_6348_UART0_IRQ,
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[IRQ_DSL] = BCM_6348_DSL_IRQ,
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[IRQ_UDC0] = BCM_6348_UDC0_IRQ,
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[IRQ_ENET0] = BCM_6348_ENET0_IRQ,
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[IRQ_ENET1] = BCM_6348_ENET1_IRQ,
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[IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
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[IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
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[IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
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[IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
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[IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
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[IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
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[IRQ_PCI] = BCM_6348_PCI_IRQ,
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};
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static const unsigned long bcm96348_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6348_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6348_SPI_ST,
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[SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
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};
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/*
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* 6358 register sets and irqs
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*/
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static const unsigned long bcm96358_regs_base[] = {
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[RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
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[RSET_PERF] = BCM_6358_PERF_BASE,
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[RSET_TIMER] = BCM_6358_TIMER_BASE,
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[RSET_WDT] = BCM_6358_WDT_BASE,
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[RSET_UART0] = BCM_6358_UART0_BASE,
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[RSET_GPIO] = BCM_6358_GPIO_BASE,
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[RSET_SPI] = BCM_6358_SPI_BASE,
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[RSET_OHCI0] = BCM_6358_OHCI0_BASE,
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[RSET_EHCI0] = BCM_6358_EHCI0_BASE,
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[RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
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[RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
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[RSET_MPI] = BCM_6358_MPI_BASE,
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[RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
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[RSET_SDRAM] = BCM_6358_SDRAM_BASE,
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[RSET_DSL] = BCM_6358_DSL_BASE,
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[RSET_ENET0] = BCM_6358_ENET0_BASE,
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[RSET_ENET1] = BCM_6358_ENET1_BASE,
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[RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
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[RSET_MEMC] = BCM_6358_MEMC_BASE,
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[RSET_DDR] = BCM_6358_DDR_BASE,
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};
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static const int bcm96358_irqs[] = {
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[IRQ_TIMER] = BCM_6358_TIMER_IRQ,
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[IRQ_SPI] = BCM_6358_SPI_IRQ,
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[IRQ_UART0] = BCM_6358_UART0_IRQ,
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[IRQ_DSL] = BCM_6358_DSL_IRQ,
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[IRQ_ENET0] = BCM_6358_ENET0_IRQ,
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[IRQ_ENET1] = BCM_6358_ENET1_IRQ,
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[IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
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[IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
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[IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
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[IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
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[IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
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[IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
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[IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
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[IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
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[IRQ_PCI] = BCM_6358_PCI_IRQ,
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};
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static const unsigned long bcm96358_regs_spi[] = {
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[SPI_CMD] = SPI_BCM_6358_SPI_CMD,
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[SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
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[SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
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[SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
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[SPI_ST] = SPI_BCM_6358_SPI_STATUS,
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[SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
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[SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
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[SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
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[SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
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[SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
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[SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
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[SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
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};
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u16 __bcm63xx_get_cpu_id(void)
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{
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return bcm63xx_cpu_id;
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}
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EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
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u16 bcm63xx_get_cpu_rev(void)
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{
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return bcm63xx_cpu_rev;
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}
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EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
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unsigned int bcm63xx_get_cpu_freq(void)
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{
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return bcm63xx_cpu_freq;
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}
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unsigned int bcm63xx_get_memory_size(void)
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{
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return bcm63xx_memory_size;
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}
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static unsigned int detect_cpu_clock(void)
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{
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unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
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if (BCMCPU_IS_6338())
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return 240000000;
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if (BCMCPU_IS_6345())
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return 140000000;
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/*
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* frequency depends on PLL configuration:
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*/
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if (BCMCPU_IS_6348()) {
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/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
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tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
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n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
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n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
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m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
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n1 += 1;
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n2 += 2;
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m1 += 1;
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}
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if (BCMCPU_IS_6358()) {
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/* 16MHz * N1 * N2 / M1_CPU */
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tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
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n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
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n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
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m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
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}
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return (16 * 1000000 * n1 * n2) / m1;
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}
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/*
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* attempt to detect the amount of memory installed
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*/
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static unsigned int detect_memory_size(void)
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{
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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if (BCMCPU_IS_6345())
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return (8 * 1024 * 1024);
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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val = bcm_sdram_readl(SDRAM_CFG_REG);
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rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
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cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
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is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
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banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
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}
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if (BCMCPU_IS_6358()) {
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val = bcm_memc_readl(MEMC_CFG_REG);
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rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
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cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
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is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
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banks = 2;
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}
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/* 0 => 11 address bits ... 2 => 13 address bits */
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rows += 11;
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/* 0 => 8 address bits ... 2 => 10 address bits */
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cols += 8;
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return 1 << (cols + rows + (is_32bits + 1) + banks);
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}
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void __init bcm63xx_cpu_init(void)
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{
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unsigned int tmp, expected_cpu_id;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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/* soc registers location depends on cpu type */
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expected_cpu_id = 0;
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switch (c->cputype) {
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case CPU_BCM3302:
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expected_cpu_id = BCM6338_CPU_ID;
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bcm63xx_regs_base = bcm96338_regs_base;
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bcm63xx_irqs = bcm96338_irqs;
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bcm63xx_regs_spi = bcm96338_regs_spi;
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break;
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case CPU_BCM6345:
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expected_cpu_id = BCM6345_CPU_ID;
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bcm63xx_regs_base = bcm96345_regs_base;
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bcm63xx_irqs = bcm96345_irqs;
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break;
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case CPU_BCM6348:
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expected_cpu_id = BCM6348_CPU_ID;
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bcm63xx_regs_base = bcm96348_regs_base;
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bcm63xx_irqs = bcm96348_irqs;
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bcm63xx_regs_spi = bcm96348_regs_spi;
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break;
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case CPU_BCM6358:
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm96358_regs_base;
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bcm63xx_irqs = bcm96358_irqs;
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bcm63xx_regs_spi = bcm96358_regs_spi;
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break;
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}
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/* really early to panic, but delaying panic would not help
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|
* since we will never get any working console */
|
|
if (!expected_cpu_id)
|
|
panic("unsupported Broadcom CPU");
|
|
|
|
/*
|
|
* bcm63xx_regs_base is set, we can access soc registers
|
|
*/
|
|
|
|
/* double check CPU type */
|
|
tmp = bcm_perf_readl(PERF_REV_REG);
|
|
bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
|
|
bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
|
|
|
|
if (bcm63xx_cpu_id != expected_cpu_id)
|
|
panic("bcm63xx CPU id mismatch");
|
|
|
|
bcm63xx_cpu_freq = detect_cpu_clock();
|
|
bcm63xx_memory_size = detect_memory_size();
|
|
|
|
printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
|
|
bcm63xx_cpu_id, bcm63xx_cpu_rev);
|
|
printk(KERN_INFO "CPU frequency is %u Hz\n",
|
|
bcm63xx_cpu_freq);
|
|
printk(KERN_INFO "%uMB of RAM installed\n",
|
|
bcm63xx_memory_size >> 20);
|
|
}
|