mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e0e5bd88de
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22463 3c298f89-4303-0410-b956-a3cf2f4a3e73
405 lines
11 KiB
Diff
405 lines
11 KiB
Diff
From ced95a5a9d7a3ba168e8518d9b5004c9a0cad1fe Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 19 Jun 2010 04:08:14 +0000
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Subject: [PATCH] MIPS: JZ4740: Add DMA support.
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Add support for DMA transfers on JZ4740 SoCs.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Cc: linux-mips@linux-mips.org
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Cc: linux-kernel@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/1401/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/include/asm/mach-jz4740/dma.h | 90 ++++++++++
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arch/mips/jz4740/dma.c | 289 +++++++++++++++++++++++++++++++
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2 files changed, 379 insertions(+), 0 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-jz4740/dma.h
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create mode 100644 arch/mips/jz4740/dma.c
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-jz4740/dma.h
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@@ -0,0 +1,90 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ7420/JZ4740 DMA definitions
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#ifndef __ASM_MACH_JZ4740_DMA_H__
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+#define __ASM_MACH_JZ4740_DMA_H__
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+
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+struct jz4740_dma_chan;
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+
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+enum jz4740_dma_request_type {
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+ JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
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+ JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
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+ JZ4740_DMA_TYPE_UART_RECEIVE = 21,
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+ JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
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+ JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
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+ JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
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+ JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
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+ JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
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+ JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
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+ JZ4740_DMA_TYPE_TCU = 28,
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+ JZ4740_DMA_TYPE_SADC = 29,
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+ JZ4740_DMA_TYPE_SLCD = 30,
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+};
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+
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+enum jz4740_dma_width {
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+ JZ4740_DMA_WIDTH_32BIT = 0,
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+ JZ4740_DMA_WIDTH_8BIT = 1,
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+ JZ4740_DMA_WIDTH_16BIT = 2,
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+};
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+
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+enum jz4740_dma_transfer_size {
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+ JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
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+ JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
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+ JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
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+ JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
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+ JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
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+};
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+
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+enum jz4740_dma_flags {
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+ JZ4740_DMA_SRC_AUTOINC = 0x2,
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+ JZ4740_DMA_DST_AUTOINC = 0x1,
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+};
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+
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+enum jz4740_dma_mode {
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+ JZ4740_DMA_MODE_SINGLE = 0,
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+ JZ4740_DMA_MODE_BLOCK = 1,
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+};
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+
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+struct jz4740_dma_config {
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+ enum jz4740_dma_width src_width;
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+ enum jz4740_dma_width dst_width;
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+ enum jz4740_dma_transfer_size transfer_size;
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+ enum jz4740_dma_request_type request_type;
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+ enum jz4740_dma_flags flags;
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+ enum jz4740_dma_mode mode;
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+};
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+
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+typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
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+
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+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
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+void jz4740_dma_free(struct jz4740_dma_chan *dma);
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+
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+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
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+ const struct jz4740_dma_config *config);
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+
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+
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+void jz4740_dma_enable(struct jz4740_dma_chan *dma);
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+void jz4740_dma_disable(struct jz4740_dma_chan *dma);
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+
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+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
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+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
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+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
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+
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+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
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+
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+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
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+ jz4740_dma_complete_callback_t cb);
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+
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+#endif /* __ASM_JZ4740_DMA_H__ */
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--- /dev/null
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+++ b/arch/mips/jz4740/dma.c
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@@ -0,0 +1,289 @@
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+/*
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+ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 SoC DMA support
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/spinlock.h>
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+#include <linux/interrupt.h>
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+
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+#include <linux/dma-mapping.h>
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+#include <asm/mach-jz4740/dma.h>
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+#include <asm/mach-jz4740/base.h>
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+
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+#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
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+#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
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+#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
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+#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
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+#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
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+#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
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+#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
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+
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+#define JZ_REG_DMA_CTRL 0x300
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+#define JZ_REG_DMA_IRQ 0x304
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+#define JZ_REG_DMA_DOORBELL 0x308
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+#define JZ_REG_DMA_DOORBELL_SET 0x30C
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+
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+#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
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+#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
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+#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
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+#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
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+#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
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+#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
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+#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
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+
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+#define JZ_DMA_CMD_SRC_INC BIT(23)
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+#define JZ_DMA_CMD_DST_INC BIT(22)
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+#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
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+#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
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+#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
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+#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
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+#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
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+#define JZ_DMA_CMD_DESC_VALID BIT(4)
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+#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
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+#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
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+#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
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+#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
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+
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+#define JZ_DMA_CMD_FLAGS_OFFSET 22
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+#define JZ_DMA_CMD_RDIL_OFFSET 16
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+#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
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+#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
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+#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
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+#define JZ_DMA_CMD_MODE_OFFSET 7
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+
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+#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
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+#define JZ_DMA_CTRL_HALT BIT(3)
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+#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
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+#define JZ_DMA_CTRL_ENABLE BIT(0)
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+
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+
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+static void __iomem *jz4740_dma_base;
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+static spinlock_t jz4740_dma_lock;
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+
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+static inline uint32_t jz4740_dma_read(size_t reg)
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+{
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+ return readl(jz4740_dma_base + reg);
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+}
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+
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+static inline void jz4740_dma_write(size_t reg, uint32_t val)
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+{
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+ writel(val, jz4740_dma_base + reg);
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+}
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+
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+static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
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+{
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+ uint32_t val2;
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+ val2 = jz4740_dma_read(reg);
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+ val2 &= ~mask;
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+ val2 |= val;
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+ jz4740_dma_write(reg, val2);
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+}
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+
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+struct jz4740_dma_chan {
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+ unsigned int id;
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+ void *dev;
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+ const char *name;
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+
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+ enum jz4740_dma_flags flags;
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+ uint32_t transfer_shift;
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+
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+ jz4740_dma_complete_callback_t complete_cb;
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+
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+ unsigned used:1;
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+};
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+
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+#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
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+
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+struct jz4740_dma_chan jz4740_dma_channels[] = {
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+ JZ4740_DMA_CHANNEL(0),
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+ JZ4740_DMA_CHANNEL(1),
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+ JZ4740_DMA_CHANNEL(2),
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+ JZ4740_DMA_CHANNEL(3),
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+ JZ4740_DMA_CHANNEL(4),
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+ JZ4740_DMA_CHANNEL(5),
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+};
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+
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+struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
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+{
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+ unsigned int i;
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+ struct jz4740_dma_chan *dma = NULL;
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+
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+ spin_lock(&jz4740_dma_lock);
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+
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+ for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
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+ if (!jz4740_dma_channels[i].used) {
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+ dma = &jz4740_dma_channels[i];
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+ dma->used = 1;
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+ break;
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+ }
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+ }
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+
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+ spin_unlock(&jz4740_dma_lock);
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+
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+ if (!dma)
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+ return NULL;
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+
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+ dma->dev = dev;
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+ dma->name = name;
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+
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+ return dma;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_request);
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+
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+void jz4740_dma_configure(struct jz4740_dma_chan *dma,
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+ const struct jz4740_dma_config *config)
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+{
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+ uint32_t cmd;
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+
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+ switch (config->transfer_size) {
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+ case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
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+ dma->transfer_shift = 1;
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+ break;
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+ case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
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+ dma->transfer_shift = 2;
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+ break;
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+ case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
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+ dma->transfer_shift = 4;
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+ break;
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+ case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
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+ dma->transfer_shift = 5;
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+ break;
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+ default:
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+ dma->transfer_shift = 0;
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+ break;
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+ }
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+
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+ cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
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+ cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
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+ cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
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+ cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
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+ cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
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+ cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
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+
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+ jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
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+ jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
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+ jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_configure);
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+
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+void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
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+{
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+ jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
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+
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+void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
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+{
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+ jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
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+
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+void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
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+{
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+ count >>= dma->transfer_shift;
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+ jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
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+
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+void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
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+ jz4740_dma_complete_callback_t cb)
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+{
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+ dma->complete_cb = cb;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
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+
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+void jz4740_dma_free(struct jz4740_dma_chan *dma)
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+{
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+ dma->dev = NULL;
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+ dma->complete_cb = NULL;
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+ dma->used = 0;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_free);
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+
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+void jz4740_dma_enable(struct jz4740_dma_chan *dma)
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+{
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+ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
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+ JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
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+ JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
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+ JZ_DMA_STATUS_CTRL_ENABLE);
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+
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+ jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
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+ JZ_DMA_CTRL_ENABLE,
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+ JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_enable);
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+
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+void jz4740_dma_disable(struct jz4740_dma_chan *dma)
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+{
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+ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
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+ JZ_DMA_STATUS_CTRL_ENABLE);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_disable);
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+
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+uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
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+{
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+ uint32_t residue;
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+ residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
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+ return residue << dma->transfer_shift;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
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+
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+static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
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+{
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+ uint32_t status;
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+
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+ status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
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+
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+ jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
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+ JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
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+
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+ if (dma->complete_cb)
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+ dma->complete_cb(dma, 0, dma->dev);
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+}
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+
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+static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
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+{
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+ uint32_t irq_status;
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+ unsigned int i;
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+
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+ irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
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+
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+ for (i = 0; i < 6; ++i) {
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+ if (irq_status & (1 << i))
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+ jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int jz4740_dma_init(void)
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+{
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+ unsigned int ret;
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+
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+ jz4740_dma_base = ioremap(JZ4740_DMAC_BASE_ADDR, 0x400);
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+
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+ if (!jz4740_dma_base)
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+ return -EBUSY;
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+
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+ spin_lock_init(&jz4740_dma_lock);
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+
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+ ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
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+
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+ if (ret)
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+ printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
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+
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+ return ret;
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+}
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+arch_initcall(jz4740_dma_init);
|