mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 17:02:05 +03:00
0942258e05
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27565 3c298f89-4303-0410-b956-a3cf2f4a3e73
118 lines
4.0 KiB
Diff
118 lines
4.0 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
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+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
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@@ -499,45 +499,6 @@ void ar9002_hw_enable_async_fifo(struct
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}
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}
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-/*
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- * If Async FIFO is enabled, the following counters change as MAC now runs
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- * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
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- *
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- * The values below tested for ht40 2 chain.
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- * Overwrite the delay/timeouts initialized in process ini.
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- */
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-void ar9002_hw_update_async_fifo(struct ath_hw *ah)
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-{
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- if (AR_SREV_9287_13_OR_LATER(ah)) {
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- REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
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- AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
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- REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
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- AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
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- REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
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- AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
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-
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- REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
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- REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
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-
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- REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
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- AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
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- REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
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- AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
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- }
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-}
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-
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-/*
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- * We don't enable WEP aggregation on mac80211 but we keep this
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- * around for HAL unification purposes.
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- */
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-void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
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-{
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- if (AR_SREV_9287_13_OR_LATER(ah)) {
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- REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
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- AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
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- }
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-}
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-
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/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
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void ar9002_hw_attach_ops(struct ath_hw *ah)
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{
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -1641,9 +1641,13 @@ int ath9k_hw_reset(struct ath_hw *ah, st
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ath9k_hw_init_global_settings(ah);
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- if (!AR_SREV_9300_20_OR_LATER(ah)) {
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- ar9002_hw_update_async_fifo(ah);
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- ar9002_hw_enable_wep_aggregation(ah);
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+ if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
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+ REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
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+ AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
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+ REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
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+ AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
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+ REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
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+ AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
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}
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REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
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--- a/drivers/net/wireless/ath/ath9k/hw.h
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+++ b/drivers/net/wireless/ath/ath9k/hw.h
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@@ -984,8 +984,6 @@ void ath9k_hw_get_delta_slope_vals(struc
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void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
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int ar9002_hw_rf_claim(struct ath_hw *ah);
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void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
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-void ar9002_hw_update_async_fifo(struct ath_hw *ah);
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-void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
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/*
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* Code specific to AR9003, we stuff these here to avoid callbacks
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--- a/drivers/net/wireless/ath/ath9k/reg.h
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+++ b/drivers/net/wireless/ath/ath9k/reg.h
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@@ -600,7 +600,6 @@
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#define AR_D_GBL_IFS_SIFS 0x1030
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#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
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-#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
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#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
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#define AR_D_TXBLK_BASE 0x1038
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@@ -616,12 +615,10 @@
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#define AR_D_GBL_IFS_SLOT 0x1070
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#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
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#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
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-#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420
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#define AR_D_GBL_IFS_EIFS 0x10b0
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#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
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#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
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-#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB
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#define AR_D_GBL_IFS_MISC 0x10f0
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#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
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@@ -1477,7 +1474,6 @@ enum {
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#define AR_TIME_OUT_ACK_S 0
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#define AR_TIME_OUT_CTS 0x3FFF0000
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#define AR_TIME_OUT_CTS_S 16
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-#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56
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#define AR_RSSI_THR 0x8018
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#define AR_RSSI_THR_MASK 0x000000FF
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@@ -1493,7 +1489,6 @@ enum {
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#define AR_USEC_TX_LAT_S 14
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#define AR_USEC_RX_LAT 0x1F800000
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#define AR_USEC_RX_LAT_S 23
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-#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074
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#define AR_RESET_TSF 0x8020
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#define AR_RESET_TSF_ONCE 0x01000000
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