blogic ea6e386f6f [ramips] uart_clk on Rt3352F is always 40MHz ... Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock. Signed-off-by: Daniel Golle <dgolle@allnet.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32812 3c298f89-4303-0410-b956-a3cf2f4a3e73		2012-07-24 20:37:50 +00:00
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include/asm/mach-ralink	ramips: rt305x: add support for Edimax 3G-6200N	2012-07-12 13:29:46 +00:00
pci	ramips: rt288x: don't register the PCI controller on each board	2012-02-16 08:17:52 +00:00
ralink	[ramips] uart_clk on Rt3352F is always 40MHz	2012-07-24 20:37:50 +00:00