sie-ceimtun/Examples/Beta1/logic/PuenteH.v

`timescale 1ns / 1ps

module PuenteH(clk, reset, enable, we, addr, IN, pwm_out, ram_read);

input clk;
input enable;				//enable
input we;				//enable de escritura
input reset;				//reset
input [10:0]addr;			//Direcciones ram
input [7:0] IN;		//Data
output [3:0] pwm_out;		//Pines de salida al PWM
output [7:0] ram_read;//Lectura desde el HBRIDGE
reg [7:0] PWM_1=0;	//PWM motor derecho
reg [7:0] PWM_2=0;	//PWM motor izquierdo
reg [7:0] PWM_3=0;	//PWM motor derecho
reg [7:0] PWM_4=0;	//PWM motor izquierdo
reg we1=0;				//Write enable

    // REGISTER BANK:   Write control
    always @(negedge clk)
    begin
        if(reset) 
            {PWM_1, PWM_2, PWM_3, PWM_4,we1} <= 0;
        else if(we & enable) begin
            case (addr)   
                    0: begin PWM_1	<= IN;     end
                    1: begin PWM_2	<= IN;		end
                    2: begin PWM_3	<= IN;		end       
                    3: begin PWM_4	<= IN;		end   						  
              default: begin we1 <= 1; end  
            endcase   
        end 
        else begin 
            we1 <= 0; end 
    end 

	RAMB16_S9 ba0( .CLK(~clk), 
			.EN(enable),
			.DOP(),
			.SSR(1'b0), 
			.ADDR(addr[10:0]), 
			.WE(we1), 
			.DI(IN),
			.DIP(1'b0), 
			.DO(ram_read));


/*    // Dual-port RAM instatiation
    RAMB16_S9_S9 ba0(
            .DOA(out),         // Port A 8-bit Data Output
            .DOB(PWM_ram_reg),     // Port B 8-bit Data Output
            .DOPA(),              // Port A 1-bit Parity Output
            .DOPB(),              // Port B 1-bit Parity Output
            .ADDRA(addr[10:0]),   // Port A 11-bit Address Input
            .ADDRB(1'b0),  // Port B 11-bit Address Input
            .CLKA(~clk),          // Port A Clock
            .CLKB(~clk),          // Port B Clock
            .DIA(IN),     // Port A 8-bit Data Input
            .DIB(),    // Port B 8-bit Data Input
            .DIPA(1'b0),          // Port A 1-bit parity Input
            .DIPB(1'b0),          // Port-B 1-bit parity Input
            .ENA(1'b1),           // Port A RAM Enable Input
            .ENB(1'b1),           // Port B RAM Enable Input
            .SSRA(1'b0),          // Port A Synchronous Set/Reset Input
            .SSRB(1'b0),          // Port B Synchronous Set/Reset Input
            .WEA(we1),            // Port A Write Enable Input
            .WEB(1'b0) );          // Port B Write Enable Input 
*/
																  
PWM OUT1A (
    .clk(clk), 
    .enable(1'b1), 
    .PWM_in(PWM_1), 
    .PWM_out(pwm_out[0])
    );

PWM OUT1B (
    .clk(clk), 
    .enable(1'b1), 
    .PWM_in(PWM_2), 
    .PWM_out(pwm_out[1])
    );

PWM OUT2A (
    .clk(clk), 
    .enable(1'b1), 
    .PWM_in(PWM_3), 
    .PWM_out(pwm_out[2])
    );

PWM OUT2B (
    .clk(clk), 
    .enable(1'b1), 
    .PWM_in(PWM_4), 
    .PWM_out(pwm_out[3])
    );	 

endmodule