mirror of
git://projects.qi-hardware.com/sie-ceimtun.git
synced 2024-12-05 04:30:39 +02:00
Uploaded the first Beta to test in the development group
This commit is contained in:
Erwin Lopez
parent
0a65a50cff
commit
8f2a9cc1d6
62
Examples/Beta1/logic/Makefile
Normal file
62
Examples/Beta1/logic/Makefile
Normal file
@ -0,0 +1,62 @@
|
||||
DESIGN = beta
|
||||
PINS = $(DESIGN).ucf
|
||||
DEVICE = xc3s500e-VQ100-4
|
||||
BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
|
||||
-g CRC:enable -g StartUpClk:CCLK
|
||||
|
||||
SRC = $(DESIGN).v PuenteH.v PWM.v enco.v
|
||||
|
||||
all: bits
|
||||
|
||||
remake: clean-build all
|
||||
|
||||
clean:
|
||||
rm -f *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
|
||||
|
||||
clean-build: clean
|
||||
rm -rf build
|
||||
|
||||
cleanall: clean
|
||||
rm -rf build $(DESIGN).bit
|
||||
|
||||
bits: $(DESIGN).bit
|
||||
|
||||
#
|
||||
# Synthesis
|
||||
#
|
||||
build/project.src:
|
||||
@[ -d build ] || mkdir build
|
||||
@rm -f $@
|
||||
for i in $(SRC); do echo verilog work ../$$i >> $@; done
|
||||
for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
|
||||
|
||||
build/project.xst: build/project.src
|
||||
echo "run" > $@
|
||||
echo "-top $(DESIGN) " >> $@
|
||||
echo "-p $(DEVICE)" >> $@
|
||||
echo "-opt_mode Area" >> $@
|
||||
echo "-opt_level 1" >> $@
|
||||
echo "-ifn project.src" >> $@
|
||||
echo "-ifmt mixed" >> $@
|
||||
echo "-ofn project.ngc" >> $@
|
||||
echo "-ofmt NGC" >> $@
|
||||
echo "-rtlview yes" >> $@
|
||||
|
||||
build/project.ngc: build/project.xst $(SRC)
|
||||
cd build && xst -ifn project.xst -ofn project.log
|
||||
|
||||
build/project.ngd: build/project.ngc $(PINS)
|
||||
cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
|
||||
|
||||
build/project.ncd: build/project.ngd
|
||||
cd build && map -pr b -p $(DEVICE) project
|
||||
|
||||
build/project_r.ncd: build/project.ncd
|
||||
cd build && par -w project project_r.ncd
|
||||
|
||||
build/project_r.twr: build/project_r.ncd
|
||||
cd build && trce -v 25 project_r.ncd project.pcf
|
||||
|
||||
$(DESIGN).bit: build/project_r.ncd build/project_r.twr
|
||||
cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
|
||||
@mv -f build/project_r.bit $@
|
||||
26
Examples/Beta1/logic/PWM.v
Normal file
26
Examples/Beta1/logic/PWM.v
Normal file
@ -0,0 +1,26 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module PWM(clk, enable, PWM_in, PWM_out);
|
||||
input clk, enable;
|
||||
input [7:0] PWM_in;
|
||||
output PWM_out;
|
||||
|
||||
reg [7:0] PWM_in_reg=0; //Registro temporal para reiniciar el acumulador
|
||||
reg [7:0] PWM_accum=0; //Acumulador
|
||||
reg [8:0] ClkCount=0; //Para dividir la frecuencia en 2^VAL
|
||||
|
||||
//Divisor de frecuencia
|
||||
always @(posedge clk) if(enable) ClkCount <= ClkCount + 1;
|
||||
|
||||
//Contador para el PWM
|
||||
always @(posedge clk)
|
||||
begin
|
||||
PWM_in_reg<=PWM_in;
|
||||
if(PWM_in_reg==PWM_in) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
|
||||
end
|
||||
|
||||
//Salida para el PWM
|
||||
|
||||
assign PWM_out=(PWM_accum<PWM_in);
|
||||
|
||||
endmodule
|
||||
98
Examples/Beta1/logic/PuenteH.v
Normal file
98
Examples/Beta1/logic/PuenteH.v
Normal file
@ -0,0 +1,98 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module PuenteH(clk, reset, enable, we, addr, IN, pwm_out, ram_read);
|
||||
|
||||
input clk;
|
||||
input enable; //enable
|
||||
input we; //enable de escritura
|
||||
input reset; //reset
|
||||
input [10:0]addr; //Direcciones ram
|
||||
input [7:0] IN; //Data
|
||||
output [3:0] pwm_out; //Pines de salida al PWM
|
||||
output [7:0] ram_read;//Lectura desde el HBRIDGE
|
||||
reg [7:0] PWM_1=0; //PWM motor derecho
|
||||
reg [7:0] PWM_2=0; //PWM motor izquierdo
|
||||
reg [7:0] PWM_3=0; //PWM motor derecho
|
||||
reg [7:0] PWM_4=0; //PWM motor izquierdo
|
||||
reg we1=0; //Write enable
|
||||
|
||||
// REGISTER BANK: Write control
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if(reset)
|
||||
{PWM_1, PWM_2, PWM_3, PWM_4,we1} <= 0;
|
||||
else if(we & enable) begin
|
||||
case (addr)
|
||||
0: begin PWM_1 <= IN; end
|
||||
1: begin PWM_2 <= IN; end
|
||||
2: begin PWM_3 <= IN; end
|
||||
3: begin PWM_4 <= IN; end
|
||||
default: begin we1 <= 1; end
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
we1 <= 0; end
|
||||
end
|
||||
|
||||
RAMB16_S9 ba0( .CLK(~clk),
|
||||
.EN(enable),
|
||||
.DOP(),
|
||||
.SSR(1'b0),
|
||||
.ADDR(addr[10:0]),
|
||||
.WE(we1),
|
||||
.DI(IN),
|
||||
.DIP(1'b0),
|
||||
.DO(ram_read));
|
||||
|
||||
|
||||
/* // Dual-port RAM instatiation
|
||||
RAMB16_S9_S9 ba0(
|
||||
.DOA(out), // Port A 8-bit Data Output
|
||||
.DOB(PWM_ram_reg), // Port B 8-bit Data Output
|
||||
.DOPA(), // Port A 1-bit Parity Output
|
||||
.DOPB(), // Port B 1-bit Parity Output
|
||||
.ADDRA(addr[10:0]), // Port A 11-bit Address Input
|
||||
.ADDRB(1'b0), // Port B 11-bit Address Input
|
||||
.CLKA(~clk), // Port A Clock
|
||||
.CLKB(~clk), // Port B Clock
|
||||
.DIA(IN), // Port A 8-bit Data Input
|
||||
.DIB(), // Port B 8-bit Data Input
|
||||
.DIPA(1'b0), // Port A 1-bit parity Input
|
||||
.DIPB(1'b0), // Port-B 1-bit parity Input
|
||||
.ENA(1'b1), // Port A RAM Enable Input
|
||||
.ENB(1'b1), // Port B RAM Enable Input
|
||||
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
|
||||
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
|
||||
.WEA(we1), // Port A Write Enable Input
|
||||
.WEB(1'b0) ); // Port B Write Enable Input
|
||||
*/
|
||||
|
||||
PWM OUT1A (
|
||||
.clk(clk),
|
||||
.enable(1'b1),
|
||||
.PWM_in(PWM_1),
|
||||
.PWM_out(pwm_out[0])
|
||||
);
|
||||
|
||||
PWM OUT1B (
|
||||
.clk(clk),
|
||||
.enable(1'b1),
|
||||
.PWM_in(PWM_2),
|
||||
.PWM_out(pwm_out[1])
|
||||
);
|
||||
|
||||
PWM OUT2A (
|
||||
.clk(clk),
|
||||
.enable(1'b1),
|
||||
.PWM_in(PWM_3),
|
||||
.PWM_out(pwm_out[2])
|
||||
);
|
||||
|
||||
PWM OUT2B (
|
||||
.clk(clk),
|
||||
.enable(1'b1),
|
||||
.PWM_in(PWM_4),
|
||||
.PWM_out(pwm_out[3])
|
||||
);
|
||||
|
||||
endmodule
|
||||
108
Examples/Beta1/logic/bb.v
Normal file
108
Examples/Beta1/logic/bb.v
Normal file
@ -0,0 +1,108 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module pwm_FINAL(clk, reset, enable, we, PWM_in, PWM_out,buffer_addr,out);
|
||||
input clk; //Clock
|
||||
input enable; //Seal enable
|
||||
input we; //Seal enable de escritura
|
||||
input reset; //Seal reset
|
||||
input [7:0] PWM_in; //Dutycycle
|
||||
input [10:0]buffer_addr; //Direcciones ram
|
||||
output PWM_out; //Salida PWM
|
||||
output [10:0]out;
|
||||
|
||||
reg [7:0] PWM_accum=0; //Acumulador PWM
|
||||
reg [7:0] PWM_in_reg=0; //Registro para saber cambios en registro de RAM
|
||||
//reg [7:0] PWM_in_reg2=0; //Registro para saber cambios en registro de RAM
|
||||
reg we1=0; //registro write enable?
|
||||
wire [7:0] PWM_ram_reg; //Registro que se lee desde la ram
|
||||
|
||||
/*always @(negedge clk)//sync de addres. Por ahora lleva todo a la primera direccion
|
||||
begin
|
||||
if(enable&we)
|
||||
begin
|
||||
PWM_in_reg<=PWM_in;
|
||||
PWM_in_reg2<=PWM_in_reg;
|
||||
end
|
||||
end
|
||||
*/
|
||||
// REGISTER BANK: Write control
|
||||
always @(negedge clk)
|
||||
begin
|
||||
/*if(reset)
|
||||
{PWM_in_reg,we1} <= 0;
|
||||
else */if(we & enable) begin
|
||||
/*case (buffer_addr)
|
||||
0: begin PWM_in_reg<=PWM_in; end
|
||||
1: begin PWM_in_reg<=PWM_in; end
|
||||
2: begin PWM_in_reg<=PWM_in; end
|
||||
default: begin we1 <= 1; end
|
||||
endcase */
|
||||
we1<=1;
|
||||
end
|
||||
else begin
|
||||
we1 <= 0; end
|
||||
end
|
||||
|
||||
/*always @(posedge clk)//Manejo de escritura RAM??
|
||||
begin
|
||||
// if(reset) {PWM_accum, PWM_in_reg} <= 0;
|
||||
// else if(enable)
|
||||
// begin
|
||||
// PWM_ram_reg<=PWM_in;
|
||||
// PWM_in_reg<=PWM_in;
|
||||
// end
|
||||
if(enable)
|
||||
begin
|
||||
case (state)
|
||||
0: begin
|
||||
PWM_in_reg<=PWM_in;
|
||||
state <= 1; end
|
||||
1: begin state <= 1; end
|
||||
default: begin state <= 0; end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
*/
|
||||
always @(posedge clk)//Manejo de escritura RAM??
|
||||
begin
|
||||
PWM_in_reg<=PWM_ram_reg;
|
||||
if(PWM_in_reg==PWM_ram_reg) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
|
||||
//PWM_accum<=PWM_accum+1;
|
||||
end
|
||||
/*RAMB16_S9 ba0( .CLK(~clk),
|
||||
.EN(enable),
|
||||
.DOP(),
|
||||
.SSR(1'b0),
|
||||
.ADDR(buffer_addr[10:0]),
|
||||
.WE(we1),
|
||||
.DI(PWM_in),
|
||||
.DIP(1'b0),
|
||||
.DO(out));
|
||||
*/
|
||||
// Dual-port RAM instatiation
|
||||
RAMB16_S9_S9 ba0(
|
||||
.DOA(out), // Port A 8-bit Data Output
|
||||
.DOB(PWM_ram_reg), // Port B 8-bit Data Output
|
||||
.DOPA(), // Port A 1-bit Parity Output
|
||||
.DOPB(), // Port B 1-bit Parity Output
|
||||
.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
|
||||
.ADDRB(1'b0), // Port B 11-bit Address Input
|
||||
.CLKA(~clk), // Port A Clock
|
||||
.CLKB(~clk), // Port B Clock
|
||||
.DIA(PWM_in), // Port A 8-bit Data Input
|
||||
.DIB(), // Port B 8-bit Data Input
|
||||
.DIPA(1'b0), // Port A 1-bit parity Input
|
||||
.DIPB(1'b0), // Port-B 1-bit parity Input
|
||||
.ENA(1'b1), // Port A RAM Enable Input
|
||||
.ENB(1'b1), // Port B RAM Enable Input
|
||||
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
|
||||
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
|
||||
.WEA(we1), // Port A Write Enable Input
|
||||
.WEB(1'b0) ); // Port B Write Enable Input
|
||||
//Salida para el PWM
|
||||
|
||||
assign PWM_out=(PWM_accum<PWM_ram_reg);
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Examples/Beta1/logic/beta.bit
Normal file
BIN
Examples/Beta1/logic/beta.bit
Normal file
Binary file not shown.
52
Examples/Beta1/logic/beta.ucf
Normal file
52
Examples/Beta1/logic/beta.ucf
Normal file
@ -0,0 +1,52 @@
|
||||
NET clk LOC = "P38";
|
||||
NET reset LOC = "P30"; #WARNING change to another pin
|
||||
#NET led LOC = "P44";
|
||||
#NET led LOC = "P70"; #Pin abajo superior izquierdo
|
||||
#NET led2 LOC = "P71"; #Pin superior izquierdo
|
||||
#NET OD2 LOC = "P66";
|
||||
#NET OD3 LOC = "P63";
|
||||
NET quadA LOC = "P67";
|
||||
NET quadB LOC = "P68";
|
||||
NET "hbridge<3>" LOC = "P53";
|
||||
NET "hbridge<2>" LOC = "P54";
|
||||
NET "hbridge<1>" LOC = "P49";
|
||||
NET "hbridge<0>" LOC = "P48";
|
||||
|
||||
|
||||
#ADDRESS BUS
|
||||
NET "addr<12>" LOC = "P90";
|
||||
NET "addr<11>" LOC = "P91";
|
||||
NET "addr<10>" LOC = "P85";
|
||||
NET "addr<9>" LOC = "P92";
|
||||
NET "addr<8>" LOC = "P94";
|
||||
NET "addr<7>" LOC = "P95";
|
||||
NET "addr<6>" LOC = "P98";
|
||||
NET "addr<5>" LOC = "P3";
|
||||
NET "addr<4>" LOC = "P2";
|
||||
NET "addr<3>" LOC = "P78";
|
||||
NET "addr<2>" LOC = "P79";
|
||||
NET "addr<1>" LOC = "P83";
|
||||
NET "addr<0>" LOC = "P84";
|
||||
|
||||
#DATA BUS
|
||||
NET "sram_data<7>" LOC = "P4";
|
||||
NET "sram_data<6>" LOC = "P5";
|
||||
NET "sram_data<5>" LOC = "P9";
|
||||
NET "sram_data<4>" LOC = "P10";
|
||||
NET "sram_data<3>" LOC = "P11";
|
||||
NET "sram_data<2>" LOC = "P12";
|
||||
NET "sram_data<1>" LOC = "P15";
|
||||
NET "sram_data<0>" LOC = "P16";
|
||||
|
||||
#CONTROL BUS
|
||||
NET "nwe" LOC = "P88";
|
||||
NET "noe" LOC = "P86";
|
||||
NET "ncs" LOC = "P69";
|
||||
|
||||
#ADC
|
||||
#NET "ADC_EOC" LOC = "P17";
|
||||
#NET "ADC_SCLK" LOC = "P18" ;
|
||||
#NET "ADC_SDIN" LOC = "P22";
|
||||
#NET "ADC_SDOUT" LOC = "P23";
|
||||
#NET "ADC_CS" LOC = "P24";
|
||||
#NET "ADC_CSTART" LOC = "P26";
|
||||
137
Examples/Beta1/logic/beta.v
Normal file
137
Examples/Beta1/logic/beta.v
Normal file
@ -0,0 +1,137 @@
|
||||
`timescale 1ns / 1ps
|
||||
/*module ADC(clk, sram_data, addr, nwe, ncs, noe, reset, led, ADC_EOC,
|
||||
ADC_SCLK, ADC_SDIN, ADC_SDOUT, ADC_CS, ADC_CSTART, led2);
|
||||
*/
|
||||
module beta(clk, sram_data, quadA, quadB, addr, nwe, ncs, noe, reset, hbridge);
|
||||
|
||||
parameter B = (7);
|
||||
|
||||
// input clk, addr, nwe, ncs, noe, reset, ADC_EOC;
|
||||
inout [B:0] sram_data;
|
||||
// output led, led2, ADC_CS, ADC_CSTART, ADC_SCLK;//agregado led2, quitados ODn
|
||||
// inout ADC_SDIN, ADC_SDOUT;
|
||||
input clk, addr, nwe, ncs, noe, reset;
|
||||
output [3:0] hbridge;
|
||||
input quadA,quadB;
|
||||
|
||||
// External conection
|
||||
//wire led, led2;
|
||||
|
||||
// synchronize signals
|
||||
reg sncs, snwe;
|
||||
reg [12:0] buffer_addr;
|
||||
reg [B:0] buffer_data;
|
||||
|
||||
// bram interfaz signals
|
||||
reg we;
|
||||
reg w_st=0;
|
||||
reg [B:0] wrBus;
|
||||
wire [B:0] rdBus;
|
||||
|
||||
// interfaz fpga signals
|
||||
wire [12:0] addr;
|
||||
|
||||
// interefaz signals assignments
|
||||
wire T = ~noe | ncs;
|
||||
assign sram_data = T?8'bZ:rdBus;
|
||||
|
||||
// synchronize assignment
|
||||
always @(negedge clk)
|
||||
begin
|
||||
sncs <= ncs;
|
||||
snwe <= nwe;
|
||||
buffer_data <= sram_data;
|
||||
buffer_addr <= addr;
|
||||
end
|
||||
|
||||
// write access cpu to bram
|
||||
always @(posedge clk)
|
||||
if(~reset) {w_st, we, wrBus} <= 0;
|
||||
else begin
|
||||
wrBus <= buffer_data;
|
||||
case (w_st)
|
||||
0: begin
|
||||
we <= 0;
|
||||
if(sncs | snwe) w_st <= 1;
|
||||
end
|
||||
1: begin
|
||||
if(~(sncs | snwe)) begin
|
||||
we <= 1;
|
||||
w_st <= 0;
|
||||
end
|
||||
else we <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// Peripherals control
|
||||
wire [3:0] csN;
|
||||
wire [7:0] rdBus0, rdBus1, rdBus2, rdBus3;
|
||||
|
||||
assign csN = buffer_addr[12]? (buffer_addr[11]? 4'b1000:
|
||||
4'b0100)
|
||||
: (buffer_addr[11]? 4'b0010:
|
||||
4'b0001);
|
||||
|
||||
assign rdBus = buffer_addr[12]? (buffer_addr[11]? rdBus3:
|
||||
rdBus2)
|
||||
: (buffer_addr[11]? rdBus1:
|
||||
rdBus0);
|
||||
|
||||
|
||||
|
||||
|
||||
//assign led2=1;
|
||||
// assign led=1;
|
||||
|
||||
// Peripheral instantiation
|
||||
/* ADC_peripheral P1(
|
||||
.clk(clk),
|
||||
.reset(~reset),
|
||||
.cs(csN[0]),
|
||||
.ADC_EOC(ADC_EOC),
|
||||
.ADC_CS(ADC_CS),
|
||||
.ADC_CSTART(ADC_CSTART),
|
||||
.ADC_SCLK(ADC_SCLK),
|
||||
.ADC_SDIN(ADC_SDIN),
|
||||
.ADC_SDOUT(ADC_SDOUT),
|
||||
.addr(buffer_addr[10:0]),
|
||||
.rdBus(rdBus0),
|
||||
.wrBus(wrBus),
|
||||
.we(we));
|
||||
*/
|
||||
|
||||
enco enco1(
|
||||
.clk(clk),
|
||||
.enable(csN[0]),
|
||||
.quadA(quadA),
|
||||
.quadB(quadB),
|
||||
.out(rdBus0),
|
||||
.buffer_addr(buffer_addr[10:0])
|
||||
);
|
||||
|
||||
RAMB16_S9 ba0( .CLK(~clk),
|
||||
.EN(csN[1]),
|
||||
.DOP(),
|
||||
.SSR(1'b0),
|
||||
.ADDR(buffer_addr[10:0]),
|
||||
.WE(we),
|
||||
.DI(wrBus),
|
||||
.DIP(1'b0),
|
||||
.DO(rdBus1));
|
||||
|
||||
PuenteH puente (
|
||||
.clk(clk),
|
||||
.reset(~reset),
|
||||
.enable(csN[2]),
|
||||
.we(we),
|
||||
.addr(buffer_addr[10:0]),
|
||||
.IN(wrBus),
|
||||
.pwm_out(hbridge),
|
||||
.ram_read(rdBus2)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
12
Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
Normal file
12
Examples/Beta1/logic/build/_xmsgs/bitgen.xmsgs
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Bitgen" num="275" delta="new" >Spartan-3E devices do not support bitstream readback of the Blockram resources in the -4C speedgrade. If Blockram readback functionality is desired, it is suggested to target the -5C or -4I speedgrades.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
15
Examples/Beta1/logic/build/_xmsgs/map.xmsgs
Normal file
15
Examples/Beta1/logic/build/_xmsgs/map.xmsgs
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
9
Examples/Beta1/logic/build/_xmsgs/ngdbuild.xmsgs
Normal file
9
Examples/Beta1/logic/build/_xmsgs/ngdbuild.xmsgs
Normal file
@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
16
Examples/Beta1/logic/build/_xmsgs/par.xmsgs
Normal file
16
Examples/Beta1/logic/build/_xmsgs/par.xmsgs
Normal file
@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
19
Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
Normal file
19
Examples/Beta1/logic/build/_xmsgs/trce.xmsgs
Normal file
@ -0,0 +1,19 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3390" delta="new" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3389" delta="new" >This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
18
Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
Normal file
18
Examples/Beta1/logic/build/_xmsgs/xst.xmsgs
Normal file
@ -0,0 +1,18 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">"../enco.v" line 65 </arg>Connection to input port '<arg fmt="%s" index="2">ADDRB</arg>' does not match port size
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">rdBus3</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00000000</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">csN<3></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
1
Examples/Beta1/logic/build/beta.lso
Normal file
1
Examples/Beta1/logic/build/beta.lso
Normal file
@ -0,0 +1 @@
|
||||
work
|
||||
493
Examples/Beta1/logic/build/beta_map.xrpt
Normal file
493
Examples/Beta1/logic/build/beta_map.xrpt
Normal file
@ -0,0 +1,493 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="lin64" product="ISE" version="12.2">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Sat Oct 30 18:30:54 2010">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="LD_LIBRARY_PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//lib/lin64:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//bin/lin64:/opt/e17/bin:/bin:/usr/locale/bin:/usr/bin:/sbin:/usr/sbin:/home/erwin/openwrt-xburst/bin/xburst:/home/erwin/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/:/usr/share/java/apache-ant/bin:/opt/java/bin:/opt/java/db/bin:/opt/java/jre/bin:/usr/lib/perl5/vendor_perl/bin:/usr/bin/perlbin/vendor:/usr/lib/perl5/core_perl/bin:/opt/qt/bin:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/:/opt/Xilinx/12.2/ISE_DS/ISE/:/usr/local/bin/:/home/erwin/ModelSim/modeltech/linux_x86_64"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE/"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="unknown"/>
|
||||
<item stringID="User_EnvOsrelease" value="unknown"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="dellerwin"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
|
||||
<item stringID="speed" value="2201.000 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_OPTION_SUMMARY">
|
||||
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="b"/>
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc3s500e-VQ100-4"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<section stringID="MAP_DESIGN_INFORMATION">
|
||||
<item stringID="MAP_PART" value="3s500evq100-4"/>
|
||||
<item stringID="MAP_DEVICE" value="xc3s500e"/>
|
||||
<item stringID="MAP_ARCHITECTURE" value="spartan3e"/>
|
||||
<item stringID="MAP_PACKAGE" value="vq100"/>
|
||||
<item stringID="MAP_SPEED" value="-4"/>
|
||||
</section>
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375808"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="2 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="118"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE_SLICEL" value="2328"/>
|
||||
<item dataType="int" stringID="MAP_AVAILABLE_SLICEM" value="2328"/>
|
||||
<item dataType="int" stringID="MAP_FLOPS_PER_SLICE" value="2"/>
|
||||
<item dataType="int" stringID="MAP_LUTS_PER_SLICE" value="2"/>
|
||||
<item AVAILABLE="2328" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
|
||||
<item AVAILABLE="2328" dataType="int" stringID="MAP_NUM_SLICEL" value="0"/>
|
||||
<item dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="130"/>
|
||||
<item dataType="int" label="Number of occupied Slices" stringID="MAP_AGG_SLICE" value="112"/>
|
||||
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
|
||||
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="28"/>
|
||||
<item dataType="int" stringID="MAP_NUM_DP_RAM" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_RAM32" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_RAM16" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_ROM16" value="0"/>
|
||||
<item dataType="int" label="Number used as Shift registers" stringID="MAP_NUM_SHIFT" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<section stringID="MAP_IOB_DATA">
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPADAGG_BONDED_IO" value="0"/>
|
||||
<item AVAILABLE="414" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="25"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
|
||||
<item AVAILABLE="116" dataType="int" stringID="MAP_NUM_DIFFM" value="0"/>
|
||||
<item AVAILABLE="44" dataType="int" stringID="MAP_NUM_DIFFMI" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFM" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFMINUM_DIFFS" value="0"/>
|
||||
<item AVAILABLE="44" dataType="int" stringID="MAP_NUM_DIFFSI" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFS" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_DIFFSI" value="0"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_HARD_IP_REPORTING">
|
||||
<item AVAILABLE="20" dataType="int" stringID="MAP_NUM_RAMB16" value="3"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MULT18X18" value="0"/>
|
||||
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="1"/>
|
||||
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_DCM" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
|
||||
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_CAPTURE" value="0"/>
|
||||
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_DCIRESET" value="0"/>
|
||||
<item AVAILABLE="20" dataType="int" stringID="MAP_NUM_MULT18X18SIO" value="0"/>
|
||||
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_MACRO_RPM_REPORTING">
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_PROPERTIES">
|
||||
<table stringID="MAP_IOB_TABLE">
|
||||
<column label="IOB
Name" sort="smart" stringID="IOB_NAME"/>
|
||||
<column stringID="Type"/>
|
||||
<column stringID="Direction"/>
|
||||
<column label="IO
Standard" sort="smart" stringID="IO_STANDARD"/>
|
||||
<column label="Diff
Term" stringID="DIFF_TERM"/>
|
||||
<column label="Drive
Strength" stringID="DRIVE_STRENGTH"/>
|
||||
<column label="Slew
Rate" stringID="SLEW_RATE"/>
|
||||
<column label="Reg
(s)" stringID="REGS"/>
|
||||
<column stringID="Resistor"/>
|
||||
<column label="IOB
Delay" stringID="IOB_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<0>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<1>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<2>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<3>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<4>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<5>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<6>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<7>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<8>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<9>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<10>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<11>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="addr<12>"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="clk"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="hbridge<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="hbridge<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="hbridge<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="hbridge<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="ncs"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="noe"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="nwe"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="quadA"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="quadB"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="reset"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="sram_data<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="Reg
(s)" stringID="REGS" value="IFF1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 3"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_RPM_MACROS">
|
||||
<section stringID="MAP_SHAPE_SECTION">
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="8"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_GUIDE_REPORT"/>
|
||||
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
|
||||
<section stringID="MAP_TIMING_REPORT"/>
|
||||
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
|
||||
<section stringID="MAP_GENERAL_CONFIG_DATA">
|
||||
<item stringID="MAP_INITP_00" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_01" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_02" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_03" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_04" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_05" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_06" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INITP_07" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_00" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_01" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_02" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_03" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_04" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_05" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_06" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_07" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_08" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_09" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0A" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0B" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0C" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0D" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0E" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_0F" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_10" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_11" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_12" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_13" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_14" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_15" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_16" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_17" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_18" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_19" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1A" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1B" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1C" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1D" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1E" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_1F" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_20" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_21" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_22" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_23" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_24" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_25" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_26" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_27" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_28" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_29" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2A" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2B" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2C" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2D" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2E" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_2F" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_30" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_31" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_32" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_33" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_34" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_35" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_36" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_37" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_38" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_39" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3A" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3B" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3C" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3D" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3E" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_3F" value="0000000000000000000000000000000000000000000000000000000000000000"/>
|
||||
<item stringID="MAP_INIT_A" value="000"/>
|
||||
<item stringID="MAP_SRVAL_A" value="000"/>
|
||||
<item stringID="MAP_DISABLE_ATTR" value="LOW"/>
|
||||
<item stringID="MAP_INIT_B" value="000"/>
|
||||
<item stringID="MAP_SRVAL_B" value="000"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION"/>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
958
Examples/Beta1/logic/build/beta_par.xrpt
Normal file
958
Examples/Beta1/logic/build/beta_par.xrpt
Normal file
@ -0,0 +1,958 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="lin64" product="ISE" version="12.2">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="par" timeStamp="Sat Oct 30 18:30:57 2010">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="LD_LIBRARY_PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//lib/lin64:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//bin/lin64:/opt/e17/bin:/bin:/usr/locale/bin:/usr/bin:/sbin:/usr/sbin:/home/erwin/openwrt-xburst/bin/xburst:/home/erwin/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/:/usr/share/java/apache-ant/bin:/opt/java/bin:/opt/java/db/bin:/opt/java/jre/bin:/usr/lib/perl5/vendor_perl/bin:/usr/bin/perlbin/vendor:/usr/lib/perl5/core_perl/bin:/opt/qt/bin:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/:/opt/Xilinx/12.2/ISE_DS/ISE/:/usr/local/bin/:/home/erwin/ModelSim/modeltech/linux_x86_64"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE/"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="unknown"/>
|
||||
<item stringID="User_EnvOsrelease" value="unknown"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="dellerwin"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
|
||||
<item stringID="speed" value="2201.000 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<task stringID="PAR_OPTION_SUMMARY">
|
||||
<section stringID="PAR_OPTION_SUMMARY">
|
||||
<item DEFAULT="false" label="-w" stringID="PAR_OVERWRITE_OUTPUT" value="true"/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="PAR_DEVICE_UTILIZATION">
|
||||
<section stringID="PAR_DESIGN_SUMMARY"></section>
|
||||
</task>
|
||||
<task stringID="PAR_PAR">
|
||||
<section stringID="PAR_DESIGN_SUMMARY">
|
||||
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="19 secs "/>
|
||||
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="18 secs "/>
|
||||
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
|
||||
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
|
||||
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="19 secs "/>
|
||||
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="19 secs "/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="PAR_par">
|
||||
<section stringID="PAR_DLY_CLK_REPORT"/>
|
||||
<section stringID="PAR_CLOCK_REPORT">
|
||||
<table stringID="PAR_CLOCK_TABLE">
|
||||
<column label="Clock Net" stringID="CLOCK_NET"/>
|
||||
<column label="Routed" stringID="ROUTED"/>
|
||||
<column label="Resource" stringID="RESOURCE"/>
|
||||
<column label="Locked" stringID="LOCKED"/>
|
||||
<column label="Fanout" stringID="FANOUT"/>
|
||||
<column label="Net Skew(ns)" stringID="NET_SKEW"/>
|
||||
<column label="Max Delay(ns)" stringID="MAX_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="Clock Net" stringID="CLOCK_NET" value="clk_BUFGP"/>
|
||||
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
|
||||
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/>
|
||||
<item label="Locked" stringID="LOCKED" value="No"/>
|
||||
<item dataType="float" label="Fanout" stringID="FANOUT" value="90.000000"/>
|
||||
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.078000"/>
|
||||
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.204000"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="PAR_PAD_PIN_REPORT">
|
||||
<table stringID="PAR_PINOUT_BY_PIN_NUMBER">
|
||||
<column label="Pin
Number" sort="smart" stringID="Pin_Number"/>
|
||||
<column label="Signal
Name" stringID="Signal_Name"/>
|
||||
<column label="Pin
Usage" stringID="Pin_Usage"/>
|
||||
<column label="Pin
Name" sort="smart" stringID="Pin_Name"/>
|
||||
<column stringID="Direction"/>
|
||||
<column label="IO
Standard" sort="smart" stringID="IO_Standard"/>
|
||||
<column label="IO Bank
Number" stringID="IO_Bank_Number"/>
|
||||
<column label="Drive
(mA)" stringID="Drive"/>
|
||||
<column label="Slew
Rate" stringID="Slew_Rate"/>
|
||||
<column label="Termination" stringID="Termination"/>
|
||||
<column label="IOB
Delay" stringID="IOB_Delay"/>
|
||||
<column label="Voltage" stringID="Voltage"/>
|
||||
<column label="Constraint" stringID="Constraint"/>
|
||||
<column label="IO
Register" stringID="IO_Register"/>
|
||||
<column label="Signal
Integrity" stringID="Signal_Integrity"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P1"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="PROG_B"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P2"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<4>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01P_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P3"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<5>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01N_3"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P4"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<7>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02P_3"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P5"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<6>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_3/VREF_3"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P6"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
|
||||
<item label="Voltage" stringID="Voltage" value="1.2"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P7"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P8"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P9"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<5>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_3/LHCLK0"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P10"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<4>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03N_3/LHCLK1"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P11"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<3>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04P_3/LHCLK2"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P12"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<2>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04N_3/LHCLK3/IRDY2"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P13"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P14"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P15"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<1>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05P_3/LHCLK4/TRDY2"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P16"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="sram_data<0>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05N_3/LHCLK5"/>
|
||||
<item stringID="Direction" value="BIDIR"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P17"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_3/LHCLK6"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P18"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_3/LHCLK7"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P19"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="20">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P20"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_3"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="21">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P21"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.5"/>
|
||||
</row>
|
||||
<row stringID="row" value="22">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P22"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07P_3"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
</row>
|
||||
<row stringID="row" value="23">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P23"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07N_3"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="3"/>
|
||||
</row>
|
||||
<row stringID="row" value="24">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P24"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01P_2/CSO_B"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="25">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P25"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01N_2/INIT_B"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="26">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P26"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02P_2/DOUT/BUSY"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="27">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P27"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_2/MOSI/CSI_B"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="28">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P28"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
|
||||
<item label="Voltage" stringID="Voltage" value="1.2"/>
|
||||
</row>
|
||||
<row stringID="row" value="29">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P29"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="30">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P30"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="reset"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP/VREF_2"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="31">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P31"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="32">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P32"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_2/D7/GCLK12"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="33">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P33"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03N_2/D6/GCLK13"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="34">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P34"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO/D5"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="35">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P35"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04P_2/D4/GCLK14"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="36">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P36"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04N_2/D3/GCLK15"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="37">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P37"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="38">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P38"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="clk"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_L05P_2/RDWR_B/GCLK0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="39">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P39"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSI"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_L05N_2/M2/GCLK1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="40">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P40"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_2/D2/GCLK2"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="41">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P41"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_2/D1/GCLK3"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="42">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P42"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO/M1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="43">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P43"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07P_2/M0"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="44">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P44"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07N_2/DIN/D0"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="45">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P45"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_2"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="46">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P46"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.5"/>
|
||||
</row>
|
||||
<row stringID="row" value="47">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P47"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08P_2/VS2"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="48">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P48"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="hbridge<0>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08N_2/VS1"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="49">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P49"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="hbridge<1>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L09P_2/VS0"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="50">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P50"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L09N_2/CCLK"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
|
||||
</row>
|
||||
<row stringID="row" value="51">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P51"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="DONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="52">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P52"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="53">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P53"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="hbridge<3>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01P_1"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="54">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P54"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="hbridge<2>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01N_1"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="Drive
(mA)" stringID="Drive" value="12"/>
|
||||
<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
|
||||
<item label="Termination" stringID="Termination" value="NONE**"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="55">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P55"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_1"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="56">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P56"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
|
||||
<item label="Voltage" stringID="Voltage" value="1.2"/>
|
||||
</row>
|
||||
<row stringID="row" value="57">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P57"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02P_1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="58">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P58"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="59">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P59"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="60">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P60"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_1/RHCLK0"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="61">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P61"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03N_1/RHCLK1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="62">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P62"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04P_1/RHCLK2"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="63">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P63"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L04N_1/RHCLK3/TRDY1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="64">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P64"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="65">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P65"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05P_1/RHCLK4/IRDY1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="66">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P66"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05N_1/RHCLK5"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="67">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P67"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="quadA"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_1/RHCLK6"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="68">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P68"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="quadB"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_1/RHCLK7"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="69">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P69"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="ncs"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP/VREF_1"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="70">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P70"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07P_1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="71">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P71"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07N_1"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
</row>
|
||||
<row stringID="row" value="72">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P72"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="73">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P73"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_1"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="1"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="74">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P74"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.5"/>
|
||||
</row>
|
||||
<row stringID="row" value="75">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P75"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="TMS"/>
|
||||
</row>
|
||||
<row stringID="row" value="76">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P76"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="TDO"/>
|
||||
</row>
|
||||
<row stringID="row" value="77">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P77"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="TCK"/>
|
||||
</row>
|
||||
<row stringID="row" value="78">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P78"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<3>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01P_0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="79">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P79"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<2>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L01N_0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="80">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P80"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCINT"/>
|
||||
<item label="Voltage" stringID="Voltage" value="1.2"/>
|
||||
</row>
|
||||
<row stringID="row" value="81">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P81"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="82">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P82"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="83">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P83"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<1>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02P_0/GCLK4"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="84">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P84"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<0>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_0/GCLK5"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="85">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P85"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<10>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03P_0/GCLK6"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="86">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P86"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="noe"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L03N_0/GCLK7"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="NONE"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="NO"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="87">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P87"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="88">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P88"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="nwe"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_L04P_0/GCLK8"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="89">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P89"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFSI"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IP_L04N_0/GCLK9"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
</row>
|
||||
<row stringID="row" value="90">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P90"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<12>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05P_0/GCLK10"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="91">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P91"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<11>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L05N_0/GCLK11"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="92">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P92"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<9>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="93">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P93"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="GND"/>
|
||||
</row>
|
||||
<row stringID="row" value="94">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P94"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<8>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06P_0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="95">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P95"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<7>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L06N_0/VREF_0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="96">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P96"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCAUX"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.5"/>
|
||||
</row>
|
||||
<row stringID="row" value="97">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P97"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="VCCO_0"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="Voltage" stringID="Voltage" value="2.50"/>
|
||||
</row>
|
||||
<row stringID="row" value="98">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P98"/>
|
||||
<item label="Signal
Name" stringID="Signal_Name" value="addr<6>"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="IBUF"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07P_0"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
<item label="IOB
Delay" stringID="IOB_Delay" value="IFD"/>
|
||||
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
|
||||
<item label="IO
Register" stringID="IO_Register" value="YES"/>
|
||||
<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
|
||||
</row>
|
||||
<row stringID="row" value="99">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P99"/>
|
||||
<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L07N_0/HSWAP"/>
|
||||
<item stringID="Direction" value="UNUSED"/>
|
||||
<item label="IO Bank
Number" stringID="IO_Bank_Number" value="0"/>
|
||||
</row>
|
||||
<row stringID="row" value="100">
|
||||
<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P100"/>
|
||||
<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="TDI"/>
|
||||
</row>
|
||||
</table>
|
||||
<table stringID="PAR_PSEUDO_LOGIC">
|
||||
<column label="Signal
Name" stringID="Signal_Name"/>
|
||||
<column stringID="Type"/>
|
||||
<column stringID="Site"/>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="PAR_UNROUTES_REPORT">
|
||||
<item dataType="int" stringID="PAR_UNROUTED_NETS" value="0"/>
|
||||
<item dataType="int" stringID="PAR_TOTAL_SOURCELESS_NETS" value="0"/>
|
||||
<item dataType="int" stringID="PAR_TOTAL_LOADLESS_NETS" value="0"/>
|
||||
</section>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
2
Examples/Beta1/logic/build/netlist.lst
Normal file
2
Examples/Beta1/logic/build/netlist.lst
Normal file
@ -0,0 +1,2 @@
|
||||
/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project.ngc 1288481444
|
||||
OK
|
||||
36
Examples/Beta1/logic/build/project.bld
Normal file
36
Examples/Beta1/logic/build/project.bld
Normal file
@ -0,0 +1,36 @@
|
||||
Release 12.2 ngdbuild M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: /home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
|
||||
-p xc3s500e-VQ100-4 project.ngc -uc ../beta.ucf
|
||||
|
||||
Reading NGO file
|
||||
"/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project.ngc" ...
|
||||
Gathering constraint information from source properties...
|
||||
Done.
|
||||
|
||||
Annotating constraints to design from ucf file "../beta.ucf" ...
|
||||
Resolving constraint associations...
|
||||
Checking Constraint Associations...
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 235524 kilobytes
|
||||
|
||||
Writing NGD file "project.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total CPU time to NGDBUILD completion: 2 sec
|
||||
|
||||
Writing NGDBUILD log file "project.bld"...
|
||||
660
Examples/Beta1/logic/build/project.log
Normal file
660
Examples/Beta1/logic/build/project.log
Normal file
@ -0,0 +1,660 @@
|
||||
Release 12.2 - xst M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
-->
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) Design Hierarchy Analysis
|
||||
4) HDL Analysis
|
||||
5) HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Advanced HDL Synthesis
|
||||
6.1) Advanced HDL Synthesis Report
|
||||
7) Low Level Synthesis
|
||||
8) Partition Report
|
||||
9) Final Report
|
||||
9.1) Device utilization summary
|
||||
9.2) Partition Resource Summary
|
||||
9.3) TIMING REPORT
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "project.src"
|
||||
Input Format : mixed
|
||||
|
||||
---- Target Parameters
|
||||
Target Device : xc3s500e-VQ100-4
|
||||
Output File Name : "project.ngc"
|
||||
Output Format : NGC
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : beta
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Area
|
||||
Optimization Effort : 1
|
||||
RTL Output : yes
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling verilog file "../beta.v" in library work
|
||||
Compiling verilog file "../PuenteH.v" in library work
|
||||
Module <beta> compiled
|
||||
Compiling verilog file "../PWM.v" in library work
|
||||
Module <PuenteH> compiled
|
||||
Compiling verilog file "../enco.v" in library work
|
||||
Module <PWM> compiled
|
||||
Module <enco> compiled
|
||||
No errors in compilation
|
||||
Analysis of file <"project.src"> succeeded.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for module <beta> in library <work> with parameters.
|
||||
B = "00000000000000000000000000000111"
|
||||
|
||||
Analyzing hierarchy for module <enco> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <PuenteH> in library <work>.
|
||||
|
||||
Analyzing hierarchy for module <PWM> in library <work>.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing top module <beta>.
|
||||
B = 32'sb00000000000000000000000000000111
|
||||
Module <beta> is correct for synthesis.
|
||||
|
||||
Set user-defined property "INIT = 000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INITP_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_10 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_11 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_12 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_13 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_14 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_15 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_16 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_17 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_18 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_19 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_1F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "INIT_3F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "SRVAL = 000" for instance <ba0> in unit <beta>.
|
||||
Set user-defined property "WRITE_MODE = WRITE_FIRST" for instance <ba0> in unit <beta>.
|
||||
Analyzing module <enco> in library <work>.
|
||||
Module <enco> is correct for synthesis.
|
||||
|
||||
Set user-defined property "INITP_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INITP_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_10 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_11 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_12 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_13 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_14 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_15 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_16 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_17 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_18 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_19 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_1F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_3F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_A = 000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "INIT_B = 000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "SIM_COLLISION_CHECK = ALL" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "SRVAL_A = 000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "SRVAL_B = 000" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "WRITE_MODE_A = WRITE_FIRST" for instance <ba0> in unit <enco>.
|
||||
Set user-defined property "WRITE_MODE_B = WRITE_FIRST" for instance <ba0> in unit <enco>.
|
||||
Analyzing module <PuenteH> in library <work>.
|
||||
Module <PuenteH> is correct for synthesis.
|
||||
|
||||
Set user-defined property "INIT = 000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INITP_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_00 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_01 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_02 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_03 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_04 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_05 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_06 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_07 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_08 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_09 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_0F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_10 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_11 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_12 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_13 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_14 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_15 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_16 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_17 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_18 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_19 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_1F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_20 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_21 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_22 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_23 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_24 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_25 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_26 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_27 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_28 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_29 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_2F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_30 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_31 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_32 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_33 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_34 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_35 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_36 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_37 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_38 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_39 = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3A = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3B = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3C = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3D = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3E = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "INIT_3F = 0000000000000000000000000000000000000000000000000000000000000000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "SRVAL = 000" for instance <ba0> in unit <PuenteH>.
|
||||
Set user-defined property "WRITE_MODE = WRITE_FIRST" for instance <ba0> in unit <PuenteH>.
|
||||
Analyzing module <PWM> in library <work>.
|
||||
Module <PWM> is correct for synthesis.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <PWM>.
|
||||
Related source file is "../PWM.v".
|
||||
Found 8-bit comparator less for signal <PWM_out>.
|
||||
Found 9-bit up counter for signal <ClkCount>.
|
||||
Found 8-bit up counter for signal <PWM_accum>.
|
||||
Found 8-bit comparator equal for signal <PWM_accum$cmp_eq0000> created at line 19.
|
||||
Found 8-bit register for signal <PWM_in_reg>.
|
||||
Summary:
|
||||
inferred 2 Counter(s).
|
||||
inferred 8 D-type flip-flop(s).
|
||||
inferred 2 Comparator(s).
|
||||
Unit <PWM> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <enco>.
|
||||
Related source file is "../enco.v".
|
||||
Found 7-bit updown counter for signal <count>.
|
||||
Found 1-bit xor2 for signal <count_direction>.
|
||||
Found 1-bit xor3 for signal <count_enable>.
|
||||
Found 3-bit register for signal <quadA_delayed>.
|
||||
Found 3-bit register for signal <quadB_delayed>.
|
||||
Summary:
|
||||
inferred 1 Counter(s).
|
||||
inferred 6 D-type flip-flop(s).
|
||||
inferred 1 Xor(s).
|
||||
Unit <enco> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <PuenteH>.
|
||||
Related source file is "../PuenteH.v".
|
||||
Found 8-bit register for signal <PWM_1>.
|
||||
Found 8-bit register for signal <PWM_2>.
|
||||
Found 8-bit register for signal <PWM_3>.
|
||||
Found 8-bit register for signal <PWM_4>.
|
||||
Found 1-bit register for signal <we1>.
|
||||
Summary:
|
||||
inferred 33 D-type flip-flop(s).
|
||||
Unit <PuenteH> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <beta>.
|
||||
Related source file is "../beta.v".
|
||||
WARNING:Xst:653 - Signal <rdBus3> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
|
||||
WARNING:Xst:646 - Signal <csN<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
||||
Found 8-bit tristate buffer for signal <sram_data>.
|
||||
Found 13-bit register for signal <buffer_addr>.
|
||||
Found 8-bit register for signal <buffer_data>.
|
||||
Found 1-bit register for signal <sncs>.
|
||||
Found 1-bit register for signal <snwe>.
|
||||
Found 1-bit register for signal <w_st>.
|
||||
Found 1-bit register for signal <we>.
|
||||
Found 8-bit register for signal <wrBus>.
|
||||
Summary:
|
||||
inferred 33 D-type flip-flop(s).
|
||||
inferred 8 Tristate(s).
|
||||
Unit <beta> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Counters : 5
|
||||
7-bit updown counter : 1
|
||||
8-bit up counter : 4
|
||||
# Registers : 18
|
||||
1-bit register : 5
|
||||
13-bit register : 1
|
||||
3-bit register : 2
|
||||
8-bit register : 10
|
||||
# Comparators : 8
|
||||
8-bit comparator equal : 4
|
||||
8-bit comparator less : 4
|
||||
# Tristates : 1
|
||||
8-bit tristate buffer : 1
|
||||
# Xors : 2
|
||||
1-bit xor2 : 1
|
||||
1-bit xor3 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Counters : 5
|
||||
7-bit updown counter : 1
|
||||
8-bit up counter : 4
|
||||
# Registers : 104
|
||||
Flip-Flops : 104
|
||||
# Comparators : 8
|
||||
8-bit comparator equal : 4
|
||||
8-bit comparator less : 4
|
||||
# Xors : 2
|
||||
1-bit xor2 : 1
|
||||
1-bit xor3 : 1
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Optimizing unit <beta> ...
|
||||
|
||||
Optimizing unit <PWM> ...
|
||||
|
||||
Optimizing unit <enco> ...
|
||||
|
||||
Optimizing unit <PuenteH> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
=========================================================================
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 143
|
||||
Flip-Flops : 143
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : project.ngr
|
||||
Top Level Output File Name : project.ngc
|
||||
Output Format : NGC
|
||||
Optimization Goal : Area
|
||||
Keep Hierarchy : no
|
||||
|
||||
Design Statistics
|
||||
# IOs : 32
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 239
|
||||
# GND : 1
|
||||
# INV : 11
|
||||
# LUT1 : 28
|
||||
# LUT2 : 38
|
||||
# LUT3 : 3
|
||||
# LUT4 : 55
|
||||
# MUXCY : 60
|
||||
# MUXF5 : 10
|
||||
# VCC : 1
|
||||
# XORCY : 32
|
||||
# FlipFlops/Latches : 143
|
||||
# FD : 38
|
||||
# FD_1 : 23
|
||||
# FDE : 7
|
||||
# FDR : 42
|
||||
# FDRE_1 : 33
|
||||
# RAMS : 3
|
||||
# RAMB16_S9 : 2
|
||||
# RAMB16_S9_S9 : 1
|
||||
# Clock Buffers : 1
|
||||
# BUFGP : 1
|
||||
# IO Buffers : 31
|
||||
# IBUF : 19
|
||||
# IOBUF : 8
|
||||
# OBUF : 4
|
||||
=========================================================================
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 3s500evq100-4
|
||||
|
||||
Number of Slices: 108 out of 4656 2%
|
||||
Number of Slice Flip Flops: 119 out of 9312 1%
|
||||
Number of 4 input LUTs: 135 out of 9312 1%
|
||||
Number of IOs: 32
|
||||
Number of bonded IOBs: 32 out of 66 48%
|
||||
IOB Flip Flops: 24
|
||||
Number of BRAMs: 3 out of 20 15%
|
||||
Number of GCLKs: 1 out of 24 4%
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
---------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
---------------------------
|
||||
|
||||
|
||||
=========================================================================
|
||||
TIMING REPORT
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
GENERATED AFTER PLACE-and-ROUTE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
-----------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+------------------------+-------+
|
||||
clk | BUFGP | 146 |
|
||||
-----------------------------------+------------------------+-------+
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
No asynchronous control signals found in this design
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -4
|
||||
|
||||
Minimum period: 9.656ns (Maximum Frequency: 103.563MHz)
|
||||
Minimum input arrival time before clock: 4.545ns
|
||||
Maximum output required time after clock: 8.043ns
|
||||
Maximum combinational path delay: 6.573ns
|
||||
|
||||
Timing Detail:
|
||||
--------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'clk'
|
||||
Clock period: 9.656ns (frequency: 103.563MHz)
|
||||
Total number of paths / destination ports: 1347 / 251
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 4.828ns (Levels of Logic = 2)
|
||||
Source: puente/PWM_1_1 (FF)
|
||||
Destination: puente/OUT1A/PWM_accum_0 (FF)
|
||||
Source Clock: clk falling
|
||||
Destination Clock: clk rising
|
||||
|
||||
Data Path: puente/PWM_1_1 to puente/OUT1A/PWM_accum_0
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDRE_1:C->Q 3 0.591 0.566 puente/PWM_1_1 (puente/PWM_1_1)
|
||||
LUT4:I2->O 1 0.704 0.595 puente/OUT1A/PWM_accum_cmp_eq0000_inv26 (puente/OUT1A/PWM_accum_cmp_eq0000_inv26)
|
||||
LUT4:I0->O 8 0.704 0.757 puente/OUT1A/PWM_accum_cmp_eq0000_inv136 (puente/OUT1A/PWM_accum_cmp_eq0000_inv)
|
||||
FDR:R 0.911 puente/OUT1A/PWM_accum_0
|
||||
----------------------------------------
|
||||
Total 4.828ns (2.910ns logic, 1.918ns route)
|
||||
(60.3% logic, 39.7% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
|
||||
Total number of paths / destination ports: 68 / 68
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.545ns (Levels of Logic = 2)
|
||||
Source: reset (PAD)
|
||||
Destination: we (FF)
|
||||
Destination Clock: clk rising
|
||||
|
||||
Data Path: reset to we
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 2 1.218 0.447 reset_IBUF (reset_IBUF)
|
||||
INV:I->O 42 0.704 1.265 reset_inv1_INV_0 (reset_inv)
|
||||
FDR:R 0.911 we
|
||||
----------------------------------------
|
||||
Total 4.545ns (2.833ns logic, 1.712ns route)
|
||||
(62.3% logic, 37.7% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
|
||||
Total number of paths / destination ports: 168 / 12
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 8.043ns (Levels of Logic = 3)
|
||||
Source: enco1/ba0 (RAM)
|
||||
Destination: sram_data<7> (PAD)
|
||||
Source Clock: clk falling
|
||||
|
||||
Data Path: enco1/ba0 to sram_data<7>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
RAMB16_S9_S9:CLKA->DOA7 2 2.800 0.526 enco1/ba0 (rdBus0<7>)
|
||||
LUT4:I1->O 1 0.704 0.000 rdBus<7>1 (rdBus<7>1)
|
||||
MUXF5:I1->O 1 0.321 0.420 rdBus<7>_f5 (rdBus<7>)
|
||||
IOBUF:I->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
|
||||
----------------------------------------
|
||||
Total 8.043ns (7.097ns logic, 0.946ns route)
|
||||
(88.2% logic, 11.8% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 16 / 8
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 6.573ns (Levels of Logic = 3)
|
||||
Source: ncs (PAD)
|
||||
Destination: sram_data<7> (PAD)
|
||||
|
||||
Data Path: ncs to sram_data<7>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 2 1.218 0.622 ncs_IBUF (ncs_IBUF)
|
||||
LUT2:I0->O 8 0.704 0.757 T1 (T)
|
||||
IOBUF:T->IO 3.272 sram_data_7_IOBUF (sram_data<7>)
|
||||
----------------------------------------
|
||||
Total 6.573ns (5.194ns logic, 1.379ns route)
|
||||
(79.0% logic, 21.0% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 7.00 secs
|
||||
Total CPU time to Xst completion: 6.07 secs
|
||||
|
||||
-->
|
||||
|
||||
|
||||
Total memory usage is 335836 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
Number of infos : 0 ( 0 filtered)
|
||||
|
||||
72
Examples/Beta1/logic/build/project.map
Normal file
72
Examples/Beta1/logic/build/project.map
Normal file
@ -0,0 +1,72 @@
|
||||
Release 12.2 Map M.63c (lin64)
|
||||
Xilinx Map Application Log File for Design 'beta'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
|
||||
Target Device : xc3s500e
|
||||
Target Package : vq100
|
||||
Target Speed : -4
|
||||
Mapper Version : spartan3e -- $Revision: 1.52 $
|
||||
Mapped Date : Sat Oct 30 18:30:51 2010
|
||||
|
||||
Mapping design into LUTs...
|
||||
Writing file project.ngm...
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Running related packing...
|
||||
Updating timing models...
|
||||
Writing design file "project.ncd"...
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Logic Utilization:
|
||||
Number of Slice Flip Flops: 118 out of 9,312 1%
|
||||
Number of 4 input LUTs: 102 out of 9,312 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 112 out of 4,656 2%
|
||||
Number of Slices containing only related logic: 112 out of 112 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 112 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 130 out of 9,312 1%
|
||||
Number used as logic: 102
|
||||
Number used as a route-thru: 28
|
||||
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
Number of bonded IOBs: 32 out of 66 48%
|
||||
IOB Flip Flops: 25
|
||||
Number of RAMB16s: 3 out of 20 15%
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.62
|
||||
|
||||
Peak Memory Usage: 367 MB
|
||||
Total REAL time to MAP completion: 2 secs
|
||||
Total CPU time to MAP completion: 2 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "project.mrp" for details.
|
||||
184
Examples/Beta1/logic/build/project.mrp
Normal file
184
Examples/Beta1/logic/build/project.mrp
Normal file
@ -0,0 +1,184 @@
|
||||
Release 12.2 Map M.63c (lin64)
|
||||
Xilinx Mapping Report File for Design 'beta'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -pr b -p xc3s500e-VQ100-4 project.ngd
|
||||
Target Device : xc3s500e
|
||||
Target Package : vq100
|
||||
Target Speed : -4
|
||||
Mapper Version : spartan3e -- $Revision: 1.52 $
|
||||
Mapped Date : Sat Oct 30 18:30:51 2010
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Logic Utilization:
|
||||
Number of Slice Flip Flops: 118 out of 9,312 1%
|
||||
Number of 4 input LUTs: 102 out of 9,312 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 112 out of 4,656 2%
|
||||
Number of Slices containing only related logic: 112 out of 112 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 112 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 130 out of 9,312 1%
|
||||
Number used as logic: 102
|
||||
Number used as a route-thru: 28
|
||||
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
Number of bonded IOBs: 32 out of 66 48%
|
||||
IOB Flip Flops: 25
|
||||
Number of RAMB16s: 3 out of 20 15%
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.62
|
||||
|
||||
Peak Memory Usage: 367 MB
|
||||
Total REAL time to MAP completion: 2 secs
|
||||
Total CPU time to MAP completion: 2 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Timing Report
|
||||
Section 11 - Configuration String Information
|
||||
Section 12 - Control Set Information
|
||||
Section 13 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
||||
rate limited output drivers. The delay on speed critical single ended outputs
|
||||
can be dramatically reduced by designating them as fast outputs.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
2 block(s) optimized away
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND XST_GND
|
||||
VCC XST_VCC
|
||||
|
||||
To enable printing of redundant blocks removed and signals merged, set the
|
||||
detailed map report option and rerun map.
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Term | Strength | Rate | | | Delay |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| addr<0> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<1> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<2> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<3> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<4> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<5> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<6> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<7> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<8> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<9> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<10> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<11> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| addr<12> | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| clk | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
|
||||
| hbridge<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| hbridge<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| hbridge<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| hbridge<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| ncs | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| noe | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
|
||||
| nwe | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| quadA | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| quadB | IBUF | INPUT | LVCMOS25 | | | | IFF1 | | 0 / 3 |
|
||||
| reset | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
|
||||
| sram_data<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
| sram_data<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF1 | | 0 / 3 |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Timing Report
|
||||
--------------------------
|
||||
This design was not run using timing mode.
|
||||
|
||||
Section 11 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 12 - Control Set Information
|
||||
------------------------------------
|
||||
No control set information for this architecture.
|
||||
|
||||
Section 13 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
||||
3
Examples/Beta1/logic/build/project.ncd
Normal file
3
Examples/Beta1/logic/build/project.ncd
Normal file
File diff suppressed because one or more lines are too long
3
Examples/Beta1/logic/build/project.ngc
Normal file
3
Examples/Beta1/logic/build/project.ngc
Normal file
File diff suppressed because one or more lines are too long
153
Examples/Beta1/logic/build/project.ngc_xst.xrpt
Normal file
153
Examples/Beta1/logic/build/project.ngc_xst.xrpt
Normal file
@ -0,0 +1,153 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="lin64" product="ISE" version="12.2">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Sat Oct 30 18:30:37 2010">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="LD_LIBRARY_PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//lib/lin64:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//bin/lin64:/opt/e17/bin:/bin:/usr/locale/bin:/usr/bin:/sbin:/usr/sbin:/home/erwin/openwrt-xburst/bin/xburst:/home/erwin/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/:/usr/share/java/apache-ant/bin:/opt/java/bin:/opt/java/db/bin:/opt/java/jre/bin:/usr/lib/perl5/vendor_perl/bin:/usr/bin/perlbin/vendor:/usr/lib/perl5/core_perl/bin:/opt/qt/bin:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/:/opt/Xilinx/12.2/ISE_DS/ISE/:/usr/local/bin/:/home/erwin/ModelSim/modeltech/linux_x86_64"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE/"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="unknown"/>
|
||||
<item stringID="User_EnvOsrelease" value="unknown"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="dellerwin"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
|
||||
<item stringID="speed" value="2201.000 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="XST_OPTION_SUMMARY">
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="beta"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s500e-VQ100-4"/>
|
||||
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Area"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="project.src"/>
|
||||
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
|
||||
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="project.ngc"/>
|
||||
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
|
||||
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="yes"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="5"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="18">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="5"/>
|
||||
<item dataType="int" stringID="XST_3BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="10"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="8">
|
||||
<item dataType="int" stringID="XST_8BIT_COMPARATOR_LESS" value="4"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_TRISTATES" value="1"></item>
|
||||
<item dataType="int" stringID="XST_XORS" value="2">
|
||||
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
|
||||
<item dataType="int" stringID="XST_1BIT_XOR3" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="5"></item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="104">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="104"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="8">
|
||||
<item dataType="int" stringID="XST_8BIT_COMPARATOR_LESS" value="4"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_XORS" value="2">
|
||||
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
|
||||
<item dataType="int" stringID="XST_1BIT_XOR3" value="1"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="143">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="143"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REPORT">
|
||||
<section stringID="XST_FINAL_RESULTS">
|
||||
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="project.ngr"/>
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="project.ngc"/>
|
||||
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
|
||||
<item stringID="XST_OPTIMIZATION_GOAL" value="Area"/>
|
||||
<item stringID="XST_KEEP_HIERARCHY" value="no"/>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_STATISTICS">
|
||||
<item stringID="XST_IOS" value="32"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="239">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="11"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="28"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="38"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="55"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="60"/>
|
||||
<item dataType="int" stringID="XST_MUXF5" value="10"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XORCY" value="32"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="143">
|
||||
<item dataType="int" stringID="XST_FD" value="38"/>
|
||||
<item dataType="int" stringID="XST_FD1" value="23"/>
|
||||
<item dataType="int" stringID="XST_FDE" value="7"/>
|
||||
<item dataType="int" stringID="XST_FDR" value="42"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_RAMS" value="3">
|
||||
<item dataType="int" stringID="XST_RAMB16S9S9" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
|
||||
<item dataType="int" stringID="XST_BUFGP" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="31">
|
||||
<item dataType="int" stringID="XST_IBUF" value="19"/>
|
||||
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="8"/>
|
||||
<item dataType="int" stringID="XST_OBUF" value="4"/>
|
||||
</item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="3s500evq100-4"/>
|
||||
<item AVAILABLE="4656" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="108"/>
|
||||
<item AVAILABLE="9312" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="119"/>
|
||||
<item AVAILABLE="9312" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="135"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="32"/>
|
||||
<item AVAILABLE="66" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="32"/>
|
||||
<item AVAILABLE="20" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="3"/>
|
||||
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
3
Examples/Beta1/logic/build/project.ngd
Normal file
3
Examples/Beta1/logic/build/project.ngd
Normal file
File diff suppressed because one or more lines are too long
3
Examples/Beta1/logic/build/project.ngm
Normal file
3
Examples/Beta1/logic/build/project.ngm
Normal file
File diff suppressed because one or more lines are too long
3
Examples/Beta1/logic/build/project.ngr
Normal file
3
Examples/Beta1/logic/build/project.ngr
Normal file
File diff suppressed because one or more lines are too long
40
Examples/Beta1/logic/build/project.pcf
Normal file
40
Examples/Beta1/logic/build/project.pcf
Normal file
@ -0,0 +1,40 @@
|
||||
//! **************************************************************************
|
||||
// Written by: Map M.63c on Sat Oct 30 18:30:53 2010
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
COMP "addr<2>" LOCATE = SITE "P79" LEVEL 1;
|
||||
COMP "addr<3>" LOCATE = SITE "P78" LEVEL 1;
|
||||
COMP "addr<4>" LOCATE = SITE "P2" LEVEL 1;
|
||||
COMP "addr<5>" LOCATE = SITE "P3" LEVEL 1;
|
||||
COMP "addr<6>" LOCATE = SITE "P98" LEVEL 1;
|
||||
COMP "addr<7>" LOCATE = SITE "P95" LEVEL 1;
|
||||
COMP "clk" LOCATE = SITE "P38" LEVEL 1;
|
||||
COMP "addr<8>" LOCATE = SITE "P94" LEVEL 1;
|
||||
COMP "addr<9>" LOCATE = SITE "P92" LEVEL 1;
|
||||
COMP "sram_data<0>" LOCATE = SITE "P16" LEVEL 1;
|
||||
COMP "sram_data<1>" LOCATE = SITE "P15" LEVEL 1;
|
||||
COMP "sram_data<2>" LOCATE = SITE "P12" LEVEL 1;
|
||||
COMP "sram_data<3>" LOCATE = SITE "P11" LEVEL 1;
|
||||
COMP "sram_data<4>" LOCATE = SITE "P10" LEVEL 1;
|
||||
COMP "sram_data<5>" LOCATE = SITE "P9" LEVEL 1;
|
||||
COMP "sram_data<6>" LOCATE = SITE "P5" LEVEL 1;
|
||||
COMP "addr<10>" LOCATE = SITE "P85" LEVEL 1;
|
||||
COMP "sram_data<7>" LOCATE = SITE "P4" LEVEL 1;
|
||||
COMP "addr<11>" LOCATE = SITE "P91" LEVEL 1;
|
||||
COMP "addr<12>" LOCATE = SITE "P90" LEVEL 1;
|
||||
COMP "ncs" LOCATE = SITE "P69" LEVEL 1;
|
||||
COMP "noe" LOCATE = SITE "P86" LEVEL 1;
|
||||
COMP "hbridge<0>" LOCATE = SITE "P48" LEVEL 1;
|
||||
COMP "hbridge<1>" LOCATE = SITE "P49" LEVEL 1;
|
||||
COMP "hbridge<2>" LOCATE = SITE "P54" LEVEL 1;
|
||||
COMP "hbridge<3>" LOCATE = SITE "P53" LEVEL 1;
|
||||
COMP "quadA" LOCATE = SITE "P67" LEVEL 1;
|
||||
COMP "quadB" LOCATE = SITE "P68" LEVEL 1;
|
||||
COMP "nwe" LOCATE = SITE "P88" LEVEL 1;
|
||||
COMP "reset" LOCATE = SITE "P30" LEVEL 1;
|
||||
COMP "addr<0>" LOCATE = SITE "P84" LEVEL 1;
|
||||
COMP "addr<1>" LOCATE = SITE "P83" LEVEL 1;
|
||||
NET "clk_BUFGP/IBUFG" BEL "clk_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
|
||||
SCHEMATIC END;
|
||||
|
||||
4
Examples/Beta1/logic/build/project.src
Normal file
4
Examples/Beta1/logic/build/project.src
Normal file
@ -0,0 +1,4 @@
|
||||
verilog work ../beta.v
|
||||
verilog work ../PuenteH.v
|
||||
verilog work ../PWM.v
|
||||
verilog work ../enco.v
|
||||
10
Examples/Beta1/logic/build/project.xst
Normal file
10
Examples/Beta1/logic/build/project.xst
Normal file
@ -0,0 +1,10 @@
|
||||
run
|
||||
-top beta
|
||||
-p xc3s500e-VQ100-4
|
||||
-opt_mode Area
|
||||
-opt_level 1
|
||||
-ifn project.src
|
||||
-ifmt mixed
|
||||
-ofn project.ngc
|
||||
-ofmt NGC
|
||||
-rtlview yes
|
||||
107
Examples/Beta1/logic/build/project_ngdbuild.xrpt
Normal file
107
Examples/Beta1/logic/build/project_ngdbuild.xrpt
Normal file
@ -0,0 +1,107 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="lin64" product="ISE" version="12.2">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Sat Oct 30 18:30:49 2010">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="LD_LIBRARY_PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//lib/lin64:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATH"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE//bin/lin64:/opt/e17/bin:/bin:/usr/locale/bin:/usr/bin:/sbin:/usr/sbin:/home/erwin/openwrt-xburst/bin/xburst:/home/erwin/openwrt-xburst/staging_dir/toolchain-mipsel_gcc-4.3.3+cs_uClibc-0.9.30.1/usr/bin/:/usr/share/java/apache-ant/bin:/opt/java/bin:/opt/java/db/bin:/opt/java/jre/bin:/usr/lib/perl5/vendor_perl/bin:/usr/bin/perlbin/vendor:/usr/lib/perl5/core_perl/bin:/opt/qt/bin:/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/:/opt/Xilinx/12.2/ISE_DS/ISE/:/usr/local/bin/:/home/erwin/ModelSim/modeltech/linux_x86_64"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="/home/erwin/Xilinxs/12.2/ISE_DS/ISE/"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="unknown"/>
|
||||
<item stringID="User_EnvOsrelease" value="unknown"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="dellerwin"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
|
||||
<item stringID="speed" value="2201.000 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<task stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<section stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc3s500e-VQ100-4"/>
|
||||
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="../beta.ucf"/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="NGDBUILD_REPORT">
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="42"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE_1" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="23"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="19"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="28"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="55"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="60"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="32"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="7"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="42"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE_1" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD_1" value="23"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="27"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="28"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="38"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="55"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="60"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="8"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_RAMB16_S9_S9" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="32"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES"/>
|
||||
</section>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
96
Examples/Beta1/logic/build/project_r.bgn
Normal file
96
Examples/Beta1/logic/build/project_r.bgn
Normal file
@ -0,0 +1,96 @@
|
||||
Release 12.2 - Bitgen M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
Loading device for application Rf_Device from file '3s500e.nph' in environment
|
||||
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
|
||||
"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
|
||||
|
||||
Sat Oct 30 18:31:21 2010
|
||||
|
||||
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -l -w -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK project_r.ncd
|
||||
|
||||
INFO:Bitgen:275 - Spartan-3E devices do not support bitstream readback of the
|
||||
Blockram resources in the -4C speedgrade. If Blockram readback functionality
|
||||
is desired, it is suggested to target the -5C or -4I speedgrades.
|
||||
Summary of Bitgen Options:
|
||||
+----------------------+----------------------+
|
||||
| Option Name | Current Setting |
|
||||
+----------------------+----------------------+
|
||||
| Compress | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| Readback | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| CRC | Enable** |
|
||||
+----------------------+----------------------+
|
||||
| DebugBitstream | No* |
|
||||
+----------------------+----------------------+
|
||||
| ConfigRate | 1* |
|
||||
+----------------------+----------------------+
|
||||
| StartupClk | Cclk** |
|
||||
+----------------------+----------------------+
|
||||
| DCMShutdown | Disable* |
|
||||
+----------------------+----------------------+
|
||||
| DonePin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| ProgPin | Pullup* |
|
||||
+----------------------+----------------------+
|
||||
| TckPin | Pullup* |
|
||||
+----------------------+----------------------+
|
||||
| TdiPin | Pullup* |
|
||||
+----------------------+----------------------+
|
||||
| TdoPin | Pullnone |
|
||||
+----------------------+----------------------+
|
||||
| TmsPin | Pullup* |
|
||||
+----------------------+----------------------+
|
||||
| UnusedPin | Pulldown* |
|
||||
+----------------------+----------------------+
|
||||
| GWE_cycle | 6* |
|
||||
+----------------------+----------------------+
|
||||
| GTS_cycle | 5* |
|
||||
+----------------------+----------------------+
|
||||
| LCK_cycle | NoWait* |
|
||||
+----------------------+----------------------+
|
||||
| DONE_cycle | 4* |
|
||||
+----------------------+----------------------+
|
||||
| Persist | No* |
|
||||
+----------------------+----------------------+
|
||||
| DriveDone | No* |
|
||||
+----------------------+----------------------+
|
||||
| DonePipe | No* |
|
||||
+----------------------+----------------------+
|
||||
| Security | None* |
|
||||
+----------------------+----------------------+
|
||||
| UserID | 0xFFFFFFFF* |
|
||||
+----------------------+----------------------+
|
||||
| MultiBootMode | No* |
|
||||
+----------------------+----------------------+
|
||||
| ActivateGclk | No* |
|
||||
+----------------------+----------------------+
|
||||
| ActiveReconfig | No* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask0 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask1 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask2 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialGclk | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialLeft | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialRight | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| IEEE1532 | No* |
|
||||
+----------------------+----------------------+
|
||||
| Binary | No* |
|
||||
+----------------------+----------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
No constraints file was processed.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Saving ll file in "project_r.ll".
|
||||
Creating bit map...
|
||||
Saving bit stream in "project_r.bit".
|
||||
Bitstream generation is complete.
|
||||
8
Examples/Beta1/logic/build/project_r.drc
Normal file
8
Examples/Beta1/logic/build/project_r.drc
Normal file
@ -0,0 +1,8 @@
|
||||
Release 12.2 Drc M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sat Oct 30 18:31:21 2010
|
||||
|
||||
drc -z project_r.ncd
|
||||
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
55517
Examples/Beta1/logic/build/project_r.ll
Normal file
55517
Examples/Beta1/logic/build/project_r.ll
Normal file
File diff suppressed because it is too large
Load Diff
3
Examples/Beta1/logic/build/project_r.ncd
Normal file
3
Examples/Beta1/logic/build/project_r.ncd
Normal file
File diff suppressed because one or more lines are too long
130
Examples/Beta1/logic/build/project_r.pad
Normal file
130
Examples/Beta1/logic/build/project_r.pad
Normal file
@ -0,0 +1,130 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sat Oct 30 18:31:15 2010
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
INPUT FILE: project.ncd
|
||||
OUTPUT FILE: project_r.pad
|
||||
PART TYPE: xc3s500e
|
||||
SPEED GRADE: -4
|
||||
PACKAGE: vq100
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
P1|||PROG_B||||||||||||
|
||||
P2|addr<4>|IBUF|IO_L01P_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
|
||||
P3|addr<5>|IBUF|IO_L01N_3|INPUT|LVCMOS25*|3||||IFD||LOCATED|YES|NONE|
|
||||
P4|sram_data<7>|IOB|IO_L02P_3|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P5|sram_data<6>|IOB|IO_L02N_3/VREF_3|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P6|||VCCINT||||||||1.2||||
|
||||
P7|||GND||||||||||||
|
||||
P8|||VCCO_3|||3|||||2.50||||
|
||||
P9|sram_data<5>|IOB|IO_L03P_3/LHCLK0|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P10|sram_data<4>|IOB|IO_L03N_3/LHCLK1|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P11|sram_data<3>|IOB|IO_L04P_3/LHCLK2|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P12|sram_data<2>|IOB|IO_L04N_3/LHCLK3/IRDY2|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P13||IBUF|IP|UNUSED||3|||||||||
|
||||
P14|||GND||||||||||||
|
||||
P15|sram_data<1>|IOB|IO_L05P_3/LHCLK4/TRDY2|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P16|sram_data<0>|IOB|IO_L05N_3/LHCLK5|BIDIR|LVCMOS25*|3|12|SLOW|NONE**|IFD||LOCATED|YES|NONE|
|
||||
P17||DIFFM|IO_L06P_3/LHCLK6|UNUSED||3|||||||||
|
||||
P18||DIFFS|IO_L06N_3/LHCLK7|UNUSED||3|||||||||
|
||||
P19|||GND||||||||||||
|
||||
P20|||VCCO_3|||3|||||2.50||||
|
||||
P21|||VCCAUX||||||||2.5||||
|
||||
P22||DIFFM|IO_L07P_3|UNUSED||3|||||||||
|
||||
P23||DIFFS|IO_L07N_3|UNUSED||3|||||||||
|
||||
P24||DIFFM|IO_L01P_2/CSO_B|UNUSED||2|||||||||
|
||||
P25||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
|
||||
P26||DIFFM|IO_L02P_2/DOUT/BUSY|UNUSED||2|||||||||
|
||||
P27||DIFFS|IO_L02N_2/MOSI/CSI_B|UNUSED||2|||||||||
|
||||
P28|||VCCINT||||||||1.2||||
|
||||
P29|||GND||||||||||||
|
||||
P30|reset|IBUF|IP/VREF_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
|
||||
P31|||VCCO_2|||2|||||2.50||||
|
||||
P32||DIFFM|IO_L03P_2/D7/GCLK12|UNUSED||2|||||||||
|
||||
P33||DIFFS|IO_L03N_2/D6/GCLK13|UNUSED||2|||||||||
|
||||
P34||IOB|IO/D5|UNUSED||2|||||||||
|
||||
P35||DIFFM|IO_L04P_2/D4/GCLK14|UNUSED||2|||||||||
|
||||
P36||DIFFS|IO_L04N_2/D3/GCLK15|UNUSED||2|||||||||
|
||||
P37|||GND||||||||||||
|
||||
P38|clk|IBUF|IP_L05P_2/RDWR_B/GCLK0|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
|
||||
P39||DIFFSI|IP_L05N_2/M2/GCLK1|UNUSED||2|||||||||
|
||||
P40||DIFFM|IO_L06P_2/D2/GCLK2|UNUSED||2|||||||||
|
||||
P41||DIFFS|IO_L06N_2/D1/GCLK3|UNUSED||2|||||||||
|
||||
P42||IOB|IO/M1|UNUSED||2|||||||||
|
||||
P43||DIFFM|IO_L07P_2/M0|UNUSED||2|||||||||
|
||||
P44||DIFFS|IO_L07N_2/DIN/D0|UNUSED||2|||||||||
|
||||
P45|||VCCO_2|||2|||||2.50||||
|
||||
P46|||VCCAUX||||||||2.5||||
|
||||
P47||DIFFM|IO_L08P_2/VS2|UNUSED||2|||||||||
|
||||
P48|hbridge<0>|IOB|IO_L08N_2/VS1|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P49|hbridge<1>|IOB|IO_L09P_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P50||DIFFS|IO_L09N_2/CCLK|UNUSED||2|||||||||
|
||||
P51|||DONE||||||||||||
|
||||
P52|||GND||||||||||||
|
||||
P53|hbridge<3>|IOB|IO_L01P_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P54|hbridge<2>|IOB|IO_L01N_1|OUTPUT|LVCMOS25*|1|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P55|||VCCO_1|||1|||||2.50||||
|
||||
P56|||VCCINT||||||||1.2||||
|
||||
P57||DIFFM|IO_L02P_1|UNUSED||1|||||||||
|
||||
P58||DIFFS|IO_L02N_1|UNUSED||1|||||||||
|
||||
P59|||GND||||||||||||
|
||||
P60||DIFFM|IO_L03P_1/RHCLK0|UNUSED||1|||||||||
|
||||
P61||DIFFS|IO_L03N_1/RHCLK1|UNUSED||1|||||||||
|
||||
P62||DIFFM|IO_L04P_1/RHCLK2|UNUSED||1|||||||||
|
||||
P63||DIFFS|IO_L04N_1/RHCLK3/TRDY1|UNUSED||1|||||||||
|
||||
P64|||GND||||||||||||
|
||||
P65||DIFFM|IO_L05P_1/RHCLK4/IRDY1|UNUSED||1|||||||||
|
||||
P66||DIFFS|IO_L05N_1/RHCLK5|UNUSED||1|||||||||
|
||||
P67|quadA|IBUF|IO_L06P_1/RHCLK6|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
|
||||
P68|quadB|IBUF|IO_L06N_1/RHCLK7|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
|
||||
P69|ncs|IBUF|IP/VREF_1|INPUT|LVCMOS25*|1||||IFD||LOCATED|YES|NONE|
|
||||
P70||DIFFM|IO_L07P_1|UNUSED||1|||||||||
|
||||
P71||DIFFS|IO_L07N_1|UNUSED||1|||||||||
|
||||
P72|||GND||||||||||||
|
||||
P73|||VCCO_1|||1|||||2.50||||
|
||||
P74|||VCCAUX||||||||2.5||||
|
||||
P75|||TMS||||||||||||
|
||||
P76|||TDO||||||||||||
|
||||
P77|||TCK||||||||||||
|
||||
P78|addr<3>|IBUF|IO_L01P_0|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P79|addr<2>|IBUF|IO_L01N_0|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P80|||VCCINT||||||||1.2||||
|
||||
P81|||GND||||||||||||
|
||||
P82|||VCCO_0|||0|||||2.50||||
|
||||
P83|addr<1>|IBUF|IO_L02P_0/GCLK4|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P84|addr<0>|IBUF|IO_L02N_0/GCLK5|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P85|addr<10>|IBUF|IO_L03P_0/GCLK6|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P86|noe|IBUF|IO_L03N_0/GCLK7|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE|
|
||||
P87|||GND||||||||||||
|
||||
P88|nwe|IBUF|IP_L04P_0/GCLK8|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P89||DIFFSI|IP_L04N_0/GCLK9|UNUSED||0|||||||||
|
||||
P90|addr<12>|IBUF|IO_L05P_0/GCLK10|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P91|addr<11>|IBUF|IO_L05N_0/GCLK11|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P92|addr<9>|IBUF|IO|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P93|||GND||||||||||||
|
||||
P94|addr<8>|IBUF|IO_L06P_0|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P95|addr<7>|IBUF|IO_L06N_0/VREF_0|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P96|||VCCAUX||||||||2.5||||
|
||||
P97|||VCCO_0|||0|||||2.50||||
|
||||
P98|addr<6>|IBUF|IO_L07P_0|INPUT|LVCMOS25*|0||||IFD||LOCATED|YES|NONE|
|
||||
P99||DIFFS|IO_L07N_0/HSWAP|UNUSED||0|||||||||
|
||||
P100|||TDI||||||||||||
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
203
Examples/Beta1/logic/build/project_r.par
Normal file
203
Examples/Beta1/logic/build/project_r.par
Normal file
@ -0,0 +1,203 @@
|
||||
Release 12.2 par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
dellerwin:: Sat Oct 30 18:30:55 2010
|
||||
|
||||
par -w project.ncd project_r.ncd
|
||||
|
||||
|
||||
Constraints file: project.pcf.
|
||||
Loading device for application Rf_Device from file '3s500e.nph' in environment /home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
|
||||
"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
|
||||
|
||||
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
|
||||
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
|
||||
|
||||
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
|
||||
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
|
||||
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
|
||||
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
|
||||
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
||||
|
||||
Device speed data version: "PRODUCTION 1.27 2010-06-22".
|
||||
|
||||
|
||||
Design Summary Report:
|
||||
|
||||
Number of External IOBs 32 out of 66 48%
|
||||
|
||||
Number of External Input IOBs 20
|
||||
|
||||
Number of External Input IBUFs 20
|
||||
Number of LOCed External Input IBUFs 20 out of 20 100%
|
||||
|
||||
|
||||
Number of External Output IOBs 4
|
||||
|
||||
Number of External Output IOBs 4
|
||||
Number of LOCed External Output IOBs 4 out of 4 100%
|
||||
|
||||
|
||||
Number of External Bidir IOBs 8
|
||||
|
||||
Number of External Bidir IOBs 8
|
||||
Number of LOCed External Bidir IOBs 8 out of 8 100%
|
||||
|
||||
|
||||
Number of BUFGMUXs 1 out of 24 4%
|
||||
Number of RAMB16s 3 out of 20 15%
|
||||
Number of Slices 112 out of 4656 2%
|
||||
Number of SLICEMs 0 out of 2328 0%
|
||||
|
||||
|
||||
|
||||
Overall effort level (-ol): Standard
|
||||
Placer effort level (-pl): High
|
||||
Placer cost table entry (-t): 1
|
||||
Router effort level (-rl): High
|
||||
|
||||
Starting initial Timing Analysis. REAL time: 1 secs
|
||||
Finished initial Timing Analysis. REAL time: 1 secs
|
||||
|
||||
|
||||
Starting Placer
|
||||
Total REAL time at the beginning of Placer: 2 secs
|
||||
Total CPU time at the beginning of Placer: 1 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:1010e082) REAL time: 2 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:1010e082) REAL time: 2 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:1010e082) REAL time: 2 secs
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement (Checksum:40d1a052) REAL time: 2 secs
|
||||
|
||||
Phase 5.30 Global Clock Region Assignment
|
||||
Phase 5.30 Global Clock Region Assignment (Checksum:40d1a052) REAL time: 2 secs
|
||||
|
||||
Phase 6.36 Local Placement Optimization
|
||||
Phase 6.36 Local Placement Optimization (Checksum:40d1a052) REAL time: 2 secs
|
||||
|
||||
Phase 7.8 Global Placement
|
||||
...
|
||||
...
|
||||
..........
|
||||
...
|
||||
...
|
||||
Phase 7.8 Global Placement (Checksum:a2a5832f) REAL time: 9 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:a2a5832f) REAL time: 9 secs
|
||||
|
||||
Phase 9.18 Placement Optimization
|
||||
Phase 9.18 Placement Optimization (Checksum:14df4917) REAL time: 10 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:14df4917) REAL time: 10 secs
|
||||
|
||||
Total REAL time to Placer completion: 10 secs
|
||||
Total CPU time to Placer completion: 10 secs
|
||||
Writing design to file project_r.ncd
|
||||
|
||||
|
||||
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 712 unrouted; REAL time: 15 secs
|
||||
|
||||
Phase 2 : 603 unrouted; REAL time: 15 secs
|
||||
|
||||
Phase 3 : 133 unrouted; REAL time: 16 secs
|
||||
|
||||
Phase 4 : 162 unrouted; (Par is working to improve performance) REAL time: 16 secs
|
||||
|
||||
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
|
||||
|
||||
Updating file: project_r.ncd with current fully routed design.
|
||||
|
||||
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
|
||||
|
||||
Total REAL time to Router completion: 19 secs
|
||||
Total CPU time to Router completion: 18 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
**************************
|
||||
Generating Clock Report
|
||||
**************************
|
||||
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| clk_BUFGP | BUFGMUX_X2Y1| No | 90 | 0.078 | 0.204 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
only delays for the net. Note this is different from Clock Skew which
|
||||
is reported in TRCE timing report. Clock Skew is the difference between
|
||||
the minimum and maximum path delays which includes logic delays.
|
||||
|
||||
Timing Score: 0 (Setup: 0, Hold: 0)
|
||||
|
||||
Asterisk (*) preceding a constraint indicates it was not met.
|
||||
This may be due to a setup or hold violation.
|
||||
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Autotimespec constraint for clock net clk | SETUP | N/A| 9.582ns| N/A| 0
|
||||
_BUFGP | HOLD | 0.968ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
All constraints were met.
|
||||
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
|
||||
constraint is not analyzed due to the following: No paths covered by this
|
||||
constraint; Other constraints intersect with this constraint; or This
|
||||
constraint was disabled by a Path Tracing Control. Please run the Timespec
|
||||
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
|
||||
|
||||
|
||||
Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 19 secs
|
||||
Total CPU time to PAR completion: 19 secs
|
||||
|
||||
Peak Memory Usage: 365 MB
|
||||
|
||||
Placement: Completed - No errors found.
|
||||
Routing: Completed - No errors found.
|
||||
|
||||
Number of error messages: 0
|
||||
Number of warning messages: 0
|
||||
Number of info messages: 1
|
||||
|
||||
Writing design to file project_r.ncd
|
||||
|
||||
|
||||
|
||||
PAR done!
|
||||
332
Examples/Beta1/logic/build/project_r.ptwx
Normal file
332
Examples/Beta1/logic/build/project_r.ptwx
Normal file
@ -0,0 +1,332 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.582" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt><twInfo anchorID="4">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
|
||||
139
Examples/Beta1/logic/build/project_r.twr
Normal file
139
Examples/Beta1/logic/build/project_r.twr
Normal file
@ -0,0 +1,139 @@
|
||||
--------------------------------------------------------------------------------
|
||||
Release 12.2 Trace (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 25
|
||||
project_r.ncd project.pcf
|
||||
|
||||
Design file: project_r.ncd
|
||||
Physical constraint file: project.pcf
|
||||
Device,package,speed: xc3s500e,vq100,-4 (PRODUCTION 1.27 2010-06-22)
|
||||
Report level: verbose report, limited to 25 items per constraint
|
||||
|
||||
Environment Variable Effect
|
||||
-------------------- ------
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
unconstrained paths section(s) of the report.
|
||||
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
a 50 Ohm transmission line loading model. For the details of this model,
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
INFO:Timing:3390 - This architecture does not support a default System Jitter
|
||||
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
|
||||
Uncertainty calculation.
|
||||
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
|
||||
'Phase Error' calculations, these terms will be zero in the Clock
|
||||
Uncertainty calculation. Please make appropriate modification to
|
||||
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
|
||||
Error.
|
||||
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
-----------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
Setup/Hold to clock clk
|
||||
------------+------------+------------+------------------+--------+
|
||||
|Max Setup to|Max Hold to | | Clock |
|
||||
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
|
||||
------------+------------+------------+------------------+--------+
|
||||
addr<0> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
|
||||
addr<1> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
|
||||
addr<2> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
|
||||
addr<3> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
|
||||
addr<4> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
|
||||
addr<5> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
|
||||
addr<6> | 4.650(F)| -0.772(F)|clk_BUFGP | 0.000|
|
||||
addr<7> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
|
||||
addr<8> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
|
||||
addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
|
||||
addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
|
||||
addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
|
||||
addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
|
||||
ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
|
||||
nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
|
||||
quadA | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
|
||||
quadB | 4.665(R)| -0.791(R)|clk_BUFGP | 0.000|
|
||||
reset | 3.592(R)| -0.849(R)|clk_BUFGP | 0.000|
|
||||
| 3.855(F)| -0.185(F)|clk_BUFGP | 0.000|
|
||||
sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<3>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<4>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
|
||||
sram_data<5>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
|
||||
sram_data<6>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
|
||||
sram_data<7>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
|
||||
------------+------------+------------+------------------+--------+
|
||||
|
||||
Clock clk to Pad
|
||||
------------+------------+------------------+--------+
|
||||
| clk (edge) | | Clock |
|
||||
Destination | to PAD |Internal Clock(s) | Phase |
|
||||
------------+------------+------------------+--------+
|
||||
hbridge<0> | 13.931(R)|clk_BUFGP | 0.000|
|
||||
| 14.353(F)|clk_BUFGP | 0.000|
|
||||
hbridge<1> | 12.746(R)|clk_BUFGP | 0.000|
|
||||
| 12.864(F)|clk_BUFGP | 0.000|
|
||||
hbridge<2> | 13.504(R)|clk_BUFGP | 0.000|
|
||||
| 13.837(F)|clk_BUFGP | 0.000|
|
||||
hbridge<3> | 12.556(R)|clk_BUFGP | 0.000|
|
||||
| 12.505(F)|clk_BUFGP | 0.000|
|
||||
sram_data<0>| 12.178(F)|clk_BUFGP | 0.000|
|
||||
sram_data<1>| 12.129(F)|clk_BUFGP | 0.000|
|
||||
sram_data<2>| 11.885(F)|clk_BUFGP | 0.000|
|
||||
sram_data<3>| 12.212(F)|clk_BUFGP | 0.000|
|
||||
sram_data<4>| 11.613(F)|clk_BUFGP | 0.000|
|
||||
sram_data<5>| 11.936(F)|clk_BUFGP | 0.000|
|
||||
sram_data<6>| 12.842(F)|clk_BUFGP | 0.000|
|
||||
sram_data<7>| 12.678(F)|clk_BUFGP | 0.000|
|
||||
------------+------------+------------------+--------+
|
||||
|
||||
Clock to Setup on destination clock clk
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
clk | 6.238| 4.791| 4.655| 9.476|
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
Pad to Pad
|
||||
---------------+---------------+---------+
|
||||
Source Pad |Destination Pad| Delay |
|
||||
---------------+---------------+---------+
|
||||
ncs |sram_data<0> | 8.523|
|
||||
ncs |sram_data<1> | 9.355|
|
||||
ncs |sram_data<2> | 8.852|
|
||||
ncs |sram_data<3> | 9.607|
|
||||
ncs |sram_data<4> | 8.850|
|
||||
ncs |sram_data<5> | 8.354|
|
||||
ncs |sram_data<6> | 9.662|
|
||||
ncs |sram_data<7> | 9.907|
|
||||
noe |sram_data<0> | 8.646|
|
||||
noe |sram_data<1> | 9.478|
|
||||
noe |sram_data<2> | 8.975|
|
||||
noe |sram_data<3> | 9.730|
|
||||
noe |sram_data<4> | 8.973|
|
||||
noe |sram_data<5> | 8.477|
|
||||
noe |sram_data<6> | 9.785|
|
||||
noe |sram_data<7> | 10.030|
|
||||
---------------+---------------+---------+
|
||||
|
||||
|
||||
Analysis completed Sat Oct 30 18:31:18 2010
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
-------------------------
|
||||
Trace Settings
|
||||
|
||||
Peak Memory Usage: 239 MB
|
||||
|
||||
|
||||
|
||||
338
Examples/Beta1/logic/build/project_r.twx
Normal file
338
Examples/Beta1/logic/build/project_r.twx
Normal file
File diff suppressed because one or more lines are too long
9
Examples/Beta1/logic/build/project_r.unroutes
Normal file
9
Examples/Beta1/logic/build/project_r.unroutes
Normal file
@ -0,0 +1,9 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sat Oct 30 18:31:15 2010
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
|
||||
3
Examples/Beta1/logic/build/project_r.xpi
Normal file
3
Examples/Beta1/logic/build/project_r.xpi
Normal file
@ -0,0 +1,3 @@
|
||||
PROGRAM=PAR
|
||||
STATE=ROUTED
|
||||
TIMESPECS_MET=OFF
|
||||
7
Examples/Beta1/logic/build/project_r_bitgen.xwbt
Normal file
7
Examples/Beta1/logic/build/project_r_bitgen.xwbt
Normal file
@ -0,0 +1,7 @@
|
||||
INFILE=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project_r.ncd
|
||||
OUTFILE=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build/project_r.bit
|
||||
FAMILY=Spartan3E
|
||||
PART=xc3s500e-4vq100
|
||||
WORKINGDIR=/home/erwin/sie-ceimtun/Examples/Beta1/logic/build
|
||||
LICENSE=WebPack
|
||||
USER_INFO=0_0_674
|
||||
131
Examples/Beta1/logic/build/project_r_pad.csv
Normal file
131
Examples/Beta1/logic/build/project_r_pad.csv
Normal file
@ -0,0 +1,131 @@
|
||||
#Release 12.2 - par M.63c (lin64)
|
||||
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Sat Oct 30 18:31:15 2010
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
#INPUT FILE: project.ncd
|
||||
#OUTPUT FILE: project_r_pad.csv
|
||||
#PART TYPE: xc3s500e
|
||||
#SPEED GRADE: -4
|
||||
#PACKAGE: vq100
|
||||
#
|
||||
# Pinout by Pin Number:
|
||||
#
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
|
||||
P1,,,PROG_B,,,,,,,,,,,,
|
||||
P2,addr<4>,IBUF,IO_L01P_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
|
||||
P3,addr<5>,IBUF,IO_L01N_3,INPUT,LVCMOS25*,3,,,,IFD,,LOCATED,YES,NONE,
|
||||
P4,sram_data<7>,IOB,IO_L02P_3,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P5,sram_data<6>,IOB,IO_L02N_3/VREF_3,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P6,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P7,,,GND,,,,,,,,,,,,
|
||||
P8,,,VCCO_3,,,3,,,,,2.50,,,,
|
||||
P9,sram_data<5>,IOB,IO_L03P_3/LHCLK0,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P10,sram_data<4>,IOB,IO_L03N_3/LHCLK1,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P11,sram_data<3>,IOB,IO_L04P_3/LHCLK2,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P12,sram_data<2>,IOB,IO_L04N_3/LHCLK3/IRDY2,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P13,,IBUF,IP,UNUSED,,3,,,,,,,,,
|
||||
P14,,,GND,,,,,,,,,,,,
|
||||
P15,sram_data<1>,IOB,IO_L05P_3/LHCLK4/TRDY2,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P16,sram_data<0>,IOB,IO_L05N_3/LHCLK5,BIDIR,LVCMOS25*,3,12,SLOW,NONE**,IFD,,LOCATED,YES,NONE,
|
||||
P17,,DIFFM,IO_L06P_3/LHCLK6,UNUSED,,3,,,,,,,,,
|
||||
P18,,DIFFS,IO_L06N_3/LHCLK7,UNUSED,,3,,,,,,,,,
|
||||
P19,,,GND,,,,,,,,,,,,
|
||||
P20,,,VCCO_3,,,3,,,,,2.50,,,,
|
||||
P21,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P22,,DIFFM,IO_L07P_3,UNUSED,,3,,,,,,,,,
|
||||
P23,,DIFFS,IO_L07N_3,UNUSED,,3,,,,,,,,,
|
||||
P24,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,,
|
||||
P25,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,,
|
||||
P26,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,,
|
||||
P27,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,,
|
||||
P28,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P29,,,GND,,,,,,,,,,,,
|
||||
P30,reset,IBUF,IP/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
|
||||
P31,,,VCCO_2,,,2,,,,,2.50,,,,
|
||||
P32,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
|
||||
P33,,DIFFS,IO_L03N_2/D6/GCLK13,UNUSED,,2,,,,,,,,,
|
||||
P34,,IOB,IO/D5,UNUSED,,2,,,,,,,,,
|
||||
P35,,DIFFM,IO_L04P_2/D4/GCLK14,UNUSED,,2,,,,,,,,,
|
||||
P36,,DIFFS,IO_L04N_2/D3/GCLK15,UNUSED,,2,,,,,,,,,
|
||||
P37,,,GND,,,,,,,,,,,,
|
||||
P38,clk,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
|
||||
P39,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
|
||||
P40,,DIFFM,IO_L06P_2/D2/GCLK2,UNUSED,,2,,,,,,,,,
|
||||
P41,,DIFFS,IO_L06N_2/D1/GCLK3,UNUSED,,2,,,,,,,,,
|
||||
P42,,IOB,IO/M1,UNUSED,,2,,,,,,,,,
|
||||
P43,,DIFFM,IO_L07P_2/M0,UNUSED,,2,,,,,,,,,
|
||||
P44,,DIFFS,IO_L07N_2/DIN/D0,UNUSED,,2,,,,,,,,,
|
||||
P45,,,VCCO_2,,,2,,,,,2.50,,,,
|
||||
P46,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P47,,DIFFM,IO_L08P_2/VS2,UNUSED,,2,,,,,,,,,
|
||||
P48,hbridge<0>,IOB,IO_L08N_2/VS1,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P49,hbridge<1>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
|
||||
P51,,,DONE,,,,,,,,,,,,
|
||||
P52,,,GND,,,,,,,,,,,,
|
||||
P53,hbridge<3>,IOB,IO_L01P_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P54,hbridge<2>,IOB,IO_L01N_1,OUTPUT,LVCMOS25*,1,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P55,,,VCCO_1,,,1,,,,,2.50,,,,
|
||||
P56,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P57,,DIFFM,IO_L02P_1,UNUSED,,1,,,,,,,,,
|
||||
P58,,DIFFS,IO_L02N_1,UNUSED,,1,,,,,,,,,
|
||||
P59,,,GND,,,,,,,,,,,,
|
||||
P60,,DIFFM,IO_L03P_1/RHCLK0,UNUSED,,1,,,,,,,,,
|
||||
P61,,DIFFS,IO_L03N_1/RHCLK1,UNUSED,,1,,,,,,,,,
|
||||
P62,,DIFFM,IO_L04P_1/RHCLK2,UNUSED,,1,,,,,,,,,
|
||||
P63,,DIFFS,IO_L04N_1/RHCLK3/TRDY1,UNUSED,,1,,,,,,,,,
|
||||
P64,,,GND,,,,,,,,,,,,
|
||||
P65,,DIFFM,IO_L05P_1/RHCLK4/IRDY1,UNUSED,,1,,,,,,,,,
|
||||
P66,,DIFFS,IO_L05N_1/RHCLK5,UNUSED,,1,,,,,,,,,
|
||||
P67,quadA,IBUF,IO_L06P_1/RHCLK6,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
|
||||
P68,quadB,IBUF,IO_L06N_1/RHCLK7,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
|
||||
P69,ncs,IBUF,IP/VREF_1,INPUT,LVCMOS25*,1,,,,IFD,,LOCATED,YES,NONE,
|
||||
P70,,DIFFM,IO_L07P_1,UNUSED,,1,,,,,,,,,
|
||||
P71,,DIFFS,IO_L07N_1,UNUSED,,1,,,,,,,,,
|
||||
P72,,,GND,,,,,,,,,,,,
|
||||
P73,,,VCCO_1,,,1,,,,,2.50,,,,
|
||||
P74,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P75,,,TMS,,,,,,,,,,,,
|
||||
P76,,,TDO,,,,,,,,,,,,
|
||||
P77,,,TCK,,,,,,,,,,,,
|
||||
P78,addr<3>,IBUF,IO_L01P_0,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P79,addr<2>,IBUF,IO_L01N_0,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P80,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P81,,,GND,,,,,,,,,,,,
|
||||
P82,,,VCCO_0,,,0,,,,,2.50,,,,
|
||||
P83,addr<1>,IBUF,IO_L02P_0/GCLK4,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P84,addr<0>,IBUF,IO_L02N_0/GCLK5,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P85,addr<10>,IBUF,IO_L03P_0/GCLK6,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P86,noe,IBUF,IO_L03N_0/GCLK7,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE,
|
||||
P87,,,GND,,,,,,,,,,,,
|
||||
P88,nwe,IBUF,IP_L04P_0/GCLK8,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P89,,DIFFSI,IP_L04N_0/GCLK9,UNUSED,,0,,,,,,,,,
|
||||
P90,addr<12>,IBUF,IO_L05P_0/GCLK10,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P91,addr<11>,IBUF,IO_L05N_0/GCLK11,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P92,addr<9>,IBUF,IO,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P93,,,GND,,,,,,,,,,,,
|
||||
P94,addr<8>,IBUF,IO_L06P_0,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P95,addr<7>,IBUF,IO_L06N_0/VREF_0,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P96,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P97,,,VCCO_0,,,0,,,,,2.50,,,,
|
||||
P98,addr<6>,IBUF,IO_L07P_0,INPUT,LVCMOS25*,0,,,,IFD,,LOCATED,YES,NONE,
|
||||
P99,,DIFFS,IO_L07N_0/HSWAP,UNUSED,,0,,,,,,,,,
|
||||
P100,,,TDI,,,,,,,,,,,,
|
||||
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
#
|
||||
#* Default value.
|
||||
#** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
#****** Special VCCO requirements may apply. Please consult the device
|
||||
# family datasheet for specific guideline on VCCO requirements.
|
||||
#
|
||||
#
|
||||
#
|
||||
|
130
Examples/Beta1/logic/build/project_r_pad.txt
Normal file
130
Examples/Beta1/logic/build/project_r_pad.txt
Normal file
@ -0,0 +1,130 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sat Oct 30 18:31:15 2010
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
|
||||
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
|
||||
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
|
||||
|
||||
INPUT FILE: project.ncd
|
||||
OUTPUT FILE: project_r_pad.txt
|
||||
PART TYPE: xc3s500e
|
||||
SPEED GRADE: -4
|
||||
PACKAGE: vq100
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|P1 | | |PROG_B | | | | | | | | | | | |
|
||||
|P2 |addr<4> |IBUF |IO_L01P_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P3 |addr<5> |IBUF |IO_L01N_3 |INPUT |LVCMOS25* |3 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P4 |sram_data<7>|IOB |IO_L02P_3 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P5 |sram_data<6>|IOB |IO_L02N_3/VREF_3 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P6 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P7 | | |GND | | | | | | | | | | | |
|
||||
|P8 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|
||||
|P9 |sram_data<5>|IOB |IO_L03P_3/LHCLK0 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P10 |sram_data<4>|IOB |IO_L03N_3/LHCLK1 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P11 |sram_data<3>|IOB |IO_L04P_3/LHCLK2 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P12 |sram_data<2>|IOB |IO_L04N_3/LHCLK3/IRDY2|BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P13 | |IBUF |IP |UNUSED | |3 | | | | | | | | |
|
||||
|P14 | | |GND | | | | | | | | | | | |
|
||||
|P15 |sram_data<1>|IOB |IO_L05P_3/LHCLK4/TRDY2|BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P16 |sram_data<0>|IOB |IO_L05N_3/LHCLK5 |BIDIR |LVCMOS25* |3 |12 |SLOW |NONE** |IFD | |LOCATED |YES |NONE |
|
||||
|P17 | |DIFFM |IO_L06P_3/LHCLK6 |UNUSED | |3 | | | | | | | | |
|
||||
|P18 | |DIFFS |IO_L06N_3/LHCLK7 |UNUSED | |3 | | | | | | | | |
|
||||
|P19 | | |GND | | | | | | | | | | | |
|
||||
|P20 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|
||||
|P21 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P22 | |DIFFM |IO_L07P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P23 | |DIFFS |IO_L07N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|P24 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|
||||
|P25 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|
||||
|P26 | |DIFFM |IO_L02P_2/DOUT/BUSY |UNUSED | |2 | | | | | | | | |
|
||||
|P27 | |DIFFS |IO_L02N_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|
||||
|P28 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P29 | | |GND | | | | | | | | | | | |
|
||||
|P30 |reset |IBUF |IP/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P31 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|
||||
|P32 | |DIFFM |IO_L03P_2/D7/GCLK12 |UNUSED | |2 | | | | | | | | |
|
||||
|P33 | |DIFFS |IO_L03N_2/D6/GCLK13 |UNUSED | |2 | | | | | | | | |
|
||||
|P34 | |IOB |IO/D5 |UNUSED | |2 | | | | | | | | |
|
||||
|P35 | |DIFFM |IO_L04P_2/D4/GCLK14 |UNUSED | |2 | | | | | | | | |
|
||||
|P36 | |DIFFS |IO_L04N_2/D3/GCLK15 |UNUSED | |2 | | | | | | | | |
|
||||
|P37 | | |GND | | | | | | | | | | | |
|
||||
|P38 |clk |IBUF |IP_L05P_2/RDWR_B/GCLK0|INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P39 | |DIFFSI |IP_L05N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
|
||||
|P40 | |DIFFM |IO_L06P_2/D2/GCLK2 |UNUSED | |2 | | | | | | | | |
|
||||
|P41 | |DIFFS |IO_L06N_2/D1/GCLK3 |UNUSED | |2 | | | | | | | | |
|
||||
|P42 | |IOB |IO/M1 |UNUSED | |2 | | | | | | | | |
|
||||
|P43 | |DIFFM |IO_L07P_2/M0 |UNUSED | |2 | | | | | | | | |
|
||||
|P44 | |DIFFS |IO_L07N_2/DIN/D0 |UNUSED | |2 | | | | | | | | |
|
||||
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|
||||
|P46 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P47 | |DIFFM |IO_L08P_2/VS2 |UNUSED | |2 | | | | | | | | |
|
||||
|P48 |hbridge<0> |IOB |IO_L08N_2/VS1 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P49 |hbridge<1> |IOB |IO_L09P_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P50 | |DIFFS |IO_L09N_2/CCLK |UNUSED | |2 | | | | | | | | |
|
||||
|P51 | | |DONE | | | | | | | | | | | |
|
||||
|P52 | | |GND | | | | | | | | | | | |
|
||||
|P53 |hbridge<3> |IOB |IO_L01P_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P54 |hbridge<2> |IOB |IO_L01N_1 |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P55 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|
||||
|P56 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P57 | |DIFFM |IO_L02P_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P58 | |DIFFS |IO_L02N_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P59 | | |GND | | | | | | | | | | | |
|
||||
|P60 | |DIFFM |IO_L03P_1/RHCLK0 |UNUSED | |1 | | | | | | | | |
|
||||
|P61 | |DIFFS |IO_L03N_1/RHCLK1 |UNUSED | |1 | | | | | | | | |
|
||||
|P62 | |DIFFM |IO_L04P_1/RHCLK2 |UNUSED | |1 | | | | | | | | |
|
||||
|P63 | |DIFFS |IO_L04N_1/RHCLK3/TRDY1|UNUSED | |1 | | | | | | | | |
|
||||
|P64 | | |GND | | | | | | | | | | | |
|
||||
|P65 | |DIFFM |IO_L05P_1/RHCLK4/IRDY1|UNUSED | |1 | | | | | | | | |
|
||||
|P66 | |DIFFS |IO_L05N_1/RHCLK5 |UNUSED | |1 | | | | | | | | |
|
||||
|P67 |quadA |IBUF |IO_L06P_1/RHCLK6 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P68 |quadB |IBUF |IO_L06N_1/RHCLK7 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P69 |ncs |IBUF |IP/VREF_1 |INPUT |LVCMOS25* |1 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P70 | |DIFFM |IO_L07P_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P71 | |DIFFS |IO_L07N_1 |UNUSED | |1 | | | | | | | | |
|
||||
|P72 | | |GND | | | | | | | | | | | |
|
||||
|P73 | | |VCCO_1 | | |1 | | | | |2.50 | | | |
|
||||
|P74 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P75 | | |TMS | | | | | | | | | | | |
|
||||
|P76 | | |TDO | | | | | | | | | | | |
|
||||
|P77 | | |TCK | | | | | | | | | | | |
|
||||
|P78 |addr<3> |IBUF |IO_L01P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P79 |addr<2> |IBUF |IO_L01N_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P80 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P81 | | |GND | | | | | | | | | | | |
|
||||
|P82 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|
||||
|P83 |addr<1> |IBUF |IO_L02P_0/GCLK4 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P84 |addr<0> |IBUF |IO_L02N_0/GCLK5 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P85 |addr<10> |IBUF |IO_L03P_0/GCLK6 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P86 |noe |IBUF |IO_L03N_0/GCLK7 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|P87 | | |GND | | | | | | | | | | | |
|
||||
|P88 |nwe |IBUF |IP_L04P_0/GCLK8 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P89 | |DIFFSI |IP_L04N_0/GCLK9 |UNUSED | |0 | | | | | | | | |
|
||||
|P90 |addr<12> |IBUF |IO_L05P_0/GCLK10 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P91 |addr<11> |IBUF |IO_L05N_0/GCLK11 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P92 |addr<9> |IBUF |IO |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P93 | | |GND | | | | | | | | | | | |
|
||||
|P94 |addr<8> |IBUF |IO_L06P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P95 |addr<7> |IBUF |IO_L06N_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P96 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P97 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|
||||
|P98 |addr<6> |IBUF |IO_L07P_0 |INPUT |LVCMOS25* |0 | | | |IFD | |LOCATED |YES |NONE |
|
||||
|P99 | |DIFFS |IO_L07N_0/HSWAP |UNUSED | |0 | | | | | | | | |
|
||||
|P100 | | |TDI | | | | | | | | | | | |
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
10
Examples/Beta1/logic/build/project_summary.xml
Normal file
10
Examples/Beta1/logic/build/project_summary.xml
Normal file
@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DesignSummary rev="2">
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DesignSummary>
|
||||
882
Examples/Beta1/logic/build/project_usage.xml
Normal file
882
Examples/Beta1/logic/build/project_usage.xml
Normal file
@ -0,0 +1,882 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DeviceUsageSummary rev="2">
|
||||
<DesignStatistics TimeStamp="Sat Oct 30 18:31:26 2010"><group name="NetStatistics">
|
||||
<item name="NumNets_Active" rev="2">
|
||||
<attrib name="value" value="280"/></item>
|
||||
<item name="NumNets_Gnd" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNets_Vcc" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_BRAMADDR" rev="2">
|
||||
<attrib name="value" value="33"/></item>
|
||||
<item name="NumNodesOfType_Active_BRAMDUMMY" rev="2">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="NumNodesOfType_Active_CLKPIN" rev="2">
|
||||
<attrib name="value" value="90"/></item>
|
||||
<item name="NumNodesOfType_Active_CNTRLPIN" rev="2">
|
||||
<attrib name="value" value="68"/></item>
|
||||
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
|
||||
<attrib name="value" value="634"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMY" rev="2">
|
||||
<attrib name="value" value="353"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMYBANK" rev="2">
|
||||
<attrib name="value" value="42"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMYESC" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
|
||||
<attrib name="value" value="51"/></item>
|
||||
<item name="NumNodesOfType_Active_HFULLHEX" rev="2">
|
||||
<attrib name="value" value="11"/></item>
|
||||
<item name="NumNodesOfType_Active_HLONG" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Active_HUNIHEX" rev="2">
|
||||
<attrib name="value" value="68"/></item>
|
||||
<item name="NumNodesOfType_Active_INPUT" rev="2">
|
||||
<attrib name="value" value="546"/></item>
|
||||
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
|
||||
<attrib name="value" value="29"/></item>
|
||||
<item name="NumNodesOfType_Active_OMUX" rev="2">
|
||||
<attrib name="value" value="263"/></item>
|
||||
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
|
||||
<attrib name="value" value="199"/></item>
|
||||
<item name="NumNodesOfType_Active_PREBXBY" rev="2">
|
||||
<attrib name="value" value="235"/></item>
|
||||
<item name="NumNodesOfType_Active_VFULLHEX" rev="2">
|
||||
<attrib name="value" value="37"/></item>
|
||||
<item name="NumNodesOfType_Active_VLONG" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NumNodesOfType_Active_VUNIHEX" rev="2">
|
||||
<attrib name="value" value="65"/></item>
|
||||
<item name="NumNodesOfType_Gnd_BRAMADDR" rev="2">
|
||||
<attrib name="value" value="11"/></item>
|
||||
<item name="NumNodesOfType_Gnd_BRAMDUMMY" rev="2">
|
||||
<attrib name="value" value="9"/></item>
|
||||
<item name="NumNodesOfType_Gnd_DOUBLE" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="NumNodesOfType_Gnd_DUMMYBANK" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NumNodesOfType_Gnd_INPUT" rev="2">
|
||||
<attrib name="value" value="24"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OMUX" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OUTPUT" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="NumNodesOfType_Gnd_PREBXBY" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Gnd_VFULLHEX" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Vcc_BRAMDUMMY" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Vcc_INPUT" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="NumNodesOfType_Vcc_PREBXBY" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NumNodesOfType_Vcc_VCCOUT" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
</group>
|
||||
<group name="SiteStatistics">
|
||||
<item name="IBUF-DIFFM" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="IBUF-DIFFMI" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="IBUF-DIFFS" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="IBUF-DIFFSI" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="IBUF-IOB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="IOB-DIFFM" rev="2">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<item name="IOB-DIFFS" rev="2">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<item name="SLICEL-SLICEM" rev="2">
|
||||
<attrib name="value" value="42"/></item>
|
||||
</group>
|
||||
<group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="1">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="AGG_IO" rev="1">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="AGG_SLICE" rev="1">
|
||||
<attrib name="value" value="112"/></item>
|
||||
<item name="NUM_4_INPUT_LUT" rev="1">
|
||||
<attrib name="value" value="130"/></item>
|
||||
<item name="NUM_BONDED_IBUF" rev="1">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="NUM_BONDED_IOB" rev="1">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="NUM_BUFGMUX" rev="1">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_CYMUX" rev="1">
|
||||
<attrib name="value" value="60"/></item>
|
||||
<item name="NUM_IOB_FF" rev="1">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="NUM_LUT_RT" rev="1">
|
||||
<attrib name="value" value="28"/></item>
|
||||
<item name="NUM_RAMB16" rev="1">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="NUM_SLICEL" rev="1">
|
||||
<attrib name="value" value="112"/></item>
|
||||
<item name="NUM_SLICE_FF" rev="1">
|
||||
<attrib name="value" value="118"/></item>
|
||||
<item name="NUM_XOR" rev="1">
|
||||
<attrib name="value" value="32"/></item>
|
||||
</group>
|
||||
</DesignStatistics>
|
||||
<DeviceUsage TimeStamp="Sat Oct 30 18:31:26 2010"><group name="SiteSummary">
|
||||
<item name="BUFGMUX" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="BUFGMUX_GCLKMUX" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="BUFGMUX_GCLK_BUFFER" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="IBUF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
|
||||
<item name="IBUF_IFD_DELAY" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
|
||||
<item name="IBUF_IFF1" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="17"/></item>
|
||||
<item name="IBUF_INBUF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
|
||||
<item name="IBUF_PAD" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
|
||||
<item name="IOB" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
|
||||
<item name="IOB_IFD_DELAY" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="8"/></item>
|
||||
<item name="IOB_IFF1" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="8"/></item>
|
||||
<item name="IOB_INBUF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="8"/></item>
|
||||
<item name="IOB_OUTBUF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
|
||||
<item name="IOB_PAD" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
|
||||
<item name="RAMB16" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
|
||||
<item name="RAMB16_RAMB16" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
|
||||
<item name="RAMB16_RAMB16A" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
|
||||
<item name="RAMB16_RAMB16B" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="SLICEL" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="112"/></item>
|
||||
<item name="SLICEL_C1VDD" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
|
||||
<item name="SLICEL_CYMUXF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="32"/></item>
|
||||
<item name="SLICEL_CYMUXG" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="28"/></item>
|
||||
<item name="SLICEL_F" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="70"/></item>
|
||||
<item name="SLICEL_F5MUX" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="10"/></item>
|
||||
<item name="SLICEL_FFX" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="59"/></item>
|
||||
<item name="SLICEL_FFY" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="59"/></item>
|
||||
<item name="SLICEL_G" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="60"/></item>
|
||||
<item name="SLICEL_GNDF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
|
||||
<item name="SLICEL_GNDG" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="12"/></item>
|
||||
<item name="SLICEL_XORF" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="16"/></item>
|
||||
<item name="SLICEL_XORG" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="16"/></item>
|
||||
</group>
|
||||
</DeviceUsage>
|
||||
<ReportConfigData TimeStamp="Sat Oct 30 18:31:26 2010"><group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="0" value="32"/><attrib name="0_INV" value="0"/></item>
|
||||
<item name="1" rev="2">
|
||||
<attrib name="1_INV" value="0"/><attrib name="1" value="32"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXG">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="0" value="28"/><attrib name="0_INV" value="0"/></item>
|
||||
</group>
|
||||
<group name="IBUF_PAD">
|
||||
<item name="IOATTRBOX" rev="2">
|
||||
<attrib name="LVCMOS25" value="20"/></item>
|
||||
</group>
|
||||
<group name="IBUF_INBUF">
|
||||
<item name="IFD_DELAY_VALUE" rev="2">
|
||||
<attrib name="DLY3" value="17"/></item>
|
||||
</group>
|
||||
<group name="SLICEL">
|
||||
<item name="BX" rev="2">
|
||||
<attrib name="BX_INV" value="1"/><attrib name="BX" value="56"/></item>
|
||||
<item name="BY" rev="2">
|
||||
<attrib name="BY" value="39"/><attrib name="BY_INV" value="0"/></item>
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="CE" value="22"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CIN" rev="2">
|
||||
<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="24"/></item>
|
||||
<item name="CLK" rev="2">
|
||||
<attrib name="CLK" value="44"/><attrib name="CLK_INV" value="17"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="SR" value="17"/><attrib name="SR_INV" value="21"/></item>
|
||||
</group>
|
||||
<group name="RAMB16">
|
||||
<item name="CLKA" rev="2">
|
||||
<attrib name="CLKA_INV" value="3"/><attrib name="CLKA" value="0"/></item>
|
||||
<item name="CLKB" rev="2">
|
||||
<attrib name="CLKB_INV" value="1"/><attrib name="CLKB" value="0"/></item>
|
||||
<item name="ENA" rev="2">
|
||||
<attrib name="ENA_INV" value="0"/><attrib name="ENA" value="3"/></item>
|
||||
<item name="ENB" rev="2">
|
||||
<attrib name="ENB_INV" value="0"/><attrib name="ENB" value="1"/></item>
|
||||
<item name="SSRA" rev="2">
|
||||
<attrib name="SSRA_INV" value="0"/><attrib name="SSRA" value="3"/></item>
|
||||
<item name="SSRB" rev="2">
|
||||
<attrib name="SSRB_INV" value="0"/><attrib name="SSRB" value="1"/></item>
|
||||
<item name="WEA" rev="2">
|
||||
<attrib name="WEA" value="3"/><attrib name="WEA_INV" value="0"/></item>
|
||||
<item name="WEB" rev="2">
|
||||
<attrib name="WEB" value="1"/><attrib name="WEB_INV" value="0"/></item>
|
||||
</group>
|
||||
<group name="IOB_OUTBUF">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="IN_INV" value="4"/><attrib name="IN" value="8"/></item>
|
||||
<item name="TRI" rev="2">
|
||||
<attrib name="TRI_INV" value="0"/><attrib name="TRI" value="8"/></item>
|
||||
</group>
|
||||
<group name="RAMB16_RAMB16A">
|
||||
<item name="CLKA" rev="2">
|
||||
<attrib name="CLKA_INV" value="3"/><attrib name="CLKA" value="0"/></item>
|
||||
<item name="ENA" rev="2">
|
||||
<attrib name="ENA_INV" value="0"/><attrib name="ENA" value="3"/></item>
|
||||
<item name="PORTA_ATTR" rev="2">
|
||||
<attrib name="2048X9" value="3"/></item>
|
||||
<item name="SSRA" rev="2">
|
||||
<attrib name="SSRA_INV" value="0"/><attrib name="SSRA" value="3"/></item>
|
||||
<item name="WEA" rev="2">
|
||||
<attrib name="WEA" value="3"/><attrib name="WEA_INV" value="0"/></item>
|
||||
<item name="WRITEMODEA" rev="2">
|
||||
<attrib name="WRITE_FIRST" value="3"/></item>
|
||||
</group>
|
||||
<group name="RAMB16_RAMB16B">
|
||||
<item name="CLKB" rev="2">
|
||||
<attrib name="CLKB_INV" value="1"/><attrib name="CLKB" value="0"/></item>
|
||||
<item name="ENB" rev="2">
|
||||
<attrib name="ENB_INV" value="0"/><attrib name="ENB" value="1"/></item>
|
||||
<item name="PORTB_ATTR" rev="2">
|
||||
<attrib name="2048X9" value="1"/></item>
|
||||
<item name="SSRB" rev="2">
|
||||
<attrib name="SSRB_INV" value="0"/><attrib name="SSRB" value="1"/></item>
|
||||
<item name="WEB" rev="2">
|
||||
<attrib name="WEB" value="1"/><attrib name="WEB_INV" value="0"/></item>
|
||||
<item name="WRITEMODEB" rev="2">
|
||||
<attrib name="WRITE_FIRST" value="1"/></item>
|
||||
</group>
|
||||
<group name="IOB_IFF1">
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="CK" value="0"/><attrib name="CK_INV" value="8"/></item>
|
||||
<item name="IFF1_INIT_ATTR" rev="2">
|
||||
<attrib name="INIT0" value="8"/></item>
|
||||
<item name="LATCH_OR_FF" rev="2">
|
||||
<attrib name="FF" value="8"/></item>
|
||||
</group>
|
||||
<group name="IBUF">
|
||||
<item name="ICLK1" rev="2">
|
||||
<attrib name="ICLK1_INV" value="15"/><attrib name="ICLK1" value="2"/></item>
|
||||
</group>
|
||||
<group name="IOB_INBUF">
|
||||
<item name="IFD_DELAY_VALUE" rev="2">
|
||||
<attrib name="DLY3" value="8"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFX">
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="CE" value="20"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="CK" value="43"/><attrib name="CK_INV" value="16"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="D" value="58"/><attrib name="D_INV" value="1"/></item>
|
||||
<item name="FFX_INIT_ATTR" rev="2">
|
||||
<attrib name="INIT0" value="59"/></item>
|
||||
<item name="FFX_SR_ATTR" rev="2">
|
||||
<attrib name="SRLOW" value="59"/></item>
|
||||
<item name="LATCH_OR_FF" rev="2">
|
||||
<attrib name="FF" value="59"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="SR" value="16"/><attrib name="SR_INV" value="21"/></item>
|
||||
<item name="SYNC_ATTR" rev="2">
|
||||
<attrib name="ASYNC" value="22"/><attrib name="SYNC" value="37"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORF">
|
||||
<item name="1" rev="2">
|
||||
<attrib name="1_INV" value="0"/><attrib name="1" value="16"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFY">
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="CE" value="20"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="CK" value="42"/><attrib name="CK_INV" value="17"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="D" value="59"/><attrib name="D_INV" value="0"/></item>
|
||||
<item name="FFY_INIT_ATTR" rev="2">
|
||||
<attrib name="INIT0" value="59"/></item>
|
||||
<item name="FFY_SR_ATTR" rev="2">
|
||||
<attrib name="SRLOW" value="59"/></item>
|
||||
<item name="LATCH_OR_FF" rev="2">
|
||||
<attrib name="FF" value="59"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="SR" value="17"/><attrib name="SR_INV" value="21"/></item>
|
||||
<item name="SYNC_ATTR" rev="2">
|
||||
<attrib name="ASYNC" value="21"/><attrib name="SYNC" value="38"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLKMUX">
|
||||
<item name="DISABLE_ATTR" rev="2">
|
||||
<attrib name="LOW" value="1"/></item>
|
||||
<item name="S" rev="2">
|
||||
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F5MUX">
|
||||
<item name="S0" rev="2">
|
||||
<attrib name="S0" value="10"/><attrib name="S0_INV" value="0"/></item>
|
||||
</group>
|
||||
<group name="IBUF_IFF1">
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="CK" value="2"/><attrib name="CK_INV" value="15"/></item>
|
||||
<item name="IFF1_INIT_ATTR" rev="2">
|
||||
<attrib name="INIT0" value="17"/></item>
|
||||
<item name="LATCH_OR_FF" rev="2">
|
||||
<attrib name="FF" value="17"/></item>
|
||||
</group>
|
||||
<group name="IOB_PAD">
|
||||
<item name="DRIVEATTRBOX" rev="2">
|
||||
<attrib name="12" value="12"/></item>
|
||||
<item name="IOATTRBOX" rev="2">
|
||||
<attrib name="LVCMOS25" value="12"/></item>
|
||||
<item name="SLEW" rev="2">
|
||||
<attrib name="SLOW" value="12"/></item>
|
||||
</group>
|
||||
<group name="IOB">
|
||||
<item name="ICLK1" rev="2">
|
||||
<attrib name="ICLK1_INV" value="8"/><attrib name="ICLK1" value="0"/></item>
|
||||
<item name="O1" rev="2">
|
||||
<attrib name="O1_INV" value="4"/><attrib name="O1" value="8"/></item>
|
||||
<item name="T1" rev="2">
|
||||
<attrib name="T1_INV" value="0"/><attrib name="T1" value="8"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX">
|
||||
<item name="S" rev="2">
|
||||
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
|
||||
</group>
|
||||
</ReportConfigData>
|
||||
<ReportPinData TimeStamp="Sat Oct 30 18:31:26 2010"><group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="1" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="S0" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXG">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="28"/></item>
|
||||
<item name="1" rev="2">
|
||||
<attrib name="value" value="28"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="28"/></item>
|
||||
<item name="S0" rev="2">
|
||||
<attrib name="value" value="28"/></item>
|
||||
</group>
|
||||
<group name="IBUF_PAD">
|
||||
<item name="PAD" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
</group>
|
||||
<group name="IBUF_INBUF">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
</group>
|
||||
<group name="IOB_IFD_DELAY">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLK_BUFFER">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL">
|
||||
<item name="BX" rev="2">
|
||||
<attrib name="value" value="57"/></item>
|
||||
<item name="BY" rev="2">
|
||||
<attrib name="value" value="39"/></item>
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="CIN" rev="2">
|
||||
<attrib name="value" value="24"/></item>
|
||||
<item name="CLK" rev="2">
|
||||
<attrib name="value" value="61"/></item>
|
||||
<item name="COUT" rev="2">
|
||||
<attrib name="value" value="28"/></item>
|
||||
<item name="F1" rev="2">
|
||||
<attrib name="value" value="68"/></item>
|
||||
<item name="F2" rev="2">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="F3" rev="2">
|
||||
<attrib name="value" value="33"/></item>
|
||||
<item name="F4" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="G1" rev="2">
|
||||
<attrib name="value" value="60"/></item>
|
||||
<item name="G2" rev="2">
|
||||
<attrib name="value" value="44"/></item>
|
||||
<item name="G3" rev="2">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="G4" rev="2">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="value" value="38"/></item>
|
||||
<item name="X" rev="2">
|
||||
<attrib name="value" value="34"/></item>
|
||||
<item name="XQ" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="Y" rev="2">
|
||||
<attrib name="value" value="14"/></item>
|
||||
<item name="YQ" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
</group>
|
||||
<group name="RAMB16">
|
||||
<item name="ADDRA10" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA11" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA12" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA13" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA3" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA4" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA5" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA6" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA7" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA8" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA9" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRB10" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB11" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB12" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB13" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB3" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB4" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB5" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB6" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB7" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB8" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB9" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="CLKA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="CLKB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIA0" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA1" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA2" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA3" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA4" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA5" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA6" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA7" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIB0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB1" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB2" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB3" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB4" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB5" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB6" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB7" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIPA0" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIPB0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DOA0" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA1" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA2" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA3" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA4" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA5" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA6" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA7" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ENA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ENB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="SSRA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="SSRB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="WEA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="WEB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="IOB_OUTBUF">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="TRI" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
</group>
|
||||
<group name="RAMB16_RAMB16A">
|
||||
<item name="ADDRA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA10" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA11" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA12" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA13" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA3" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA4" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA5" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA6" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA7" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA8" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRA9" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="CLKA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DIA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DIA0" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA1" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA2" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA3" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA4" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA5" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA6" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIA7" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DIPA0" rev="2">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="DOA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA0" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA1" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA2" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA3" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA4" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA5" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA6" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOA7" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ENA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="SSRA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="WEA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
</group>
|
||||
<group name="RAMB16_RAMB16B">
|
||||
<item name="ADDRB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB10" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB11" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB12" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB13" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB3" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB4" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB5" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB6" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB7" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB8" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ADDRB9" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="CLKB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB1" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB2" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB3" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB4" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB5" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB6" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIB7" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIPB0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DOB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="ENB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="SSRB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="WEB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="IOB_IFF1">
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="Q" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
</group>
|
||||
<group name="IBUF">
|
||||
<item name="I" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="ICLK1" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="IQ1" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="PAD" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
</group>
|
||||
<group name="IOB_INBUF">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFX">
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="Q" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="value" value="37"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
<item name="1" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
<item name="O" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFY">
|
||||
<item name="CE" rev="2">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="Q" rev="2">
|
||||
<attrib name="value" value="59"/></item>
|
||||
<item name="SR" rev="2">
|
||||
<attrib name="value" value="38"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORG">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
<item name="1" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
<item name="O" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLKMUX">
|
||||
<item name="I0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="S" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F5MUX">
|
||||
<item name="F" rev="2">
|
||||
<attrib name="value" value="10"/></item>
|
||||
<item name="G" rev="2">
|
||||
<attrib name="value" value="10"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="10"/></item>
|
||||
<item name="S0" rev="2">
|
||||
<attrib name="value" value="10"/></item>
|
||||
</group>
|
||||
<group name="IBUF_IFF1">
|
||||
<item name="CK" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="Q" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
</group>
|
||||
<group name="IOB_PAD">
|
||||
<item name="PAD" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
</group>
|
||||
<group name="IOB">
|
||||
<item name="ICLK1" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="IQ1" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="O1" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="PAD" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="T1" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_C1VDD">
|
||||
<item name="1" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX">
|
||||
<item name="I0" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="O" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="S" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F">
|
||||
<item name="A1" rev="2">
|
||||
<attrib name="value" value="68"/></item>
|
||||
<item name="A2" rev="2">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="A3" rev="2">
|
||||
<attrib name="value" value="33"/></item>
|
||||
<item name="A4" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="70"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_G">
|
||||
<item name="A1" rev="2">
|
||||
<attrib name="value" value="60"/></item>
|
||||
<item name="A2" rev="2">
|
||||
<attrib name="value" value="44"/></item>
|
||||
<item name="A3" rev="2">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="A4" rev="2">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="D" rev="2">
|
||||
<attrib name="value" value="60"/></item>
|
||||
</group>
|
||||
<group name="IBUF_IFD_DELAY">
|
||||
<item name="IN" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
<item name="OUT" rev="2">
|
||||
<attrib name="value" value="17"/></item>
|
||||
</group>
|
||||
<group name="RAMB16_RAMB16">
|
||||
<item name="ADDRA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="ADDRB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DIA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DIB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="DOA" rev="2">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="DOB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_GNDF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_GNDG">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
</group>
|
||||
</ReportPinData>
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DeviceUsageSummary>
|
||||
827
Examples/Beta1/logic/build/usage_statistics_webtalk.html
Normal file
827
Examples/Beta1/logic/build/usage_statistics_webtalk.html
Normal file
@ -0,0 +1,827 @@
|
||||
<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR> <BR><HR> <BR>
|
||||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN='4'><B>Software Version and Target Device</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD>
|
||||
<TD><xtag-property name="ProductVersion">ISE:12.2</xtag-property><xtag-property name="ProductConfiguration"> (WebPack)</xtag-property><xtag-property name="BuildVersion"> - M.63c</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Family:</B></TD>
|
||||
<TD><xtag-property name="TargetFamily">Spartan3E</xtag-property></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
|
||||
<TD><xtag-property name="OSPlatform">LIN64</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD><xtag-property name="TargetDevice">xc3s500e</xtag-property></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
|
||||
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">44f8cd23f23f4c7d956e087dfdda32fd</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
|
||||
<TD><xtag-property name="TargetPackage">vq100</xtag-property></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Registration ID</B></TD>
|
||||
<TD><xtag-property name="RegistrationID">0_0_674</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Speed:</B></TD>
|
||||
<TD><xtag-property name="TargetSpeed">-4</xtag-property></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
|
||||
<TD><xtag-property name="Date Generated">2010-10-30T18:31:27</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
|
||||
<TD><xtag-property name="ToolFlow">CommandLine</xtag-property></TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="UserEnvironment">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
|
||||
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
|
||||
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>unknown</xtag-env-param-value></xtag-property></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
|
||||
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz</xtag-env-param-value></xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
|
||||
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>2201.000 MHz</xtag-env-param-value></xtag-property></TD>
|
||||
</TR>
|
||||
</xtag-section></TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Device Usage Statistics</B></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'><TD><B>Macro Statistics</B></TD><TD><B>Miscellaneous Statistics</B></TD><TD><B>Net Statistics</B></TD><TD><B>Site Usage</B></TD></TR><TR VALIGN=TOP>
|
||||
<TD> </TD>
|
||||
<xtag-section name="DesignStatistics">
|
||||
<TD>
|
||||
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>AGG_BONDED_IO=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>AGG_IO=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>AGG_SLICE=112</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_4_INPUT_LUT=130</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_BONDED_IBUF=20</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_BONDED_IOB=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_BUFGMUX=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_CYMUX=60</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_IOB_FF=25</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_LUT_RT=28</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_RAMB16=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_SLICEL=112</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_SLICE_FF=118</xtag-item1></LI>
|
||||
<LI><xtag-item1>NUM_XOR=32</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
<TD>
|
||||
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>NumNets_Active=280</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_BRAMADDR=33</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_BRAMDUMMY=52</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=90</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=68</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=634</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=353</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=42</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=51</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=11</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HLONG=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=68</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_INPUT=546</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=29</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_OMUX=263</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=199</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=235</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=37</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VLONG=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=65</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMADDR=11</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMDUMMY=9</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=24</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_VFULLHEX=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_BRAMDUMMY=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_INPUT=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_PREBXBY=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_VCCOUT=7</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SiteStatistics">SiteStatistics</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IBUF-DIFFM=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-DIFFMI=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-DIFFS=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-DIFFSI=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-IOB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFM=6</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFS=6</xtag-item1></LI>
|
||||
<LI><xtag-item1>SLICEL-SLICEM=42</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
</xtag-section>
|
||||
<xtag-section name="DeviceUsage">
|
||||
<TD>
|
||||
<xtag-group><xtag-group-name name="SiteSummary">SiteSummary</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item2>BUFGMUX=1</xtag-item2></LI>
|
||||
<LI><xtag-item2>BUFGMUX_GCLKMUX=1</xtag-item2></LI>
|
||||
<LI><xtag-item2>BUFGMUX_GCLK_BUFFER=1</xtag-item2></LI>
|
||||
<LI><xtag-item2>IBUF=20</xtag-item2></LI>
|
||||
<LI><xtag-item2>IBUF_IFD_DELAY=17</xtag-item2></LI>
|
||||
<LI><xtag-item2>IBUF_IFF1=17</xtag-item2></LI>
|
||||
<LI><xtag-item2>IBUF_INBUF=20</xtag-item2></LI>
|
||||
<LI><xtag-item2>IBUF_PAD=20</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB=12</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB_IFD_DELAY=8</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB_IFF1=8</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB_INBUF=8</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB_OUTBUF=12</xtag-item2></LI>
|
||||
<LI><xtag-item2>IOB_PAD=12</xtag-item2></LI>
|
||||
<LI><xtag-item2>RAMB16=3</xtag-item2></LI>
|
||||
<LI><xtag-item2>RAMB16_RAMB16=3</xtag-item2></LI>
|
||||
<LI><xtag-item2>RAMB16_RAMB16A=3</xtag-item2></LI>
|
||||
<LI><xtag-item2>RAMB16_RAMB16B=1</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL=112</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_C1VDD=4</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_CYMUXF=32</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_CYMUXG=28</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_F=70</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_F5MUX=10</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_FFX=59</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_FFY=59</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_G=60</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_GNDF=12</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_GNDG=12</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_XORF=16</xtag-item2></LI>
|
||||
<LI><xtag-item2>SLICEL_XORG=16</xtag-item2></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
</xtag-section>
|
||||
</TR></TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Configuration Data</B></TD></TR><TR VALIGN=TOP>
|
||||
<xtag-section name="ReportConfigData">
|
||||
<TD>
|
||||
<xtag-group><xtag-group-name name="BUFGMUX">BUFGMUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>S=[S_INV:1] [S:0]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>DISABLE_ATTR=[LOW:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>S=[S_INV:1] [S:0]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF">IBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>ICLK1=[ICLK1_INV:15] [ICLK1:2]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_IFF1">IBUF_IFF1</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CK=[CK:2] [CK_INV:15]</xtag-item3></LI>
|
||||
<LI><xtag-item3>IFF1_INIT_ATTR=[INIT0:17]</xtag-item3></LI>
|
||||
<LI><xtag-item3>LATCH_OR_FF=[FF:17]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_INBUF">IBUF_INBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>IFD_DELAY_VALUE=[DLY3:17]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:20]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>ICLK1=[ICLK1_INV:8] [ICLK1:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>O1=[O1_INV:4] [O1:8]</xtag-item3></LI>
|
||||
<LI><xtag-item3>T1=[T1_INV:0] [T1:8]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_IFF1">IOB_IFF1</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CK=[CK:0] [CK_INV:8]</xtag-item3></LI>
|
||||
<LI><xtag-item3>IFF1_INIT_ATTR=[INIT0:8]</xtag-item3></LI>
|
||||
<LI><xtag-item3>LATCH_OR_FF=[FF:8]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>IFD_DELAY_VALUE=[DLY3:8]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>IN=[IN_INV:4] [IN:8]</xtag-item3></LI>
|
||||
<LI><xtag-item3>TRI=[TRI_INV:0] [TRI:8]</xtag-item3></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>DRIVEATTRBOX=[12:12]</xtag-item3></LI>
|
||||
<LI><xtag-item3>IOATTRBOX=[LVCMOS25:12]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SLEW=[SLOW:12]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16">RAMB16</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CLKA=[CLKA_INV:3] [CLKA:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CLKB=[CLKB_INV:1] [CLKB:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:3]</xtag-item3></LI>
|
||||
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:3]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WEA=[WEA:3] [WEA_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WEB=[WEB:1] [WEB_INV:0]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16_RAMB16A">RAMB16_RAMB16A</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CLKA=[CLKA_INV:3] [CLKA:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>ENA=[ENA_INV:0] [ENA:3]</xtag-item3></LI>
|
||||
<LI><xtag-item3>PORTA_ATTR=[2048X9:3]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SSRA=[SSRA_INV:0] [SSRA:3]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WEA=[WEA:3] [WEA_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WRITEMODEA=[WRITE_FIRST:3]</xtag-item3></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16_RAMB16B">RAMB16_RAMB16B</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CLKB=[CLKB_INV:1] [CLKB:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>ENB=[ENB_INV:0] [ENB:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>PORTB_ATTR=[2048X9:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SSRB=[SSRB_INV:0] [SSRB:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WEB=[WEB:1] [WEB_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>WRITEMODEB=[WRITE_FIRST:1]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>BX=[BX_INV:1] [BX:56]</xtag-item3></LI>
|
||||
<LI><xtag-item3>BY=[BY:39] [BY_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CE=[CE:22] [CE_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CIN=[CIN_INV:0] [CIN:24]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CLK=[CLK:44] [CLK_INV:17]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SR=[SR:17] [SR_INV:21]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>0=[0:32] [0_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>1=[1_INV:0] [1:32]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>0=[0:28] [0_INV:0]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>S0=[S0:10] [S0_INV:0]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CE=[CE:20] [CE_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CK=[CK:43] [CK_INV:16]</xtag-item3></LI>
|
||||
<LI><xtag-item3>D=[D:58] [D_INV:1]</xtag-item3></LI>
|
||||
<LI><xtag-item3>FFX_INIT_ATTR=[INIT0:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>FFX_SR_ATTR=[SRLOW:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>LATCH_OR_FF=[FF:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SR=[SR:16] [SR_INV:21]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SYNC_ATTR=[ASYNC:22] [SYNC:37]</xtag-item3></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>CE=[CE:20] [CE_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>CK=[CK:42] [CK_INV:17]</xtag-item3></LI>
|
||||
<LI><xtag-item3>D=[D:59] [D_INV:0]</xtag-item3></LI>
|
||||
<LI><xtag-item3>FFY_INIT_ATTR=[INIT0:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>FFY_SR_ATTR=[SRLOW:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>LATCH_OR_FF=[FF:59]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SR=[SR:17] [SR_INV:21]</xtag-item3></LI>
|
||||
<LI><xtag-item3>SYNC_ATTR=[ASYNC:21] [SYNC:38]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item3>1=[1_INV:0] [1:16]</xtag-item3></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
</xtag-section>
|
||||
</TR></TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Pin Data</B></TD></TR><TR VALIGN=TOP>
|
||||
<xtag-section name="ReportConfigData">
|
||||
<TD>
|
||||
<xtag-group><xtag-group-name name="BUFGMUX">BUFGMUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>I0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>O=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>S=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="BUFGMUX_GCLKMUX">BUFGMUX_GCLKMUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>I0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>S=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="BUFGMUX_GCLK_BUFFER">BUFGMUX_GCLK_BUFFER</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF">IBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>I=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>ICLK1=17</xtag-item1></LI>
|
||||
<LI><xtag-item1>IQ1=17</xtag-item1></LI>
|
||||
<LI><xtag-item1>PAD=20</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_IFD_DELAY">IBUF_IFD_DELAY</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=17</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=17</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_IFF1">IBUF_IFF1</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>CK=17</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=17</xtag-item1></LI>
|
||||
<LI><xtag-item1>Q=17</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_INBUF">IBUF_INBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=20</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=20</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IBUF_PAD">IBUF_PAD</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>PAD=20</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB">IOB</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>ICLK1=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>IQ1=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>O1=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>PAD=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>T1=8</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_IFD_DELAY">IOB_IFD_DELAY</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=8</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_IFF1">IOB_IFF1</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>CK=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>Q=8</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_INBUF">IOB_INBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=8</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>IN=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>TRI=8</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="IOB_PAD">IOB_PAD</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>PAD=12</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16">RAMB16</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>ADDRA10=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA11=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA12=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA13=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA3=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA4=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA5=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA6=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA7=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA8=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA9=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB10=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB11=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB12=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB13=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB3=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB4=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB5=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB6=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB7=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB8=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB9=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>CLKA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>CLKB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA0=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA1=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA2=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA3=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA4=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA5=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA6=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA7=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB1=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB2=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB3=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB4=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB5=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB6=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB7=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIPA0=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIPB0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA0=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA1=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA2=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA3=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA4=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA5=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA6=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA7=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ENA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ENB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>SSRA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>SSRB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>WEA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>WEB=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16_RAMB16">RAMB16_RAMB16</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>ADDRA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOB=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16_RAMB16A">RAMB16_RAMB16A</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>ADDRA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA10=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA11=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA12=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA13=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA3=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA4=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA5=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA6=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA7=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA8=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRA9=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>CLKA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA0=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA1=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA2=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA3=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA4=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA5=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA6=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIA7=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIPA0=2</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA0=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA1=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA2=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA3=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA4=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA5=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA6=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOA7=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>ENA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>SSRA=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>WEA=3</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="RAMB16_RAMB16B">RAMB16_RAMB16B</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>ADDRB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB10=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB11=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB12=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB13=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB3=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB4=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB5=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB6=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB7=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB8=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ADDRB9=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>CLKB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB1=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB2=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB3=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB4=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB5=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB6=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIB7=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DIPB0=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>DOB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>ENB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>SSRB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>WEB=1</xtag-item1></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>BX=57</xtag-item1></LI>
|
||||
<LI><xtag-item1>BY=39</xtag-item1></LI>
|
||||
<LI><xtag-item1>CE=22</xtag-item1></LI>
|
||||
<LI><xtag-item1>CIN=24</xtag-item1></LI>
|
||||
<LI><xtag-item1>CLK=61</xtag-item1></LI>
|
||||
<LI><xtag-item1>COUT=28</xtag-item1></LI>
|
||||
<LI><xtag-item1>F1=68</xtag-item1></LI>
|
||||
<LI><xtag-item1>F2=52</xtag-item1></LI>
|
||||
<LI><xtag-item1>F3=33</xtag-item1></LI>
|
||||
<LI><xtag-item1>F4=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>G1=60</xtag-item1></LI>
|
||||
<LI><xtag-item1>G2=44</xtag-item1></LI>
|
||||
<LI><xtag-item1>G3=25</xtag-item1></LI>
|
||||
<LI><xtag-item1>G4=23</xtag-item1></LI>
|
||||
<LI><xtag-item1>SR=38</xtag-item1></LI>
|
||||
<LI><xtag-item1>X=34</xtag-item1></LI>
|
||||
<LI><xtag-item1>XQ=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>Y=14</xtag-item1></LI>
|
||||
<LI><xtag-item1>YQ=59</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_C1VDD">SLICEL_C1VDD</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>1=4</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_CYMUXF">SLICEL_CYMUXF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>1=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>S0=32</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_CYMUXG">SLICEL_CYMUXG</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=28</xtag-item1></LI>
|
||||
<LI><xtag-item1>1=28</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=28</xtag-item1></LI>
|
||||
<LI><xtag-item1>S0=28</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_F">SLICEL_F</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>A1=68</xtag-item1></LI>
|
||||
<LI><xtag-item1>A2=52</xtag-item1></LI>
|
||||
<LI><xtag-item1>A3=33</xtag-item1></LI>
|
||||
<LI><xtag-item1>A4=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=70</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_F5MUX">SLICEL_F5MUX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>F=10</xtag-item1></LI>
|
||||
<LI><xtag-item1>G=10</xtag-item1></LI>
|
||||
<LI><xtag-item1>OUT=10</xtag-item1></LI>
|
||||
<LI><xtag-item1>S0=10</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_FFX">SLICEL_FFX</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>CE=20</xtag-item1></LI>
|
||||
<LI><xtag-item1>CK=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>Q=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>SR=37</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_FFY">SLICEL_FFY</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>CE=20</xtag-item1></LI>
|
||||
<LI><xtag-item1>CK=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>Q=59</xtag-item1></LI>
|
||||
<LI><xtag-item1>SR=38</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_G">SLICEL_G</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>A1=60</xtag-item1></LI>
|
||||
<LI><xtag-item1>A2=44</xtag-item1></LI>
|
||||
<LI><xtag-item1>A3=25</xtag-item1></LI>
|
||||
<LI><xtag-item1>A4=23</xtag-item1></LI>
|
||||
<LI><xtag-item1>D=60</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_GNDF">SLICEL_GNDF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=12</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_GNDG">SLICEL_GNDG</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=12</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_XORF">SLICEL_XORF</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=16</xtag-item1></LI>
|
||||
<LI><xtag-item1>1=16</xtag-item1></LI>
|
||||
<LI><xtag-item1>O=16</xtag-item1></LI>
|
||||
</UL>
|
||||
</TD>
|
||||
<TD>
|
||||
</xtag-group>
|
||||
<xtag-group><xtag-group-name name="SLICEL_XORG">SLICEL_XORG</xtag-group-name>
|
||||
<UL>
|
||||
<LI><xtag-item1>0=16</xtag-item1></LI>
|
||||
<LI><xtag-item1>1=16</xtag-item1></LI>
|
||||
<LI><xtag-item1>O=16</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
</xtag-section>
|
||||
</TR></TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
|
||||
<tr>
|
||||
<td><xtag-program-name>bitgen</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>82</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>82</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>map</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>98</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>96</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>102</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>102</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>par</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>95</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>95</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>trce</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>95</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>95</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>xst</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>200</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>197</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
<td><xtag-total-exception>0</xtag-total-exception></td>
|
||||
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
|
||||
</tr>
|
||||
</xtag-section></TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="UnisimStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>Unisim Statistics</B></TD></TR>
|
||||
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_PRE_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_BUFGP</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD</xtag-preunisim-param-name>=<xtag-preunisim-param-value>38</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDE</xtag-preunisim-param-name>=<xtag-preunisim-param-value>7</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDR</xtag-preunisim-param-name>=<xtag-preunisim-param-value>42</xtag-preunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FDRE_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>33</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_FD_1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>23</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_GND</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>19</xtag-preunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_INV</xtag-preunisim-param-name>=<xtag-preunisim-param-value>11</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_IOBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>8</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT1</xtag-preunisim-param-name>=<xtag-preunisim-param-value>28</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT2</xtag-preunisim-param-name>=<xtag-preunisim-param-value>38</xtag-preunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT3</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT4</xtag-preunisim-param-name>=<xtag-preunisim-param-value>55</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>60</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF5</xtag-preunisim-param-name>=<xtag-preunisim-param-value>10</xtag-preunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>4</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAMB16_S9</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAMB16_S9_S9</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_VCC</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_XORCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>32</xtag-preunisim-param-value></TD>
|
||||
<TR ALIGN=CENTER><TD COLSPAN=4><B><xtag-unisim-type-name>NGDBUILD_POST_UNISIM_SUMMARY</xtag-unisim-type-name></B></TD></TR><TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_BUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD</xtag-postunisim-param-name>=<xtag-postunisim-param-value>38</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDE</xtag-postunisim-param-name>=<xtag-postunisim-param-value>7</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDR</xtag-postunisim-param-name>=<xtag-postunisim-param-value>42</xtag-postunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FDRE_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>33</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_FD_1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>23</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_GND</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>27</xtag-postunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_IBUFG</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_INV</xtag-postunisim-param-name>=<xtag-postunisim-param-value>11</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT1</xtag-postunisim-param-name>=<xtag-postunisim-param-value>28</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT2</xtag-postunisim-param-name>=<xtag-postunisim-param-value>38</xtag-postunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT3</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_LUT4</xtag-postunisim-param-name>=<xtag-postunisim-param-value>55</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>60</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF5</xtag-postunisim-param-name>=<xtag-postunisim-param-value>10</xtag-postunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>4</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>8</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAMB16_S9</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAMB16_S9_S9</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_VCC</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
|
||||
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_XORCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>32</xtag-postunisim-param-value></TD>
|
||||
</xtag-section></TABLE>
|
||||
</BODY></HTML>
|
||||
16
Examples/Beta1/logic/build/webtalk.log
Normal file
16
Examples/Beta1/logic/build/webtalk.log
Normal file
@ -0,0 +1,16 @@
|
||||
Release 12.2 - WebTalk (M.63c)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Project Information
|
||||
--------------------
|
||||
ProjectID=44f8cd23f23f4c7d956e087dfdda32fd
|
||||
ProjectIteration=2
|
||||
|
||||
WebTalk Summary
|
||||
----------------
|
||||
INFO:WebTalk:2 - WebTalk is enabled.
|
||||
|
||||
INFO:WebTalk:8 - WebTalk Install setting is ON.
|
||||
INFO:WebTalk:6 - WebTalk User setting is ON.
|
||||
|
||||
INFO:WebTalk:5 - /home/erwin/sie-ceimtun/Examples/Beta1/logic/build/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at /home/erwin/Xilinxs/12.2/ISE_DS/ISE/data/reports/webtalk_introduction.html
|
||||
BIN
Examples/Beta1/logic/build/xlnx_auto_0_xdb/cst.xbcd
Normal file
BIN
Examples/Beta1/logic/build/xlnx_auto_0_xdb/cst.xbcd
Normal file
Binary file not shown.
4
Examples/Beta1/logic/build/xst/work/hdllib.ref
Normal file
4
Examples/Beta1/logic/build/xst/work/hdllib.ref
Normal file
@ -0,0 +1,4 @@
|
||||
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288481438
|
||||
MO beta NULL ../beta.v vlg5C/beta.bin 1288481438
|
||||
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288481438
|
||||
MO enco NULL ../enco.v vlg6D/enco.bin 1288481438
|
||||
BIN
Examples/Beta1/logic/build/xst/work/vlg50/_p_w_m.bin
Normal file
BIN
Examples/Beta1/logic/build/xst/work/vlg50/_p_w_m.bin
Normal file
Binary file not shown.
BIN
Examples/Beta1/logic/build/xst/work/vlg5C/beta.bin
Normal file
BIN
Examples/Beta1/logic/build/xst/work/vlg5C/beta.bin
Normal file
Binary file not shown.
BIN
Examples/Beta1/logic/build/xst/work/vlg69/_puente_h.bin
Normal file
BIN
Examples/Beta1/logic/build/xst/work/vlg69/_puente_h.bin
Normal file
Binary file not shown.
BIN
Examples/Beta1/logic/build/xst/work/vlg6D/enco.bin
Normal file
BIN
Examples/Beta1/logic/build/xst/work/vlg6D/enco.bin
Normal file
Binary file not shown.
79
Examples/Beta1/logic/enco.v
Normal file
79
Examples/Beta1/logic/enco.v
Normal file
@ -0,0 +1,79 @@
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module enco(clk, enable,quadA, quadB, out,buffer_addr);
|
||||
input clk, quadA, quadB;
|
||||
input enable;
|
||||
input [10:0]buffer_addr;
|
||||
output [7:0] out;
|
||||
|
||||
wire [7:0] vel_dir;
|
||||
//Registros para implementar retardos, con la idea de syncronizar las seales
|
||||
reg [2:0] quadA_delayed, quadB_delayed=0;
|
||||
always @(posedge clk) quadA_delayed <= {quadA_delayed[1:0], quadA};
|
||||
always @(posedge clk) quadB_delayed <= {quadB_delayed[1:0], quadB};
|
||||
|
||||
//Valores internos para habilitar el conteo, y determinar la direccin del mismo
|
||||
wire count_enable = quadA_delayed[1] ^ quadA_delayed[2] ^ quadB_delayed[1] ^ quadB_delayed[2];
|
||||
wire count_direction = quadA_delayed[1] ^ quadB_delayed[2];
|
||||
|
||||
//Registro para almacenar el contador
|
||||
reg [6:0] count=0; //Pendiente cambiar este, no sabemos que dato saldr al final
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if(count_enable)
|
||||
begin
|
||||
if(count_direction) count<=count+1; else count<=count-1;
|
||||
end
|
||||
end
|
||||
|
||||
//Falta definir como vamos a comunicar esta info, es ms facil como posicin
|
||||
|
||||
/*reg [1:0] pos_reg0=0; //Registro temporal 1
|
||||
reg [1:0] pos_reg1=0; //Registro temporal
|
||||
reg dir=0; //Direccin, 1=adelante? 0=atras?
|
||||
always @(posedge clk)
|
||||
begin
|
||||
pos_reg0<={quadB, quadA};
|
||||
pos_reg1<=pos_reg0;
|
||||
|
||||
if(pos_reg1==pos_reg0) dir<=dir;
|
||||
else if(pos_reg0==1)
|
||||
begin
|
||||
if(pos_reg1<pos_reg0) dir<=0; else dir<=1;
|
||||
end
|
||||
else if(pos_reg1==1)
|
||||
begin
|
||||
if(pos_reg1<pos_reg0) dir<=0; else dir<=1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(pos_reg1<pos_reg0) dir<=1; else dir<=0;
|
||||
end
|
||||
|
||||
|
||||
end*/
|
||||
//Fue cambiado!
|
||||
assign vel_dir={1'b0,count[6:0]};
|
||||
|
||||
// Dual-port RAM instatiation
|
||||
RAMB16_S9_S9 ba0(
|
||||
.DOA(out), // Port A 8-bit Data Output
|
||||
.DOB(), // Port B 8-bit Data Output
|
||||
.DOPA(), // Port A 1-bit Parity Output
|
||||
.DOPB(), // Port B 1-bit Parity Output
|
||||
.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
|
||||
.ADDRB(1'b0), // Port B 11-bit Address Input
|
||||
.CLKA(~clk), // Port A Clock
|
||||
.CLKB(~clk), // Port B Clock
|
||||
.DIA(), // Port A 8-bit Data Input
|
||||
.DIB(vel_dir), // Port B 8-bit Data Input
|
||||
.DIPA(1'b0), // Port A 1-bit parity Input
|
||||
.DIPB(1'b0), // Port-B 1-bit parity Input
|
||||
.ENA(1'b1), // Port A RAM Enable Input
|
||||
.ENB(1'b1), // Port B RAM Enable Input
|
||||
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
|
||||
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
|
||||
.WEA(1'b0), // Port A Write Enable Input
|
||||
.WEB(enable) ); // Port B Write Enable Input
|
||||
|
||||
endmodule
|
||||
76
Examples/Beta1/src/ADCw.cpp
Normal file
76
Examples/Beta1/src/ADCw.cpp
Normal file
@ -0,0 +1,76 @@
|
||||
#include "ADCw.h"
|
||||
|
||||
ADCw::ADCw()
|
||||
{
|
||||
BUFFER_OFFSET = 8; //Ignore first 16 samples
|
||||
ADC_SPI_CLKDIV=ADC_SPI_CLKDIV_MAX; //Set clock to minimum speed
|
||||
BUFFER_LEN=16;
|
||||
MUX_CHANNELS =0;
|
||||
|
||||
ADCBuffer = jz_adc_init();
|
||||
|
||||
//Clean FPGA RAM memory
|
||||
for (int i = 0; i < 512; i++) //RAMB16_s9_s9 has 2048 bytes 8-bit
|
||||
{
|
||||
ADCBuffer[i] = 0x00000000; //Clean 4 register by cicle
|
||||
}
|
||||
|
||||
adcConfig(ADC_CMD_SET_SPI_CLKDIV);
|
||||
adcConfig(ADC_CMD_SET_FAST_CONV);
|
||||
printf("\nADC in Fast Convertion Mode (10us) and Fs=9.8KHz (Min)\n");
|
||||
}
|
||||
|
||||
void ADCw::testADC()
|
||||
{
|
||||
/******************************* TEST 1 ***********************************/
|
||||
printf("\nINIT TEST1: Autoselft {(Vref+) - (Vref-)}/2 -> Return 0x0200 \n");
|
||||
adcConfig(ADC_CMD_SET_AUTOSELFT_1);
|
||||
adcConfig(ADC_CMD_READ_AUTOSELFT_1);
|
||||
for(int i=BUFFER_OFFSET; i< BUFFER_LEN/2+BUFFER_OFFSET; i++)
|
||||
printf("[%08X]", ADCBuffer[i]);
|
||||
fflush (stdout);
|
||||
|
||||
/******************************* TEST 2 ***********************************/
|
||||
printf("\n\nINIT TEST2: Autoselft (Vref-) -> Return 0x0000 \n");
|
||||
adcConfig(ADC_CMD_SET_AUTOSELFT_2);
|
||||
adcConfig(ADC_CMD_READ_AUTOSELFT_2);
|
||||
for(int i=BUFFER_OFFSET; i< BUFFER_LEN/2+BUFFER_OFFSET; i++)
|
||||
printf("[%08X]", ADCBuffer[i]);
|
||||
fflush (stdout);
|
||||
|
||||
/******************************* TEST 3 ***********************************/
|
||||
printf("\n\nINIT TEST3: Autoselft (Vref+) -> Return 0x03FF \n");
|
||||
adcConfig(ADC_CMD_SET_AUTOSELFT_3);
|
||||
adcConfig(ADC_CMD_READ_AUTOSELFT_3);
|
||||
for(int i=BUFFER_OFFSET; i< BUFFER_LEN/2+BUFFER_OFFSET; i++)
|
||||
printf("[%08X]", ADCBuffer[i]);
|
||||
fflush (stdout);
|
||||
|
||||
printf("\n\nTESTS complete\n");
|
||||
}
|
||||
|
||||
void ADCw::powerDownADC()
|
||||
{
|
||||
adcConfig(ADC_CMD_SET_POWER_DOWN);
|
||||
printf("\nADC in Power Down Mode \n");
|
||||
}
|
||||
|
||||
JZ_REG* ADCw::takeSamplesADC(int CHANNEL)
|
||||
{
|
||||
adcConfig(ADC_CMD_SET_CHANNEL0+CHANNEL);
|
||||
adcConfig(ADC_CMD_READ_CHANNEL0+CHANNEL);
|
||||
return (JZ_REG*)(ADCBuffer+BUFFER_OFFSET);
|
||||
}
|
||||
|
||||
void ADCw::adcConfig(uchar CMD)
|
||||
{
|
||||
ADCBuffer[0] = (((MUX_CHANNELS<<6) + CMD)<<24) + \
|
||||
((BUFFER_LEN+BUFFER_OFFSET*2) << 8) + \
|
||||
(ADC_SPI_CLKDIV);
|
||||
while(adcCheckBufferFull()) usleep (10);
|
||||
}
|
||||
|
||||
int ADCw::adcCheckBufferFull()
|
||||
{
|
||||
return ADCBuffer[0]&0x20000000;
|
||||
}
|
||||
31
Examples/Beta1/src/ADCw.h
Normal file
31
Examples/Beta1/src/ADCw.h
Normal file
@ -0,0 +1,31 @@
|
||||
#ifndef ADCW_H
|
||||
#define ADCW_H
|
||||
|
||||
#include "jz_adc_peripheral.c"
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
class ADCw
|
||||
{
|
||||
public:
|
||||
ADCw();
|
||||
~ADCw(){}
|
||||
|
||||
void testADC();
|
||||
void powerDownADC();
|
||||
JZ_REG * takeSamplesADC(int CHANNEL);
|
||||
void setClockDiv(uchar value){ ADC_SPI_CLKDIV = value;}
|
||||
void setBufferLen(int value){ BUFFER_LEN = value;}
|
||||
void setMuxChannels(uchar value){ MUX_CHANNELS = value;}
|
||||
private:
|
||||
void adcConfig(uchar CMD);
|
||||
int adcCheckBufferFull();
|
||||
|
||||
JZ_REG * ADCBuffer;
|
||||
uchar ADC_SPI_CLKDIV;
|
||||
int BUFFER_LEN;
|
||||
int BUFFER_OFFSET;
|
||||
uchar MUX_CHANNELS;
|
||||
};
|
||||
|
||||
#endif // ADCW_H
|
||||
33
Examples/Beta1/src/Makefile
Normal file
33
Examples/Beta1/src/Makefile
Normal file
@ -0,0 +1,33 @@
|
||||
CC = mipsel-openwrt-linux-gcc
|
||||
|
||||
all: UNROBOT_pwm_test
|
||||
|
||||
DEBUG = -O3 -g0
|
||||
|
||||
COMMON_SOURCES = UNROBOT_pwm_test.c jz47xx_gpio.c jz47xx_mmap.c
|
||||
|
||||
H_SOURCES = jz47xx_gpio.h jz47xx_mmap.h
|
||||
|
||||
INCLUDE = -I.
|
||||
|
||||
WARNINGS= -Wcast-align -Wpacked -Wpadded -Wall
|
||||
|
||||
CCFLAGS = ${INCLUDE} ${DEBUG} ${WARNINGS}
|
||||
|
||||
LDFLAGS =
|
||||
|
||||
COMMON_OBJECTS = $(COMMON_SOURCES:.cpp=.o)
|
||||
|
||||
|
||||
ADCw : $(COMMON_OBJECTS) ram_test.o
|
||||
$(CC) $(LDFLAGS) $(COMMON_OBJECTS) ram_test.o -o ram_test
|
||||
|
||||
|
||||
.c.o:
|
||||
$(CC) -c $(CCFLAGS) $< -o $@
|
||||
|
||||
clean:
|
||||
rm -f *.o ram_test ${EXEC} *~ ram_test
|
||||
|
||||
indent:
|
||||
indent -bad -bap -nbc -bl -nce -i2 --no-tabs --line-length120 $(COMMON_SOURCES) $(H_SOURCES)
|
||||
BIN
Examples/Beta1/src/UNROBOT_pwm_test
Normal file
BIN
Examples/Beta1/src/UNROBOT_pwm_test
Normal file
Binary file not shown.
80
Examples/Beta1/src/UNROBOT_pwm_test.c
Normal file
80
Examples/Beta1/src/UNROBOT_pwm_test.c
Normal file
@ -0,0 +1,80 @@
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "jz47xx_gpio.c"
|
||||
#include "jz47xx_mmap.c"
|
||||
|
||||
#define CS2_PORT JZ_GPIO_PORT_B
|
||||
#define CS2_PIN 26
|
||||
|
||||
int
|
||||
main ()
|
||||
{
|
||||
#ifdef DOUBLE
|
||||
set_fpu (0x27F); /* use double-precision rounding */
|
||||
#endif
|
||||
|
||||
int i;
|
||||
int pwm1=10; //PWM Led en SIE, entre 0 y 255
|
||||
int pwm2=255; //PWM Led fuera SIE, entre 0 y 255
|
||||
int dutycycle1; //PWM Led en SIE
|
||||
int dutycycle2; //PWM Led fuera SIE
|
||||
|
||||
JZ_PIO *pio;
|
||||
int *virt_addr;
|
||||
|
||||
// Set GPIOB26 as part of External Memory Controller
|
||||
pio = jz_gpio_map (CS2_PORT);
|
||||
jz_gpio_as_func (pio, CS2_PIN, 0);
|
||||
|
||||
virt_addr = (int *) jz_mmap (0x13010000) + 0x18;
|
||||
|
||||
printf ("\nIniciado: \nPrueba Beta Alpha3 UNROBOT \n");
|
||||
|
||||
if (*virt_addr != 0xFFF7700)
|
||||
{ // 0 WS, 8 bits
|
||||
*virt_addr = 0xFFF7700;
|
||||
printf ("Configuring CS2 8 bits \n");
|
||||
}
|
||||
else
|
||||
printf ("CS2, already configured\n");
|
||||
|
||||
virt_addr = (int *) jz_fpga_map (0x14000000);
|
||||
|
||||
dutycycle1=(int)((float)((100.0/255.0)*pwm1));
|
||||
dutycycle2=(int)((float)((100.0/255.0)*pwm2));
|
||||
|
||||
|
||||
|
||||
printf ("DUTY1:%d%% \n", dutycycle1);
|
||||
printf ("DUTY2:%d%% \n", dutycycle2);
|
||||
|
||||
printf ("Setting PWM1..\n");
|
||||
virt_addr[1024] = pwm1;
|
||||
|
||||
|
||||
printf ("Setting PWM2..\n");
|
||||
virt_addr[1536] = pwm2;
|
||||
virt_addr[1537] = pwm2;
|
||||
virt_addr[1535] = pwm2;
|
||||
|
||||
printf ("Writing In Memory1 the Dutycycles and pwm references from 0x100 to 0x103..\n");
|
||||
|
||||
virt_addr[512] = pwm1;
|
||||
virt_addr[513] = dutycycle1;
|
||||
virt_addr[514] = pwm2;
|
||||
virt_addr[515] = dutycycle2;
|
||||
|
||||
printf ("Reading from Memory1 the Dutycycles and pwm references..\n");
|
||||
|
||||
printf("1- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[512], virt_addr[513]);
|
||||
printf("2- PWM_REF:%d, Duty Cycle:%d%% \n", virt_addr[514], virt_addr[515]);
|
||||
|
||||
printf("1- Encoder:%d\n", virt_addr[0]);
|
||||
printf("1- Encoder:%d\n", virt_addr[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
119
Examples/Beta1/src/jz47xx_gpio.c
Normal file
119
Examples/Beta1/src/jz47xx_gpio.c
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
JZ47xx GPIO at userspace
|
||||
|
||||
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz47xx_gpio.h"
|
||||
#include "jz47xx_mmap.h"
|
||||
|
||||
|
||||
#define JZ_GPIO_BASE 0x10010000
|
||||
|
||||
void
|
||||
jz_gpio_as_output (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXFUNC = (1 << (o));
|
||||
pio->PXSELC = (1 << (o));
|
||||
pio->PXDIRS = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_as_input (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXFUNC = (1 << (o));
|
||||
pio->PXSELC = (1 << (o));
|
||||
pio->PXDIRC = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_as_irq (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXFUNC = (1 << (o));
|
||||
pio->PXSELS = (1 << (o));
|
||||
pio->PXDIRC = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_set_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXDATS = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXDATC = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val)
|
||||
{
|
||||
if (val == 0)
|
||||
pio->PXDATC = (1 << (o));
|
||||
else
|
||||
pio->PXDATS = (1 << (o));
|
||||
}
|
||||
|
||||
unsigned int
|
||||
jz_gpio_get_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
return (pio->PXPIN & (1 << o)) ? 1 : 0;
|
||||
}
|
||||
|
||||
int
|
||||
jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func)
|
||||
{
|
||||
switch (func)
|
||||
{
|
||||
case 0:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGC = (1 << o);
|
||||
pio->PXSELC = (1 << o);
|
||||
pio->PXPES = (1 << o);
|
||||
return 1;
|
||||
|
||||
case 1:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGC = (1 << o);
|
||||
pio->PXSELS = (1 << o);
|
||||
pio->PXPES = (1 << o);
|
||||
return 1;
|
||||
|
||||
case 2:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGS = (1 << o);
|
||||
pio->PXSELC = (1 << o);
|
||||
pio->PXPES = (1 << o);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
JZ_PIO *
|
||||
jz_gpio_map (int port)
|
||||
{
|
||||
JZ_PIO *pio;
|
||||
|
||||
pio = (JZ_PIO *) jz_mmap (JZ_GPIO_BASE);
|
||||
pio = (JZ_PIO *) ((unsigned int) pio + port * 0x100);
|
||||
|
||||
return pio;
|
||||
}
|
||||
110
Examples/Beta1/src/jz47xx_gpio.cpp
Normal file
110
Examples/Beta1/src/jz47xx_gpio.cpp
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
JZ47xx GPIO at userspace
|
||||
|
||||
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz47xx_gpio.h"
|
||||
#include "jz47xx_mmap.h"
|
||||
|
||||
|
||||
#define JZ_GPIO_BASE 0x10010000
|
||||
|
||||
void
|
||||
jz_gpio_as_output (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXFUNC = (1 << (o));
|
||||
pio->PXSELC = (1 << (o));
|
||||
pio->PXDIRS = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_as_input (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXFUNC = (1 << (o));
|
||||
pio->PXSELC = (1 << (o));
|
||||
pio->PXDIRC = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_set_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXDATS = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
pio->PXDATC = (1 << (o));
|
||||
}
|
||||
|
||||
void
|
||||
jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val)
|
||||
{
|
||||
if (val == 0)
|
||||
pio->PXDATC = (1 << (o));
|
||||
else
|
||||
pio->PXDATS = (1 << (o));
|
||||
}
|
||||
|
||||
unsigned int
|
||||
jz_gpio_get_pin (JZ_PIO * pio, unsigned int o)
|
||||
{
|
||||
return (pio->PXPIN & (1 << o)) ? 1 : 0;
|
||||
}
|
||||
|
||||
int
|
||||
jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func)
|
||||
{
|
||||
switch (func)
|
||||
{
|
||||
case 0:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGC = (1 << o);
|
||||
pio->PXSELC = (1 << o);
|
||||
return 1;
|
||||
|
||||
case 1:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGC = (1 << o);
|
||||
pio->PXSELS = (1 << o);
|
||||
return 1;
|
||||
|
||||
case 2:
|
||||
pio->PXFUNS = (1 << o);
|
||||
pio->PXTRGS = (1 << o);
|
||||
pio->PXSELC = (1 << o);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
JZ_PIO *
|
||||
jz_gpio_map (int port)
|
||||
{
|
||||
JZ_PIO *pio;
|
||||
|
||||
pio = (JZ_PIO *) jz_mmap (JZ_GPIO_BASE);
|
||||
pio = (JZ_PIO *) (pio + port * 0x100);
|
||||
|
||||
// pio = (JZ_PIO *) ((unsigned int) pio + port * 0x100);
|
||||
|
||||
return pio;
|
||||
}
|
||||
84
Examples/Beta1/src/jz47xx_gpio.h
Normal file
84
Examples/Beta1/src/jz47xx_gpio.h
Normal file
@ -0,0 +1,84 @@
|
||||
/*
|
||||
JZ47xx GPIO at userspace
|
||||
|
||||
Copyright (C) 2010 Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#ifndef __jz47xx_gpio_h__
|
||||
#define __jz47xx_gpio_h__
|
||||
|
||||
#define JZ_GPIO_PORT_A 0
|
||||
#define JZ_GPIO_PORT_B 1
|
||||
#define JZ_GPIO_PORT_C 2
|
||||
#define JZ_GPIO_PORT_D 3
|
||||
|
||||
typedef volatile unsigned int JZ_REG; /* Hardware register definition */
|
||||
|
||||
typedef struct _JZ_PIO
|
||||
{
|
||||
JZ_REG PXPIN; /* PIN Level Register */
|
||||
JZ_REG Reserved0;
|
||||
JZ_REG Reserved1;
|
||||
JZ_REG Reserved2;
|
||||
JZ_REG PXDAT; /* Port Data Register */
|
||||
JZ_REG PXDATS; /* Port Data Set Register */
|
||||
JZ_REG PXDATC; /* Port Data Clear Register */
|
||||
JZ_REG Reserved3;
|
||||
JZ_REG PXIM; /* Interrupt Mask Register */
|
||||
JZ_REG PXIMS; /* Interrupt Mask Set Reg */
|
||||
JZ_REG PXIMC; /* Interrupt Mask Clear Reg */
|
||||
JZ_REG Reserved4;
|
||||
JZ_REG PXPE; /* Pull Enable Register */
|
||||
JZ_REG PXPES; /* Pull Enable Set Reg. */
|
||||
JZ_REG PXPEC; /* Pull Enable Clear Reg. */
|
||||
JZ_REG Reserved5;
|
||||
JZ_REG PXFUN; /* Function Register */
|
||||
JZ_REG PXFUNS; /* Function Set Register */
|
||||
JZ_REG PXFUNC; /* Function Clear Register */
|
||||
JZ_REG Reserved6;
|
||||
JZ_REG PXSEL; /* Select Register */
|
||||
JZ_REG PXSELS; /* Select Set Register */
|
||||
JZ_REG PXSELC; /* Select Clear Register */
|
||||
JZ_REG Reserved7;
|
||||
JZ_REG PXDIR; /* Direction Register */
|
||||
JZ_REG PXDIRS; /* Direction Set Register */
|
||||
JZ_REG PXDIRC; /* Direction Clear Register */
|
||||
JZ_REG Reserved8;
|
||||
JZ_REG PXTRG; /* Trigger Register */
|
||||
JZ_REG PXTRGS; /* Trigger Set Register */
|
||||
JZ_REG PXTRGC; /* Trigger Set Register */
|
||||
JZ_REG Reserved9;
|
||||
JZ_REG PXFLG; /* Port Flag Register */
|
||||
JZ_REG PXFLGC; /* Port Flag clear Register */
|
||||
} JZ_PIO, *PJZ_PIO;
|
||||
|
||||
void jz_gpio_as_output (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_as_input (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_set_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_clear_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
void jz_gpio_out (JZ_PIO * pio, unsigned int o, unsigned int val);
|
||||
|
||||
unsigned int jz_gpio_get_pin (JZ_PIO * pio, unsigned int o);
|
||||
|
||||
int jz_gpio_as_func (JZ_PIO * pio, unsigned int o, int func);
|
||||
|
||||
JZ_PIO *jz_gpio_map (int port);
|
||||
|
||||
#endif
|
||||
64
Examples/Beta1/src/jz47xx_mmap.c
Normal file
64
Examples/Beta1/src/jz47xx_mmap.c
Normal file
@ -0,0 +1,64 @@
|
||||
/*
|
||||
* JZ47xx GPIO lines
|
||||
*
|
||||
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdlib.h>
|
||||
#include <termios.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz47xx_mmap.h"
|
||||
|
||||
|
||||
void *
|
||||
jz_mmap (off_t address)
|
||||
{
|
||||
int fd;
|
||||
|
||||
void *pio;
|
||||
|
||||
if ((fd = open ("/dev/mem", O_RDWR | O_SYNC)) == -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot open /dev/mem.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
pio = (void *) mmap (0, getpagesize (), PROT_READ | PROT_WRITE, MAP_SHARED, fd, address);
|
||||
|
||||
if (pio == (void *) -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot mmap.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
return pio;
|
||||
}
|
||||
|
||||
void *
|
||||
jz_fpga_map (off_t address)
|
||||
{
|
||||
int fd;
|
||||
|
||||
void *fpga;
|
||||
|
||||
if ((fd = open ("/dev/mem", O_RDWR | O_SYNC)) == -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot open /dev/mem.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
fpga = (void *) mmap (0, FPGA_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, address);
|
||||
|
||||
if (fpga == (void *) -1)
|
||||
{
|
||||
fprintf (stderr, "Cannot mmap.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
return fpga;
|
||||
}
|
||||
|
||||
17
Examples/Beta1/src/jz47xx_mmap.h
Normal file
17
Examples/Beta1/src/jz47xx_mmap.h
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* JZ47xx GPIO lines
|
||||
*
|
||||
* Written 2010 by Andres Calderon andres.calderon@emqbit.com
|
||||
*/
|
||||
|
||||
#ifndef __jz47xx_mmap_h__
|
||||
#define __jz47xx_mmap_h__
|
||||
|
||||
#include <sys/mman.h>
|
||||
|
||||
#define FPGA_SIZE (1 << 15)
|
||||
|
||||
void *jz_mmap (off_t address);
|
||||
void *jz_fpga_map (off_t address);
|
||||
|
||||
#endif
|
||||
47
Examples/Beta1/src/jz_adc_peripheral.c
Normal file
47
Examples/Beta1/src/jz_adc_peripheral.c
Normal file
@ -0,0 +1,47 @@
|
||||
/* ADC Peripheral.c
|
||||
|
||||
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
|
||||
Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "jz_adc_peripheral.h"
|
||||
|
||||
JZ_REG *
|
||||
jz_adc_init()
|
||||
{
|
||||
JZ_PIO *pio;
|
||||
JZ_REG *virt_addr;
|
||||
|
||||
pio = jz_gpio_map (CS2_PORT);
|
||||
jz_gpio_as_func (pio, CS2_PIN, 0);
|
||||
|
||||
virt_addr = (JZ_REG *) (jz_mmap(0x13010000) + 0x18);
|
||||
|
||||
if (*virt_addr != 0x0FFF7700)
|
||||
{
|
||||
*virt_addr = 0x0FFF7700;
|
||||
printf ("ADC: Configuring CS2 8 bits and 0 WS: %08X\n", *virt_addr);
|
||||
}
|
||||
else
|
||||
printf ("ADC: CS2, already configured: %08X\n", *virt_addr);
|
||||
|
||||
virt_addr = (JZ_REG *) jz_mmap (0x14000000);
|
||||
|
||||
return virt_addr;
|
||||
}
|
||||
81
Examples/Beta1/src/jz_adc_peripheral.h
Normal file
81
Examples/Beta1/src/jz_adc_peripheral.h
Normal file
@ -0,0 +1,81 @@
|
||||
/* ADC Peripheral.h
|
||||
|
||||
Copyright (C) 2010 Carlos Camargo cicamargoba@unal.edu.co
|
||||
Andres Calderon andres.calderon@emqbit.com
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
|
||||
|
||||
#ifndef __adc_peripheral_h__
|
||||
#define __adc_peripheral_h__
|
||||
|
||||
#include "jz47xx_mmap.c"
|
||||
#include "jz47xx_gpio.c"
|
||||
|
||||
#define ADC_CMD_NONE 0x00 /* Nothing to do */
|
||||
#define ADC_CMD_SET_SPI_CLKDIV 0x00 /* Set clock divider for ADC sclk */
|
||||
#define ADC_CMD_SET_BUFFER_SIZE 0x00 /* Set clock divider for ADC sclk */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL0 0x30 /* Set channel 0 */
|
||||
#define ADC_CMD_READ_CHANNEL0 0x20 /* Read channel 0 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL1 0x31 /* Set channel 1 */
|
||||
#define ADC_CMD_READ_CHANNEL1 0x21 /* Read channel 1 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL2 0x32 /* Set channel 2 */
|
||||
#define ADC_CMD_READ_CHANNEL2 0x22 /* Read channel 2 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL3 0x33 /* Set channel 3 */
|
||||
#define ADC_CMD_READ_CHANNEL3 0x23 /* Read channel 3 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL4 0x34 /* Set channel 4 */
|
||||
#define ADC_CMD_READ_CHANNEL4 0x24 /* Read channel 4 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL5 0x35 /* Set channel 5 */
|
||||
#define ADC_CMD_READ_CHANNEL5 0x25 /* Read channel 5 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL6 0x36 /* Set channel 6 */
|
||||
#define ADC_CMD_READ_CHANNEL6 0x26 /* Read channel 6 */
|
||||
|
||||
#define ADC_CMD_SET_CHANNEL7 0x37 /* Set channel 7 */
|
||||
#define ADC_CMD_READ_CHANNEL7 0x27 /* Read channel 8 */
|
||||
|
||||
#define ADC_CMD_SET_POWER_DOWN 0X38 /* Set ADC power down mode (1uA) */
|
||||
|
||||
#define ADC_CMD_SET_FAST_CONV 0X39 /* Initialize ADC Fast Convertion(<10us)*/
|
||||
|
||||
#define ADC_CMD_SET_LOW_CONV 0X3A /* Initialize ADC Slow Convertion(<40us)*/
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_1 0x3B /* Set Autoselft ADC {(Vref+)-(Vref-)}/2*/
|
||||
#define ADC_CMD_READ_AUTOSELFT_1 0x2B /* Read Autoselft ADC 1 (0x0200) */
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_2 0x3C /* Set Autoselft ADC (Vref-) */
|
||||
#define ADC_CMD_READ_AUTOSELFT_2 0x2C /* Read Autoselft ADC 2 (0x0000) */
|
||||
|
||||
#define ADC_CMD_SET_AUTOSELFT_3 0x3D /* Set Autoselft ADC (Vref+) */
|
||||
#define ADC_CMD_READ_AUTOSELFT_3 0x2D /* Read Autoselft ADC 3 (0x03FF) */
|
||||
|
||||
#define ADC_SPI_CLKDIV_MIN 0x08 /* 50/(2*9) -> 2.78MHz (MAX=2.8MHz) */
|
||||
#define ADC_SPI_CLKDIV_MAX 0xFF /* 50/(2*256) -> 97.65KHz */
|
||||
|
||||
#define ADC_MAX_BUFFER 0x3FE/* 1022 reads/commands */
|
||||
|
||||
#define CS2_PORT JZ_GPIO_PORT_B
|
||||
#define CS2_PIN 26
|
||||
|
||||
typedef unsigned char uchar;
|
||||
|
||||
JZ_REG *jz_adc_init();
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user