mirror of
git://projects.qi-hardware.com/sie-ceimtun.git
synced 2025-01-10 15:20:14 +02:00
19 lines
1.0 KiB
XML
19 lines
1.0 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- IMPORTANT: This is an internal file that has been generated
|
|
by the Xilinx ISE software. Any direct editing or
|
|
changes made to this file may result in unpredictable
|
|
behavior or data corruption. It is strongly advised that
|
|
users do not edit the contents of this file. -->
|
|
<messages>
|
|
<msg type="warning" file="HDLCompilers" num="259" delta="new" ><arg fmt="%s" index="1">"../enco.v" line 65 </arg>Connection to input port '<arg fmt="%s" index="2">ADDRB</arg>' does not match port size
|
|
</msg>
|
|
|
|
<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">rdBus3</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00000000</arg>.
|
|
</msg>
|
|
|
|
<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">csN<3></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
|
|
</msg>
|
|
|
|
</messages>
|
|
|