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27 lines
586 B
Verilog
27 lines
586 B
Verilog
`timescale 1ns / 1ps
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module PWM(clk, enable, PWM_in, PWM_out);
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input clk, enable;
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input [7:0] PWM_in;
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output PWM_out;
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reg [7:0] PWM_in_reg=0; //Registro temporal para reiniciar el acumulador
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reg [7:0] PWM_accum=0; //Acumulador
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reg [8:0] ClkCount=0; //Para dividir la frecuencia en 2^VAL
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//Divisor de frecuencia
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always @(posedge clk) if(enable) ClkCount <= ClkCount + 1;
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//Contador para el PWM
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always @(posedge clk)
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begin
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PWM_in_reg<=PWM_in;
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if(PWM_in_reg==PWM_in) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
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end
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//Salida para el PWM
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assign PWM_out=(PWM_accum<PWM_in);
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endmodule
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