mirror of
git://projects.qi-hardware.com/sie-ceimtun.git
synced 2024-12-05 05:07:12 +02:00
Yet another .bit fix
This commit is contained in:
Erwin Lopez
parent
03456560f3
commit
4618f6427e
Binary file not shown.
@ -15,7 +15,7 @@ NET quadD LOC = "P66";
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#NET quadD LOC = "P33"; #PINES DE PRUEBA
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NET "hbridge<3>" LOC = "P53";
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NET "hbridge<2>" LOC = "P57";
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NET "hbridge<1>" LOC = "P27";
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NET "hbridge<1>" LOC = "P47";
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NET "hbridge<0>" LOC = "P49";
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#NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
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#NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
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@ -5,10 +5,10 @@
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behavior or data corruption. It is strongly advised that
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users do not edit the contents of this file. -->
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<messages>
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<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
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<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
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</msg>
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<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
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<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
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</msg>
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</messages>
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@ -12,7 +12,5 @@
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<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
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<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
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</messages>
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@ -5,7 +5,7 @@
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application stringID="Map" timeStamp="Sun Oct 31 14:11:34 2010">
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<application stringID="Map" timeStamp="Sun Oct 31 20:56:35 2010">
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<section stringID="User_Env">
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<table stringID="User_EnvVar">
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<column stringID="variable"/>
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@ -33,7 +33,7 @@
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<column stringID="speed"/>
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<row stringID="row" value="0">
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<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
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<item stringID="speed" value="2201.000 MHz"/>
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<item stringID="speed" value="1200.000 MHz"/>
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</row>
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</table>
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</section>
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@ -53,7 +53,7 @@
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<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
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<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
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<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
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<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375984"/>
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<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375948"/>
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<item stringID="MAP_TOTAL_REAL_TIME" value="5 secs "/>
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<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
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</section>
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@ -5,7 +5,7 @@
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application stringID="par" timeStamp="Sun Oct 31 14:11:36 2010">
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<application stringID="par" timeStamp="Sun Oct 31 20:56:38 2010">
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<section stringID="User_Env">
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<table stringID="User_EnvVar">
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<column stringID="variable"/>
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@ -47,12 +47,12 @@
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</task>
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<task stringID="PAR_PAR">
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<section stringID="PAR_DESIGN_SUMMARY">
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<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="23 secs "/>
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<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="22 secs "/>
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<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="21 secs "/>
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<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="19 secs "/>
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<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
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<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
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<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="24 secs "/>
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<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="22 secs "/>
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<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="22 secs "/>
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<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="19 secs "/>
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</section>
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</task>
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<task stringID="PAR_par">
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@ -72,7 +72,7 @@
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<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/>
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<item label="Locked" stringID="LOCKED" value="No"/>
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<item dataType="float" label="Fanout" stringID="FANOUT" value="99.000000"/>
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<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.075000"/>
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<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.086000"/>
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<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.204000"/>
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</row>
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</table>
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@ -344,18 +344,10 @@
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</row>
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<row stringID="row" value="27">
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<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P27"/>
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<item label="Signal
Name" stringID="Signal_Name" value="hbridge<1>"/>
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<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
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<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFS"/>
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<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L02N_2/MOSI/CSI_B"/>
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<item stringID="Direction" value="OUTPUT"/>
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<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
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<item stringID="Direction" value="UNUSED"/>
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<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
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<item label="Drive
(mA)" stringID="Drive" value="12"/>
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<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
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<item label="Termination" stringID="Termination" value="NONE**"/>
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<item label="Constraint" stringID="Constraint" value="LOCATED"/>
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<item label="IO
Register" stringID="IO_Register" value="NO"/>
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<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
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</row>
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<row stringID="row" value="28">
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<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P28"/>
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@ -492,10 +484,18 @@
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</row>
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<row stringID="row" value="47">
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<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P47"/>
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<item label="Pin
Usage" stringID="Pin_Usage" value="DIFFM"/>
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<item label="Signal
Name" stringID="Signal_Name" value="hbridge<1>"/>
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<item label="Pin
Usage" stringID="Pin_Usage" value="IOB"/>
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<item label="Pin
Name" sort="smart" stringID="Pin_Name" value="IO_L08P_2/VS2"/>
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<item stringID="Direction" value="UNUSED"/>
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<item stringID="Direction" value="OUTPUT"/>
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<item label="IO
Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
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<item label="IO Bank
Number" stringID="IO_Bank_Number" value="2"/>
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<item label="Drive
(mA)" stringID="Drive" value="12"/>
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<item label="Slew
Rate" stringID="Slew_Rate" value="SLOW"/>
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<item label="Termination" stringID="Termination" value="NONE**"/>
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<item label="Constraint" stringID="Constraint" value="LOCATED"/>
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<item label="IO
Register" stringID="IO_Register" value="NO"/>
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<item label="Signal
Integrity" stringID="Signal_Integrity" value="NONE"/>
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</row>
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<row stringID="row" value="48">
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<item label="Pin
Number" sort="smart" stringID="Pin_Number" value="P48"/>
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@ -1,2 +1,2 @@
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/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project.ngc 1288551154
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/home/erwin/Erwin/Documentos/UNAL/CEIMTUN/2010-UNRobot/Curso Embebidos/Test_Video/Beta1/logic/build/project.ngc 1288576581
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OK
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@ -27,7 +27,7 @@ NGDBUILD Design Results Summary:
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Number of errors: 0
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Number of warnings: 0
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Total memory usage is 235688 kilobytes
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Total memory usage is 235664 kilobytes
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Writing NGD file "project.ngd" ...
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Total REAL time to NGDBUILD completion: 3 sec
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@ -644,13 +644,13 @@ Delay: 6.573ns (Levels of Logic = 3)
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=========================================================================
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Total REAL time to Xst completion: 8.00 secs
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Total CPU time to Xst completion: 6.36 secs
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Total REAL time to Xst completion: 7.00 secs
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Total CPU time to Xst completion: 6.07 secs
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-->
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Total memory usage is 336212 kilobytes
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Total memory usage is 336208 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 2 ( 0 filtered)
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@ -8,7 +8,7 @@ Target Device : xc3s500e
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Target Package : vq100
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Target Speed : -4
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Mapper Version : spartan3e -- $Revision: 1.52 $
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Mapped Date : Sun Oct 31 14:11:28 2010
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Mapped Date : Sun Oct 31 20:56:29 2010
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Mapping design into LUTs...
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Writing file project.ngm...
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@ -8,7 +8,7 @@ Target Device : xc3s500e
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Target Package : vq100
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Target Speed : -4
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Mapper Version : spartan3e -- $Revision: 1.52 $
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Mapped Date : Sun Oct 31 14:11:28 2010
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Mapped Date : Sun Oct 31 20:56:29 2010
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Design Summary
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--------------
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -5,7 +5,7 @@
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application stringID="Xst" timeStamp="Sun Oct 31 13:52:26 2010">
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<application stringID="Xst" timeStamp="Sun Oct 31 20:56:14 2010">
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<section stringID="User_Env">
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<table stringID="User_EnvVar">
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<column stringID="variable"/>
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@ -33,7 +33,7 @@
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<column stringID="speed"/>
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<row stringID="row" value="0">
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<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
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<item stringID="speed" value="2201.000 MHz"/>
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<item stringID="speed" value="1200.000 MHz"/>
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</row>
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</table>
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</section>
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File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
@ -1,5 +1,5 @@
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//! **************************************************************************
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// Written by: Map M.63c on Sun Oct 31 14:11:32 2010
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// Written by: Map M.63c on Sun Oct 31 20:56:33 2010
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//! **************************************************************************
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SCHEMATIC START;
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@ -26,7 +26,7 @@ COMP "addr<12>" LOCATE = SITE "P90" LEVEL 1;
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COMP "ncs" LOCATE = SITE "P69" LEVEL 1;
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COMP "noe" LOCATE = SITE "P86" LEVEL 1;
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COMP "hbridge<0>" LOCATE = SITE "P49" LEVEL 1;
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COMP "hbridge<1>" LOCATE = SITE "P27" LEVEL 1;
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COMP "hbridge<1>" LOCATE = SITE "P47" LEVEL 1;
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COMP "hbridge<2>" LOCATE = SITE "P57" LEVEL 1;
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COMP "hbridge<3>" LOCATE = SITE "P53" LEVEL 1;
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COMP "quadA" LOCATE = SITE "P71" LEVEL 1;
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@ -5,7 +5,7 @@
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application stringID="NgdBuild" timeStamp="Sun Oct 31 14:11:24 2010">
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<application stringID="NgdBuild" timeStamp="Sun Oct 31 20:56:27 2010">
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<section stringID="User_Env">
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<table stringID="User_EnvVar">
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<column stringID="variable"/>
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@ -33,7 +33,7 @@
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<column stringID="speed"/>
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<row stringID="row" value="0">
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<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU T6670 @ 2.20GHz"/>
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<item stringID="speed" value="1200.000 MHz"/>
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<item stringID="speed" value="2201.000 MHz"/>
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</row>
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</table>
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</section>
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@ -4,7 +4,7 @@ Loading device for application Rf_Device from file '3s500e.nph' in environment
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/home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
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"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
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Sun Oct 31 14:12:04 2010
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Sun Oct 31 20:57:04 2010
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/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -l -w -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK project_r.ncd
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@ -1,7 +1,7 @@
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Release 12.2 Drc M.63c (lin64)
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Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
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Sun Oct 31 14:12:04 2010
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Sun Oct 31 20:57:04 2010
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drc -z project_r.ncd
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@ -1,5 +1,5 @@
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Revision 3
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; Created by bitgen M.63c at Sun Oct 31 14:12:05 2010
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; Created by bitgen M.63c at Sun Oct 31 20:57:05 2010
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; Bit lines have the following form:
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; <offset> <frame address> <frame offset> <information>
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; <information> may be zero or more <kw>=<value> pairs
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@ -2102,7 +2102,6 @@ Bit 249612 0x000a2200 1292 Block=RAMB16_X0Y6 Ram=B:BIT416
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Bit 249613 0x000a2200 1293 Block=RAMB16_X0Y6 Ram=B:BIT544
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Bit 249614 0x000a2200 1294 Block=RAMB16_X0Y6 Ram=B:BIT672
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Bit 249615 0x000a2200 1295 Block=RAMB16_X0Y6 Ram=B:BIT800
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Bit 251376 0x000a2200 3056 Block=P27 Latch=O2 Net=puente/OUT1B/Mcompar_PWM_out_cy<7>
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Bit 251696 0x000a2400 272 Block=RAMB16_X0Y9 Ram=B:BIT95
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Bit 251697 0x000a2400 273 Block=RAMB16_X0Y9 Ram=B:BIT223
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Bit 251698 0x000a2400 274 Block=RAMB16_X0Y9 Ram=B:BIT351
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@ -73815,149 +73814,150 @@ Bit 479298 0x00121e00 1282 Block=RAMB16_X0Y6 Ram=B:BIT16240
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Bit 479299 0x00121e00 1283 Block=RAMB16_X0Y6 Ram=B:BIT16368
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Bit 479305 0x00121e00 1289 Block=RAMB16_X0Y6 Ram=B:BIT16224
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Bit 479306 0x00121e00 1290 Block=RAMB16_X0Y6 Ram=B:BIT16352
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Bit 488538 0x00122400 1210 Block=SLICE_X13Y56 Latch=YQ Net=wrBus<6>
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Bit 488541 0x00122400 1213 Block=SLICE_X13Y56 Latch=XQ Net=wrBus<7>
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Bit 547610 0x00142400 1306 Block=SLICE_X15Y53 Latch=YQ Net=wrBus<4>
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Bit 547613 0x00142400 1309 Block=SLICE_X15Y53 Latch=XQ Net=wrBus<5>
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Bit 547802 0x00142400 1498 Block=SLICE_X15Y47 Latch=YQ Net=wrBus<0>
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Bit 547805 0x00142400 1501 Block=SLICE_X15Y47 Latch=XQ Net=wrBus<1>
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Bit 606714 0x00162400 1434 Block=SLICE_X17Y49 Latch=YQ Net=wrBus<2>
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Bit 606717 0x00162400 1437 Block=SLICE_X17Y49 Latch=XQ Net=wrBus<3>
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Bit 665594 0x00182400 1338 Block=SLICE_X18Y52 Latch=YQ Net=puente/OUT1B/PWM_in_reg<0>
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Bit 665597 0x00182400 1341 Block=SLICE_X18Y52 Latch=XQ Net=puente/OUT1B/PWM_in_reg<1>
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Bit 547770 0x00142400 1466 Block=SLICE_X15Y48 Latch=YQ Net=wrBus<2>
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Bit 547773 0x00142400 1469 Block=SLICE_X15Y48 Latch=XQ Net=wrBus<3>
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Bit 547834 0x00142400 1530 Block=SLICE_X15Y46 Latch=YQ Net=wrBus<0>
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Bit 547837 0x00142400 1533 Block=SLICE_X15Y46 Latch=XQ Net=wrBus<1>
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Bit 606554 0x00162400 1274 Block=SLICE_X17Y54 Latch=YQ Net=wrBus<4>
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Bit 606557 0x00162400 1277 Block=SLICE_X17Y54 Latch=XQ Net=wrBus<5>
|
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Bit 667407 0x001a0000 47 Block=P95 Latch=IQ1 Net=buffer_addr<7>
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Bit 667432 0x001a0000 72 Block=P94 Latch=IQ1 Net=buffer_addr<8>
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Bit 668730 0x001a0000 1370 Block=SLICE_X19Y51 Latch=YQ Net=puente/OUT1B/PWM_in_reg<2>
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Bit 668733 0x001a0000 1373 Block=SLICE_X19Y51 Latch=XQ Net=puente/OUT1B/PWM_in_reg<3>
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Bit 724474 0x001a2400 1242 Block=SLICE_X20Y55 Latch=YQ Net=puente/PWM_2<2>
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Bit 724477 0x001a2400 1245 Block=SLICE_X20Y55 Latch=XQ Net=puente/PWM_2<3>
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Bit 724506 0x001a2400 1274 Block=SLICE_X20Y54 Latch=YQ Net=puente/PWM_2<4>
|
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Bit 724509 0x001a2400 1277 Block=SLICE_X20Y54 Latch=XQ Net=puente/PWM_2<5>
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Bit 724634 0x001a2400 1402 Block=SLICE_X20Y50 Latch=YQ Net=puente/PWM_2<0>
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Bit 724637 0x001a2400 1405 Block=SLICE_X20Y50 Latch=XQ Net=puente/PWM_2<1>
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Bit 724666 0x001a2400 1434 Block=SLICE_X20Y49 Latch=YQ Net=puente/OUT1B/PWM_in_reg<6>
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Bit 724669 0x001a2400 1437 Block=SLICE_X20Y49 Latch=XQ Net=puente/OUT1B/PWM_in_reg<7>
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Bit 727642 0x001c0000 1306 Block=SLICE_X21Y53 Latch=YQ Net=puente/OUT1B/PWM_accum<7>
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Bit 727645 0x001c0000 1309 Block=SLICE_X21Y53 Latch=XQ Net=puente/OUT1B/PWM_accum<6>
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Bit 727674 0x001c0000 1338 Block=SLICE_X21Y52 Latch=YQ Net=puente/OUT1B/PWM_accum<5>
|
||||
Bit 727677 0x001c0000 1341 Block=SLICE_X21Y52 Latch=XQ Net=puente/OUT1B/PWM_accum<4>
|
||||
Bit 727706 0x001c0000 1370 Block=SLICE_X21Y51 Latch=YQ Net=puente/OUT1B/PWM_accum<3>
|
||||
Bit 727709 0x001c0000 1373 Block=SLICE_X21Y51 Latch=XQ Net=puente/OUT1B/PWM_accum<2>
|
||||
Bit 727738 0x001c0000 1402 Block=SLICE_X21Y50 Latch=YQ Net=puente/OUT1B/PWM_accum<1>
|
||||
Bit 727741 0x001c0000 1405 Block=SLICE_X21Y50 Latch=XQ Net=puente/OUT1B/PWM_accum<0>
|
||||
Bit 783610 0x001c2400 1402 Block=SLICE_X22Y50 Latch=YQ Net=puente/PWM_2<6>
|
||||
Bit 783613 0x001c2400 1405 Block=SLICE_X22Y50 Latch=XQ Net=puente/PWM_2<7>
|
||||
Bit 786714 0x001e0000 1402 Block=SLICE_X23Y50 Latch=YQ Net=puente/OUT1B/PWM_in_reg<4>
|
||||
Bit 786717 0x001e0000 1405 Block=SLICE_X23Y50 Latch=XQ Net=puente/OUT1B/PWM_in_reg<5>
|
||||
Bit 845370 0x00200000 1082 Block=SLICE_X25Y60 Latch=YQ Net=puente/we1
|
||||
Bit 904154 0x00220000 890 Block=SLICE_X27Y66 Latch=YQ Net=enco1/count<7>
|
||||
Bit 904157 0x00220000 893 Block=SLICE_X27Y66 Latch=XQ Net=enco1/count<6>
|
||||
Bit 904186 0x00220000 922 Block=SLICE_X27Y65 Latch=YQ Net=enco1/count<5>
|
||||
Bit 904189 0x00220000 925 Block=SLICE_X27Y65 Latch=XQ Net=enco1/count<4>
|
||||
Bit 904218 0x00220000 954 Block=SLICE_X27Y64 Latch=YQ Net=enco1/count<3>
|
||||
Bit 904221 0x00220000 957 Block=SLICE_X27Y64 Latch=XQ Net=enco1/count<2>
|
||||
Bit 904250 0x00220000 986 Block=SLICE_X27Y63 Latch=YQ Net=enco1/count<1>
|
||||
Bit 904253 0x00220000 989 Block=SLICE_X27Y63 Latch=XQ Net=enco1/count<0>
|
||||
Bit 904346 0x00220000 1082 Block=SLICE_X27Y60 Latch=YQ Net=enco2/count<7>
|
||||
Bit 904349 0x00220000 1085 Block=SLICE_X27Y60 Latch=XQ Net=enco2/count<6>
|
||||
Bit 904378 0x00220000 1114 Block=SLICE_X27Y59 Latch=YQ Net=enco2/count<5>
|
||||
Bit 904381 0x00220000 1117 Block=SLICE_X27Y59 Latch=XQ Net=enco2/count<4>
|
||||
Bit 904410 0x00220000 1146 Block=SLICE_X27Y58 Latch=YQ Net=enco2/count<3>
|
||||
Bit 904413 0x00220000 1149 Block=SLICE_X27Y58 Latch=XQ Net=enco2/count<2>
|
||||
Bit 904442 0x00220000 1178 Block=SLICE_X27Y57 Latch=YQ Net=enco2/count<1>
|
||||
Bit 904445 0x00220000 1181 Block=SLICE_X27Y57 Latch=XQ Net=enco2/count<0>
|
||||
Bit 668282 0x001a0000 922 Block=SLICE_X19Y65 Latch=YQ Net=wrBus<6>
|
||||
Bit 668285 0x001a0000 925 Block=SLICE_X19Y65 Latch=XQ Net=wrBus<7>
|
||||
Bit 845114 0x00200000 826 Block=SLICE_X25Y68 Latch=YQ Net=enco1/count<7>
|
||||
Bit 845117 0x00200000 829 Block=SLICE_X25Y68 Latch=XQ Net=enco1/count<6>
|
||||
Bit 845146 0x00200000 858 Block=SLICE_X25Y67 Latch=YQ Net=enco1/count<5>
|
||||
Bit 845149 0x00200000 861 Block=SLICE_X25Y67 Latch=XQ Net=enco1/count<4>
|
||||
Bit 845178 0x00200000 890 Block=SLICE_X25Y66 Latch=YQ Net=enco1/count<3>
|
||||
Bit 845181 0x00200000 893 Block=SLICE_X25Y66 Latch=XQ Net=enco1/count<2>
|
||||
Bit 845210 0x00200000 922 Block=SLICE_X25Y65 Latch=YQ Net=enco1/count<1>
|
||||
Bit 845213 0x00200000 925 Block=SLICE_X25Y65 Latch=XQ Net=enco1/count<0>
|
||||
Bit 845402 0x00200000 1114 Block=SLICE_X25Y59 Latch=YQ Net=enco2/count<7>
|
||||
Bit 845405 0x00200000 1117 Block=SLICE_X25Y59 Latch=XQ Net=enco2/count<6>
|
||||
Bit 845434 0x00200000 1146 Block=SLICE_X25Y58 Latch=YQ Net=enco2/count<5>
|
||||
Bit 845437 0x00200000 1149 Block=SLICE_X25Y58 Latch=XQ Net=enco2/count<4>
|
||||
Bit 845466 0x00200000 1178 Block=SLICE_X25Y57 Latch=YQ Net=enco2/count<3>
|
||||
Bit 845469 0x00200000 1181 Block=SLICE_X25Y57 Latch=XQ Net=enco2/count<2>
|
||||
Bit 845498 0x00200000 1210 Block=SLICE_X25Y56 Latch=YQ Net=enco2/count<1>
|
||||
Bit 845501 0x00200000 1213 Block=SLICE_X25Y56 Latch=XQ Net=enco2/count<0>
|
||||
Bit 904346 0x00220000 1082 Block=SLICE_X27Y60 Latch=YQ Net=puente/we1
|
||||
Bit 909416 0x00220200 3048 Block=P30 Latch=I Net=reset_IBUF
|
||||
Bit 960474 0x00222400 1338 Block=SLICE_X28Y52 Latch=YQ Net=puente/PWM_1<0>
|
||||
Bit 960477 0x00222400 1341 Block=SLICE_X28Y52 Latch=XQ Net=puente/PWM_1<1>
|
||||
Bit 960538 0x00222400 1402 Block=SLICE_X28Y50 Latch=YQ Net=puente/PWM_1<2>
|
||||
Bit 960541 0x00222400 1405 Block=SLICE_X28Y50 Latch=XQ Net=puente/PWM_1<3>
|
||||
Bit 960602 0x00222400 1466 Block=SLICE_X28Y48 Latch=YQ Net=puente/PWM_1<6>
|
||||
Bit 960605 0x00222400 1469 Block=SLICE_X28Y48 Latch=XQ Net=puente/PWM_1<7>
|
||||
Bit 960730 0x00222400 1594 Block=SLICE_X28Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<0>
|
||||
Bit 960733 0x00222400 1597 Block=SLICE_X28Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<1>
|
||||
Bit 960314 0x00222400 1178 Block=SLICE_X28Y57 Latch=YQ Net=puente/PWM_4<0>
|
||||
Bit 960317 0x00222400 1181 Block=SLICE_X28Y57 Latch=XQ Net=puente/PWM_4<1>
|
||||
Bit 960410 0x00222400 1274 Block=SLICE_X28Y54 Latch=YQ Net=puente/OUT1B/PWM_in_reg<4>
|
||||
Bit 960413 0x00222400 1277 Block=SLICE_X28Y54 Latch=XQ Net=puente/OUT1B/PWM_in_reg<5>
|
||||
Bit 960442 0x00222400 1306 Block=SLICE_X28Y53 Latch=YQ Net=puente/PWM_2<0>
|
||||
Bit 960445 0x00222400 1309 Block=SLICE_X28Y53 Latch=XQ Net=puente/PWM_2<1>
|
||||
Bit 960538 0x00222400 1402 Block=SLICE_X28Y50 Latch=YQ Net=puente/PWM_1<6>
|
||||
Bit 960541 0x00222400 1405 Block=SLICE_X28Y50 Latch=XQ Net=puente/PWM_1<7>
|
||||
Bit 960570 0x00222400 1434 Block=SLICE_X28Y49 Latch=YQ Net=puente/PWM_1<4>
|
||||
Bit 960573 0x00222400 1437 Block=SLICE_X28Y49 Latch=XQ Net=puente/PWM_1<5>
|
||||
Bit 960602 0x00222400 1466 Block=SLICE_X28Y48 Latch=YQ Net=puente/OUT1A/PWM_in_reg<4>
|
||||
Bit 960605 0x00222400 1469 Block=SLICE_X28Y48 Latch=XQ Net=puente/OUT1A/PWM_in_reg<5>
|
||||
Bit 962272 0x00240000 32 Block=P92 Latch=IQ1 Net=buffer_addr<9>
|
||||
Bit 963610 0x00240000 1370 Block=SLICE_X29Y51 Latch=YQ Net=puente/PWM_1<4>
|
||||
Bit 963613 0x00240000 1373 Block=SLICE_X29Y51 Latch=XQ Net=puente/PWM_1<5>
|
||||
Bit 963674 0x00240000 1434 Block=SLICE_X29Y49 Latch=YQ Net=puente/OUT1A/PWM_accum<7>
|
||||
Bit 963677 0x00240000 1437 Block=SLICE_X29Y49 Latch=XQ Net=puente/OUT1A/PWM_accum<6>
|
||||
Bit 963706 0x00240000 1466 Block=SLICE_X29Y48 Latch=YQ Net=puente/OUT1A/PWM_accum<5>
|
||||
Bit 963709 0x00240000 1469 Block=SLICE_X29Y48 Latch=XQ Net=puente/OUT1A/PWM_accum<4>
|
||||
Bit 963738 0x00240000 1498 Block=SLICE_X29Y47 Latch=YQ Net=puente/OUT1A/PWM_accum<3>
|
||||
Bit 963741 0x00240000 1501 Block=SLICE_X29Y47 Latch=XQ Net=puente/OUT1A/PWM_accum<2>
|
||||
Bit 963770 0x00240000 1530 Block=SLICE_X29Y46 Latch=YQ Net=puente/OUT1A/PWM_accum<1>
|
||||
Bit 963773 0x00240000 1533 Block=SLICE_X29Y46 Latch=XQ Net=puente/OUT1A/PWM_accum<0>
|
||||
Bit 963834 0x00240000 1594 Block=SLICE_X29Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<2>
|
||||
Bit 963837 0x00240000 1597 Block=SLICE_X29Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<3>
|
||||
Bit 1019482 0x00242400 1370 Block=SLICE_X30Y51 Latch=YQ Net=puente/OUT2B/PWM_in_reg<2>
|
||||
Bit 1019485 0x00242400 1373 Block=SLICE_X30Y51 Latch=XQ Net=puente/OUT2B/PWM_in_reg<3>
|
||||
Bit 1019514 0x00242400 1402 Block=SLICE_X30Y50 Latch=YQ Net=puente/PWM_4<2>
|
||||
Bit 1019517 0x00242400 1405 Block=SLICE_X30Y50 Latch=XQ Net=puente/PWM_4<3>
|
||||
Bit 1019674 0x00242400 1562 Block=SLICE_X30Y45 Latch=YQ Net=puente/PWM_4<0>
|
||||
Bit 1019677 0x00242400 1565 Block=SLICE_X30Y45 Latch=XQ Net=puente/PWM_4<1>
|
||||
Bit 1019706 0x00242400 1594 Block=SLICE_X30Y44 Latch=YQ Net=puente/OUT1A/PWM_in_reg<6>
|
||||
Bit 1019709 0x00242400 1597 Block=SLICE_X30Y44 Latch=XQ Net=puente/OUT1A/PWM_in_reg<7>
|
||||
Bit 963450 0x00240000 1210 Block=SLICE_X29Y56 Latch=YQ Net=puente/OUT2B/PWM_in_reg<0>
|
||||
Bit 963453 0x00240000 1213 Block=SLICE_X29Y56 Latch=XQ Net=puente/OUT2B/PWM_in_reg<1>
|
||||
Bit 963546 0x00240000 1306 Block=SLICE_X29Y53 Latch=YQ Net=puente/OUT1B/PWM_in_reg<0>
|
||||
Bit 963549 0x00240000 1309 Block=SLICE_X29Y53 Latch=XQ Net=puente/OUT1B/PWM_in_reg<1>
|
||||
Bit 963578 0x00240000 1338 Block=SLICE_X29Y52 Latch=YQ Net=puente/PWM_2<6>
|
||||
Bit 963581 0x00240000 1341 Block=SLICE_X29Y52 Latch=XQ Net=puente/PWM_2<7>
|
||||
Bit 963674 0x00240000 1434 Block=SLICE_X29Y49 Latch=YQ Net=puente/OUT1A/PWM_in_reg<6>
|
||||
Bit 963677 0x00240000 1437 Block=SLICE_X29Y49 Latch=XQ Net=puente/OUT1A/PWM_in_reg<7>
|
||||
Bit 1019034 0x00242400 922 Block=SLICE_X30Y65 Latch=YQ Net=puente/OUT2A/PWM_in_reg<4>
|
||||
Bit 1019037 0x00242400 925 Block=SLICE_X30Y65 Latch=XQ Net=puente/OUT2A/PWM_in_reg<5>
|
||||
Bit 1019066 0x00242400 954 Block=SLICE_X30Y64 Latch=YQ Net=puente/PWM_3<6>
|
||||
Bit 1019069 0x00242400 957 Block=SLICE_X30Y64 Latch=XQ Net=puente/PWM_3<7>
|
||||
Bit 1019130 0x00242400 1018 Block=SLICE_X30Y62 Latch=YQ Net=puente/OUT2A/PWM_in_reg<0>
|
||||
Bit 1019133 0x00242400 1021 Block=SLICE_X30Y62 Latch=XQ Net=puente/OUT2A/PWM_in_reg<1>
|
||||
Bit 1019162 0x00242400 1050 Block=SLICE_X30Y61 Latch=YQ Net=puente/PWM_3<0>
|
||||
Bit 1019165 0x00242400 1053 Block=SLICE_X30Y61 Latch=XQ Net=puente/PWM_3<1>
|
||||
Bit 1019194 0x00242400 1082 Block=SLICE_X30Y60 Latch=YQ Net=puente/PWM_4<4>
|
||||
Bit 1019197 0x00242400 1085 Block=SLICE_X30Y60 Latch=XQ Net=puente/PWM_4<5>
|
||||
Bit 1019290 0x00242400 1178 Block=SLICE_X30Y57 Latch=YQ Net=puente/PWM_4<6>
|
||||
Bit 1019293 0x00242400 1181 Block=SLICE_X30Y57 Latch=XQ Net=puente/PWM_4<7>
|
||||
Bit 1019386 0x00242400 1274 Block=SLICE_X30Y54 Latch=YQ Net=puente/PWM_2<4>
|
||||
Bit 1019389 0x00242400 1277 Block=SLICE_X30Y54 Latch=XQ Net=puente/PWM_2<5>
|
||||
Bit 1019450 0x00242400 1338 Block=SLICE_X30Y52 Latch=YQ Net=puente/PWM_2<2>
|
||||
Bit 1019453 0x00242400 1341 Block=SLICE_X30Y52 Latch=XQ Net=puente/PWM_2<3>
|
||||
Bit 1019482 0x00242400 1370 Block=SLICE_X30Y51 Latch=YQ Net=puente/OUT1A/PWM_in_reg<2>
|
||||
Bit 1019485 0x00242400 1373 Block=SLICE_X30Y51 Latch=XQ Net=puente/OUT1A/PWM_in_reg<3>
|
||||
Bit 1021263 0x00260000 47 Block=P91 Latch=IQ1 Net=buffer_addr<11>
|
||||
Bit 1021288 0x00260000 72 Block=P90 Latch=IQ1 Net=buffer_addr<12>
|
||||
Bit 1022554 0x00260000 1338 Block=SLICE_X31Y52 Latch=YQ Net=enco2/quadB_delayed<1>
|
||||
Bit 1022557 0x00260000 1341 Block=SLICE_X31Y52 Latch=XQ Net=enco2/quadB_delayed<2>
|
||||
Bit 1022618 0x00260000 1402 Block=SLICE_X31Y50 Latch=YQ Net=puente/OUT1A/PWM_in_reg<4>
|
||||
Bit 1022621 0x00260000 1405 Block=SLICE_X31Y50 Latch=XQ Net=puente/OUT1A/PWM_in_reg<5>
|
||||
Bit 1022650 0x00260000 1434 Block=SLICE_X31Y49 Latch=YQ Net=puente/PWM_4<4>
|
||||
Bit 1022653 0x00260000 1437 Block=SLICE_X31Y49 Latch=XQ Net=puente/PWM_4<5>
|
||||
Bit 1022682 0x00260000 1466 Block=SLICE_X31Y48 Latch=YQ Net=puente/OUT2B/PWM_accum<7>
|
||||
Bit 1022685 0x00260000 1469 Block=SLICE_X31Y48 Latch=XQ Net=puente/OUT2B/PWM_accum<6>
|
||||
Bit 1022714 0x00260000 1498 Block=SLICE_X31Y47 Latch=YQ Net=puente/OUT2B/PWM_accum<5>
|
||||
Bit 1022717 0x00260000 1501 Block=SLICE_X31Y47 Latch=XQ Net=puente/OUT2B/PWM_accum<4>
|
||||
Bit 1022746 0x00260000 1530 Block=SLICE_X31Y46 Latch=YQ Net=puente/OUT2B/PWM_accum<3>
|
||||
Bit 1022749 0x00260000 1533 Block=SLICE_X31Y46 Latch=XQ Net=puente/OUT2B/PWM_accum<2>
|
||||
Bit 1022778 0x00260000 1562 Block=SLICE_X31Y45 Latch=YQ Net=puente/OUT2B/PWM_accum<1>
|
||||
Bit 1022781 0x00260000 1565 Block=SLICE_X31Y45 Latch=XQ Net=puente/OUT2B/PWM_accum<0>
|
||||
Bit 1022810 0x00260000 1594 Block=SLICE_X31Y44 Latch=YQ Net=puente/OUT2B/PWM_in_reg<4>
|
||||
Bit 1022813 0x00260000 1597 Block=SLICE_X31Y44 Latch=XQ Net=puente/OUT2B/PWM_in_reg<5>
|
||||
Bit 1078170 0x00262400 1082 Block=SLICE_X32Y60 Latch=YQ Net=we
|
||||
Bit 1078173 0x00262400 1085 Block=SLICE_X32Y60 Latch=XQ Net=w_st
|
||||
Bit 1078394 0x00262400 1306 Block=SLICE_X32Y53 Latch=YQ Net=puente/PWM_3<4>
|
||||
Bit 1078397 0x00262400 1309 Block=SLICE_X32Y53 Latch=XQ Net=puente/PWM_3<5>
|
||||
Bit 1078426 0x00262400 1338 Block=SLICE_X32Y52 Latch=YQ Net=puente/PWM_3<2>
|
||||
Bit 1078429 0x00262400 1341 Block=SLICE_X32Y52 Latch=XQ Net=puente/PWM_3<3>
|
||||
Bit 1078586 0x00262400 1498 Block=SLICE_X32Y47 Latch=YQ Net=puente/PWM_4<6>
|
||||
Bit 1078589 0x00262400 1501 Block=SLICE_X32Y47 Latch=XQ Net=puente/PWM_4<7>
|
||||
Bit 1022202 0x00260000 986 Block=SLICE_X31Y63 Latch=YQ Net=puente/PWM_3<4>
|
||||
Bit 1022205 0x00260000 989 Block=SLICE_X31Y63 Latch=XQ Net=puente/PWM_3<5>
|
||||
Bit 1022234 0x00260000 1018 Block=SLICE_X31Y62 Latch=YQ Net=puente/OUT2B/PWM_accum<7>
|
||||
Bit 1022237 0x00260000 1021 Block=SLICE_X31Y62 Latch=XQ Net=puente/OUT2B/PWM_accum<6>
|
||||
Bit 1022266 0x00260000 1050 Block=SLICE_X31Y61 Latch=YQ Net=puente/OUT2B/PWM_accum<5>
|
||||
Bit 1022269 0x00260000 1053 Block=SLICE_X31Y61 Latch=XQ Net=puente/OUT2B/PWM_accum<4>
|
||||
Bit 1022298 0x00260000 1082 Block=SLICE_X31Y60 Latch=YQ Net=puente/OUT2B/PWM_accum<3>
|
||||
Bit 1022301 0x00260000 1085 Block=SLICE_X31Y60 Latch=XQ Net=puente/OUT2B/PWM_accum<2>
|
||||
Bit 1022330 0x00260000 1114 Block=SLICE_X31Y59 Latch=YQ Net=puente/OUT2B/PWM_accum<1>
|
||||
Bit 1022333 0x00260000 1117 Block=SLICE_X31Y59 Latch=XQ Net=puente/OUT2B/PWM_accum<0>
|
||||
Bit 1022394 0x00260000 1178 Block=SLICE_X31Y57 Latch=YQ Net=puente/OUT1B/PWM_accum<7>
|
||||
Bit 1022397 0x00260000 1181 Block=SLICE_X31Y57 Latch=XQ Net=puente/OUT1B/PWM_accum<6>
|
||||
Bit 1022426 0x00260000 1210 Block=SLICE_X31Y56 Latch=YQ Net=puente/OUT1B/PWM_accum<5>
|
||||
Bit 1022429 0x00260000 1213 Block=SLICE_X31Y56 Latch=XQ Net=puente/OUT1B/PWM_accum<4>
|
||||
Bit 1022458 0x00260000 1242 Block=SLICE_X31Y55 Latch=YQ Net=puente/OUT1B/PWM_accum<3>
|
||||
Bit 1022461 0x00260000 1245 Block=SLICE_X31Y55 Latch=XQ Net=puente/OUT1B/PWM_accum<2>
|
||||
Bit 1022490 0x00260000 1274 Block=SLICE_X31Y54 Latch=YQ Net=puente/OUT1B/PWM_accum<1>
|
||||
Bit 1022493 0x00260000 1277 Block=SLICE_X31Y54 Latch=XQ Net=puente/OUT1B/PWM_accum<0>
|
||||
Bit 1022586 0x00260000 1370 Block=SLICE_X31Y51 Latch=YQ Net=puente/PWM_1<2>
|
||||
Bit 1022589 0x00260000 1373 Block=SLICE_X31Y51 Latch=XQ Net=puente/PWM_1<3>
|
||||
Bit 1022618 0x00260000 1402 Block=SLICE_X31Y50 Latch=YQ Net=puente/PWM_1<0>
|
||||
Bit 1022621 0x00260000 1405 Block=SLICE_X31Y50 Latch=XQ Net=puente/PWM_1<1>
|
||||
Bit 1022650 0x00260000 1434 Block=SLICE_X31Y49 Latch=YQ Net=puente/OUT1A/PWM_accum<7>
|
||||
Bit 1022653 0x00260000 1437 Block=SLICE_X31Y49 Latch=XQ Net=puente/OUT1A/PWM_accum<6>
|
||||
Bit 1022682 0x00260000 1466 Block=SLICE_X31Y48 Latch=YQ Net=puente/OUT1A/PWM_accum<5>
|
||||
Bit 1022685 0x00260000 1469 Block=SLICE_X31Y48 Latch=XQ Net=puente/OUT1A/PWM_accum<4>
|
||||
Bit 1022714 0x00260000 1498 Block=SLICE_X31Y47 Latch=YQ Net=puente/OUT1A/PWM_accum<3>
|
||||
Bit 1022717 0x00260000 1501 Block=SLICE_X31Y47 Latch=XQ Net=puente/OUT1A/PWM_accum<2>
|
||||
Bit 1022746 0x00260000 1530 Block=SLICE_X31Y46 Latch=YQ Net=puente/OUT1A/PWM_accum<1>
|
||||
Bit 1022749 0x00260000 1533 Block=SLICE_X31Y46 Latch=XQ Net=puente/OUT1A/PWM_accum<0>
|
||||
Bit 1078170 0x00262400 1082 Block=SLICE_X32Y60 Latch=YQ Net=puente/PWM_3<2>
|
||||
Bit 1078173 0x00262400 1085 Block=SLICE_X32Y60 Latch=XQ Net=puente/PWM_3<3>
|
||||
Bit 1078234 0x00262400 1146 Block=SLICE_X32Y58 Latch=YQ Net=puente/PWM_4<2>
|
||||
Bit 1078237 0x00262400 1149 Block=SLICE_X32Y58 Latch=XQ Net=puente/PWM_4<3>
|
||||
Bit 1078362 0x00262400 1274 Block=SLICE_X32Y54 Latch=YQ Net=we
|
||||
Bit 1078365 0x00262400 1277 Block=SLICE_X32Y54 Latch=XQ Net=w_st
|
||||
Bit 1078426 0x00262400 1338 Block=SLICE_X32Y52 Latch=YQ Net=puente/OUT1B/PWM_in_reg<2>
|
||||
Bit 1078429 0x00262400 1341 Block=SLICE_X32Y52 Latch=XQ Net=puente/OUT1B/PWM_in_reg<3>
|
||||
Bit 1078458 0x00262400 1370 Block=SLICE_X32Y51 Latch=YQ Net=puente/OUT1B/PWM_in_reg<6>
|
||||
Bit 1078461 0x00262400 1373 Block=SLICE_X32Y51 Latch=XQ Net=puente/OUT1B/PWM_in_reg<7>
|
||||
Bit 1078490 0x00262400 1402 Block=SLICE_X32Y50 Latch=YQ Net=puente/OUT1A/PWM_in_reg<0>
|
||||
Bit 1078493 0x00262400 1405 Block=SLICE_X32Y50 Latch=XQ Net=puente/OUT1A/PWM_in_reg<1>
|
||||
Bit 1080264 0x00280000 72 Block=P88 Latch=IQ1 Net=snwe
|
||||
Bit 1081370 0x00280000 1178 Block=SLICE_X33Y57 Latch=YQ Net=puente/OUT2A/PWM_in_reg<4>
|
||||
Bit 1081373 0x00280000 1181 Block=SLICE_X33Y57 Latch=XQ Net=puente/OUT2A/PWM_in_reg<5>
|
||||
Bit 1081466 0x00280000 1274 Block=SLICE_X33Y54 Latch=YQ Net=puente/OUT2A/PWM_accum<7>
|
||||
Bit 1081469 0x00280000 1277 Block=SLICE_X33Y54 Latch=XQ Net=puente/OUT2A/PWM_accum<6>
|
||||
Bit 1081498 0x00280000 1306 Block=SLICE_X33Y53 Latch=YQ Net=puente/OUT2A/PWM_accum<5>
|
||||
Bit 1081501 0x00280000 1309 Block=SLICE_X33Y53 Latch=XQ Net=puente/OUT2A/PWM_accum<4>
|
||||
Bit 1081530 0x00280000 1338 Block=SLICE_X33Y52 Latch=YQ Net=puente/OUT2A/PWM_accum<3>
|
||||
Bit 1081533 0x00280000 1341 Block=SLICE_X33Y52 Latch=XQ Net=puente/OUT2A/PWM_accum<2>
|
||||
Bit 1081562 0x00280000 1370 Block=SLICE_X33Y51 Latch=YQ Net=puente/OUT2A/PWM_accum<1>
|
||||
Bit 1081565 0x00280000 1373 Block=SLICE_X33Y51 Latch=XQ Net=puente/OUT2A/PWM_accum<0>
|
||||
Bit 1140442 0x002a0000 1274 Block=SLICE_X34Y54 Latch=YQ Net=puente/OUT2A/PWM_in_reg<0>
|
||||
Bit 1140445 0x002a0000 1277 Block=SLICE_X34Y54 Latch=XQ Net=puente/OUT2A/PWM_in_reg<1>
|
||||
Bit 1140538 0x002a0000 1370 Block=SLICE_X34Y51 Latch=YQ Net=puente/PWM_3<0>
|
||||
Bit 1140541 0x002a0000 1373 Block=SLICE_X34Y51 Latch=XQ Net=puente/PWM_3<1>
|
||||
Bit 1140570 0x002a0000 1402 Block=SLICE_X34Y50 Latch=YQ Net=puente/PWM_3<6>
|
||||
Bit 1140573 0x002a0000 1405 Block=SLICE_X34Y50 Latch=XQ Net=puente/PWM_3<7>
|
||||
Bit 1140762 0x002a0000 1594 Block=SLICE_X34Y44 Latch=YQ Net=puente/OUT2B/PWM_in_reg<6>
|
||||
Bit 1140765 0x002a0000 1597 Block=SLICE_X34Y44 Latch=XQ Net=puente/OUT2B/PWM_in_reg<7>
|
||||
Bit 1081114 0x00280000 922 Block=SLICE_X33Y65 Latch=YQ Net=puente/OUT2A/PWM_in_reg<2>
|
||||
Bit 1081117 0x00280000 925 Block=SLICE_X33Y65 Latch=XQ Net=puente/OUT2A/PWM_in_reg<3>
|
||||
Bit 1081146 0x00280000 954 Block=SLICE_X33Y64 Latch=YQ Net=puente/OUT2A/PWM_in_reg<6>
|
||||
Bit 1081149 0x00280000 957 Block=SLICE_X33Y64 Latch=XQ Net=puente/OUT2A/PWM_in_reg<7>
|
||||
Bit 1081178 0x00280000 986 Block=SLICE_X33Y63 Latch=YQ Net=puente/OUT2A/PWM_accum<7>
|
||||
Bit 1081181 0x00280000 989 Block=SLICE_X33Y63 Latch=XQ Net=puente/OUT2A/PWM_accum<6>
|
||||
Bit 1081210 0x00280000 1018 Block=SLICE_X33Y62 Latch=YQ Net=puente/OUT2A/PWM_accum<5>
|
||||
Bit 1081213 0x00280000 1021 Block=SLICE_X33Y62 Latch=XQ Net=puente/OUT2A/PWM_accum<4>
|
||||
Bit 1081242 0x00280000 1050 Block=SLICE_X33Y61 Latch=YQ Net=puente/OUT2A/PWM_accum<3>
|
||||
Bit 1081245 0x00280000 1053 Block=SLICE_X33Y61 Latch=XQ Net=puente/OUT2A/PWM_accum<2>
|
||||
Bit 1081274 0x00280000 1082 Block=SLICE_X33Y60 Latch=YQ Net=puente/OUT2A/PWM_accum<1>
|
||||
Bit 1081277 0x00280000 1085 Block=SLICE_X33Y60 Latch=XQ Net=puente/OUT2A/PWM_accum<0>
|
||||
Bit 1081402 0x00280000 1210 Block=SLICE_X33Y56 Latch=YQ Net=puente/OUT2B/PWM_in_reg<4>
|
||||
Bit 1081405 0x00280000 1213 Block=SLICE_X33Y56 Latch=XQ Net=puente/OUT2B/PWM_in_reg<5>
|
||||
Bit 1081690 0x00280000 1498 Block=SLICE_X33Y47 Latch=YQ Net=puente/OUT2B/PWM_in_reg<2>
|
||||
Bit 1081693 0x00280000 1501 Block=SLICE_X33Y47 Latch=XQ Net=puente/OUT2B/PWM_in_reg<3>
|
||||
Bit 1081722 0x00280000 1530 Block=SLICE_X33Y46 Latch=YQ Net=puente/OUT2B/PWM_in_reg<6>
|
||||
Bit 1081725 0x00280000 1533 Block=SLICE_X33Y46 Latch=XQ Net=puente/OUT2B/PWM_in_reg<7>
|
||||
Bit 1142344 0x002a0200 72 Block=P85 Latch=IQ1 Net=buffer_addr<10>
|
||||
Bit 1143450 0x002a0200 1178 Block=SLICE_X35Y57 Latch=YQ Net=puente/OUT2A/PWM_in_reg<6>
|
||||
Bit 1143453 0x002a0200 1181 Block=SLICE_X35Y57 Latch=XQ Net=puente/OUT2A/PWM_in_reg<7>
|
||||
Bit 1143482 0x002a0200 1210 Block=SLICE_X35Y56 Latch=YQ Net=puente/OUT2A/PWM_in_reg<2>
|
||||
Bit 1143485 0x002a0200 1213 Block=SLICE_X35Y56 Latch=XQ Net=puente/OUT2A/PWM_in_reg<3>
|
||||
Bit 1143898 0x002a0200 1626 Block=SLICE_X35Y43 Latch=YQ Net=puente/OUT2B/PWM_in_reg<0>
|
||||
Bit 1143901 0x002a0200 1629 Block=SLICE_X35Y43 Latch=XQ Net=puente/OUT2B/PWM_in_reg<1>
|
||||
Bit 1145416 0x002a0400 40 Block=P86 Latch=I Net=noe_IBUF
|
||||
Bit 1148463 0x002a0400 3087 Block=P38 Latch=I Net=clk_BUFGP/IBUFG
|
||||
Bit 1202490 0x002c0200 1242 Block=SLICE_X37Y55 Latch=YQ Net=enco2/quadA_delayed<1>
|
||||
Bit 1202493 0x002c0200 1245 Block=SLICE_X37Y55 Latch=XQ Net=enco2/quadA_delayed<2>
|
||||
Bit 1258330 0x002e0000 1210 Block=SLICE_X38Y56 Latch=YQ Net=enco2/quadB_delayed<1>
|
||||
Bit 1258333 0x002e0000 1213 Block=SLICE_X38Y56 Latch=XQ Net=enco2/quadB_delayed<2>
|
||||
Bit 1260271 0x002e0200 47 Block=P84 Latch=IQ1 Net=buffer_addr<0>
|
||||
Bit 1260296 0x002e0200 72 Block=P83 Latch=IQ1 Net=buffer_addr<1>
|
||||
Bit 1261434 0x002e0200 1210 Block=SLICE_X39Y56 Latch=YQ Net=enco2/quadA_delayed<1>
|
||||
Bit 1261437 0x002e0200 1213 Block=SLICE_X39Y56 Latch=XQ Net=enco2/quadA_delayed<2>
|
||||
Bit 1261466 0x002e0200 1242 Block=SLICE_X39Y55 Latch=YQ Net=enco1/quadB_delayed<1>
|
||||
Bit 1261469 0x002e0200 1245 Block=SLICE_X39Y55 Latch=XQ Net=enco1/quadB_delayed<2>
|
||||
Bit 1261498 0x002e0200 1274 Block=SLICE_X39Y54 Latch=YQ Net=enco1/quadA_delayed<1>
|
||||
Bit 1261501 0x002e0200 1277 Block=SLICE_X39Y54 Latch=XQ Net=enco1/quadA_delayed<2>
|
||||
Bit 1971015 0x02022400 3079 Block=P47 Latch=O2 Net=puente/OUT1B/Mcompar_PWM_out_cy<7>
|
||||
Bit 2089039 0x02027200 47 Block=P79 Latch=IQ1 Net=buffer_addr<2>
|
||||
Bit 2089064 0x02027200 72 Block=P78 Latch=IQ1 Net=buffer_addr<3>
|
||||
Bit 2147943 0x02029600 3079 Block=P49 Latch=O2 Net=puente/OUT1A/Mcompar_PWM_out_cy<7>
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sun Oct 31 14:11:59 2010
|
||||
Sun Oct 31 20:56:58 2010
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -45,7 +45,7 @@ P23||DIFFS|IO_L07N_3|UNUSED||3|||||||||
|
||||
P24||DIFFM|IO_L01P_2/CSO_B|UNUSED||2|||||||||
|
||||
P25||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
|
||||
P26||DIFFM|IO_L02P_2/DOUT/BUSY|UNUSED||2|||||||||
|
||||
P27|hbridge<1>|IOB|IO_L02N_2/MOSI/CSI_B|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P27||DIFFS|IO_L02N_2/MOSI/CSI_B|UNUSED||2|||||||||
|
||||
P28|||VCCINT||||||||1.2||||
|
||||
P29|||GND||||||||||||
|
||||
P30|reset|IBUF|IP/VREF_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
|
||||
@ -65,7 +65,7 @@ P43||DIFFM|IO_L07P_2/M0|UNUSED||2|||||||||
|
||||
P44||DIFFS|IO_L07N_2/DIN/D0|UNUSED||2|||||||||
|
||||
P45|||VCCO_2|||2|||||2.50||||
|
||||
P46|||VCCAUX||||||||2.5||||
|
||||
P47||DIFFM|IO_L08P_2/VS2|UNUSED||2|||||||||
|
||||
P47|hbridge<1>|IOB|IO_L08P_2/VS2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P48||DIFFS|IO_L08N_2/VS1|UNUSED||2|||||||||
|
||||
P49|hbridge<0>|IOB|IO_L09P_2/VS0|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P50||DIFFS|IO_L09N_2/CCLK|UNUSED||2|||||||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Release 12.2 par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
dellerwin:: Sun Oct 31 14:11:35 2010
|
||||
dellerwin:: Sun Oct 31 20:56:36 2010
|
||||
|
||||
par -w project.ncd project_r.ncd
|
||||
|
||||
@ -65,43 +65,41 @@ Total REAL time at the beginning of Placer: 2 secs
|
||||
Total CPU time at the beginning of Placer: 1 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:f088b6e2) REAL time: 3 secs
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:7a263013) REAL time: 4 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:f088b6e2) REAL time: 3 secs
|
||||
Phase 2.7 Design Feasibility Check (Checksum:7a263013) REAL time: 4 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:f088b6e2) REAL time: 3 secs
|
||||
Phase 3.31 Local Placement Optimization (Checksum:7a263013) REAL time: 4 secs
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement (Checksum:78a2ce5c) REAL time: 3 secs
|
||||
Phase 4.2 Initial Clock and IO Placement (Checksum:240478d) REAL time: 4 secs
|
||||
|
||||
Phase 5.30 Global Clock Region Assignment
|
||||
Phase 5.30 Global Clock Region Assignment (Checksum:78a2ce5c) REAL time: 3 secs
|
||||
Phase 5.30 Global Clock Region Assignment (Checksum:240478d) REAL time: 4 secs
|
||||
|
||||
Phase 6.36 Local Placement Optimization
|
||||
Phase 6.36 Local Placement Optimization (Checksum:78a2ce5c) REAL time: 3 secs
|
||||
Phase 6.36 Local Placement Optimization (Checksum:240478d) REAL time: 4 secs
|
||||
|
||||
Phase 7.8 Global Placement
|
||||
....
|
||||
......
|
||||
....
|
||||
...
|
||||
...
|
||||
Phase 7.8 Global Placement (Checksum:93fddddd) REAL time: 10 secs
|
||||
.....
|
||||
Phase 7.8 Global Placement (Checksum:15c67c8c) REAL time: 11 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:93fddddd) REAL time: 10 secs
|
||||
Phase 8.5 Local Placement Optimization (Checksum:15c67c8c) REAL time: 11 secs
|
||||
|
||||
Phase 9.18 Placement Optimization
|
||||
Phase 9.18 Placement Optimization (Checksum:b650a32c) REAL time: 11 secs
|
||||
Phase 9.18 Placement Optimization (Checksum:8caa3353) REAL time: 11 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:b650a32c) REAL time: 11 secs
|
||||
Phase 10.5 Local Placement Optimization (Checksum:8caa3353) REAL time: 11 secs
|
||||
|
||||
Total REAL time to Placer completion: 11 secs
|
||||
Total CPU time to Placer completion: 9 secs
|
||||
Total CPU time to Placer completion: 10 secs
|
||||
Writing design to file project_r.ncd
|
||||
|
||||
|
||||
@ -109,36 +107,30 @@ Writing design to file project_r.ncd
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 776 unrouted; REAL time: 16 secs
|
||||
Phase 1 : 776 unrouted; REAL time: 17 secs
|
||||
|
||||
Phase 2 : 652 unrouted; REAL time: 16 secs
|
||||
Phase 2 : 652 unrouted; REAL time: 17 secs
|
||||
|
||||
Phase 3 : 117 unrouted; REAL time: 16 secs
|
||||
Phase 3 : 136 unrouted; REAL time: 17 secs
|
||||
|
||||
Phase 4 : 153 unrouted; (Par is working to improve performance) REAL time: 17 secs
|
||||
Phase 4 : 180 unrouted; (Par is working to improve performance) REAL time: 18 secs
|
||||
|
||||
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
|
||||
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 18 secs
|
||||
|
||||
Updating file: project_r.ncd with current fully routed design.
|
||||
|
||||
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 17 secs
|
||||
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 22 secs
|
||||
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
|
||||
|
||||
Updating file: project_r.ncd with current fully routed design.
|
||||
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
|
||||
|
||||
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
|
||||
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
|
||||
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
|
||||
|
||||
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
|
||||
|
||||
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
|
||||
|
||||
Total REAL time to Router completion: 23 secs
|
||||
Total CPU time to Router completion: 22 secs
|
||||
Total REAL time to Router completion: 21 secs
|
||||
Total CPU time to Router completion: 19 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
@ -156,7 +148,7 @@ Generating Clock Report
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.075 | 0.204 |
|
||||
| clk_BUFGP | BUFGMUX_X2Y1| No | 99 | 0.086 | 0.204 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
@ -173,7 +165,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Autotimespec constraint for clock net clk | SETUP | N/A| 9.302ns| N/A| 0
|
||||
Autotimespec constraint for clock net clk | SETUP | N/A| 9.105ns| N/A| 0
|
||||
_BUFGP | HOLD | 0.968ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
@ -190,8 +182,8 @@ Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 24 secs
|
||||
Total CPU time to PAR completion: 22 secs
|
||||
Total REAL time to PAR completion: 22 secs
|
||||
Total CPU time to PAR completion: 19 secs
|
||||
|
||||
Peak Memory Usage: 357 MB
|
||||
|
||||
|
||||
@ -329,4 +329,4 @@
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.302" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="5">0</twUnmetConstCnt><twInfo anchorID="6">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
|
||||
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_BUFGP</twConstName><twConstData type="SETUP" best="9.105" units="ns" score="0"/><twConstData type="HOLD" slack="0.968" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt><twInfo anchorID="4">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
|
||||
|
||||
@ -62,8 +62,8 @@ quadA | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
|
||||
quadB | 4.665(R)| -0.790(R)|clk_BUFGP | 0.000|
|
||||
quadC | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
|
||||
quadD | 4.663(R)| -0.788(R)|clk_BUFGP | 0.000|
|
||||
reset | 3.422(R)| -0.258(R)|clk_BUFGP | 0.000|
|
||||
| 3.958(F)| -0.175(F)|clk_BUFGP | 0.000|
|
||||
reset | 3.336(R)| -0.369(R)|clk_BUFGP | 0.000|
|
||||
| 4.315(F)| -0.589(F)|clk_BUFGP | 0.000|
|
||||
sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
|
||||
@ -79,22 +79,22 @@ Clock clk to Pad
|
||||
| clk (edge) | | Clock |
|
||||
Destination | to PAD |Internal Clock(s) | Phase |
|
||||
------------+------------+------------------+--------+
|
||||
hbridge<0> | 12.986(R)|clk_BUFGP | 0.000|
|
||||
| 12.791(F)|clk_BUFGP | 0.000|
|
||||
hbridge<1> | 12.097(R)|clk_BUFGP | 0.000|
|
||||
| 12.323(F)|clk_BUFGP | 0.000|
|
||||
hbridge<2> | 12.361(R)|clk_BUFGP | 0.000|
|
||||
| 12.576(F)|clk_BUFGP | 0.000|
|
||||
hbridge<3> | 12.249(R)|clk_BUFGP | 0.000|
|
||||
| 12.533(F)|clk_BUFGP | 0.000|
|
||||
sram_data<0>| 13.558(F)|clk_BUFGP | 0.000|
|
||||
sram_data<1>| 13.456(F)|clk_BUFGP | 0.000|
|
||||
sram_data<2>| 13.303(F)|clk_BUFGP | 0.000|
|
||||
sram_data<3>| 13.306(F)|clk_BUFGP | 0.000|
|
||||
sram_data<4>| 13.100(F)|clk_BUFGP | 0.000|
|
||||
sram_data<5>| 12.982(F)|clk_BUFGP | 0.000|
|
||||
sram_data<6>| 13.549(F)|clk_BUFGP | 0.000|
|
||||
sram_data<7>| 14.331(F)|clk_BUFGP | 0.000|
|
||||
hbridge<0> | 12.564(R)|clk_BUFGP | 0.000|
|
||||
| 12.481(F)|clk_BUFGP | 0.000|
|
||||
hbridge<1> | 12.901(R)|clk_BUFGP | 0.000|
|
||||
| 12.921(F)|clk_BUFGP | 0.000|
|
||||
hbridge<2> | 12.713(R)|clk_BUFGP | 0.000|
|
||||
| 12.377(F)|clk_BUFGP | 0.000|
|
||||
hbridge<3> | 13.541(R)|clk_BUFGP | 0.000|
|
||||
| 13.383(F)|clk_BUFGP | 0.000|
|
||||
sram_data<0>| 13.296(F)|clk_BUFGP | 0.000|
|
||||
sram_data<1>| 13.038(F)|clk_BUFGP | 0.000|
|
||||
sram_data<2>| 12.986(F)|clk_BUFGP | 0.000|
|
||||
sram_data<3>| 13.246(F)|clk_BUFGP | 0.000|
|
||||
sram_data<4>| 13.147(F)|clk_BUFGP | 0.000|
|
||||
sram_data<5>| 12.926(F)|clk_BUFGP | 0.000|
|
||||
sram_data<6>| 13.450(F)|clk_BUFGP | 0.000|
|
||||
sram_data<7>| 13.381(F)|clk_BUFGP | 0.000|
|
||||
------------+------------+------------------+--------+
|
||||
|
||||
Clock to Setup on destination clock clk
|
||||
@ -102,33 +102,33 @@ Clock to Setup on destination clock clk
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
clk | 5.484| 4.651| 4.353| 8.989|
|
||||
clk | 6.132| 4.553| 3.790| 9.078|
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
Pad to Pad
|
||||
---------------+---------------+---------+
|
||||
Source Pad |Destination Pad| Delay |
|
||||
---------------+---------------+---------+
|
||||
ncs |sram_data<0> | 9.401|
|
||||
ncs |sram_data<1> | 9.145|
|
||||
ncs |sram_data<2> | 9.411|
|
||||
ncs |sram_data<3> | 9.425|
|
||||
ncs |sram_data<4> | 9.674|
|
||||
ncs |sram_data<5> | 9.658|
|
||||
ncs |sram_data<6> | 11.147|
|
||||
ncs |sram_data<7> | 11.413|
|
||||
noe |sram_data<0> | 9.064|
|
||||
noe |sram_data<1> | 8.808|
|
||||
noe |sram_data<2> | 9.074|
|
||||
noe |sram_data<3> | 9.088|
|
||||
noe |sram_data<4> | 9.337|
|
||||
noe |sram_data<5> | 9.321|
|
||||
noe |sram_data<6> | 10.810|
|
||||
noe |sram_data<7> | 11.076|
|
||||
ncs |sram_data<0> | 10.289|
|
||||
ncs |sram_data<1> | 10.543|
|
||||
ncs |sram_data<2> | 10.539|
|
||||
ncs |sram_data<3> | 10.091|
|
||||
ncs |sram_data<4> | 9.970|
|
||||
ncs |sram_data<5> | 10.339|
|
||||
ncs |sram_data<6> | 9.761|
|
||||
ncs |sram_data<7> | 10.018|
|
||||
noe |sram_data<0> | 8.488|
|
||||
noe |sram_data<1> | 8.742|
|
||||
noe |sram_data<2> | 8.738|
|
||||
noe |sram_data<3> | 8.290|
|
||||
noe |sram_data<4> | 8.169|
|
||||
noe |sram_data<5> | 8.538|
|
||||
noe |sram_data<6> | 7.960|
|
||||
noe |sram_data<7> | 8.217|
|
||||
---------------+---------------+---------+
|
||||
|
||||
|
||||
Analysis completed Sun Oct 31 14:12:02 2010
|
||||
Analysis completed Sun Oct 31 20:57:02 2010
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -1,7 +1,7 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sun Oct 31 14:11:59 2010
|
||||
Sun Oct 31 20:56:59 2010
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#Release 12.2 - par M.63c (lin64)
|
||||
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Sun Oct 31 14:11:59 2010
|
||||
#Sun Oct 31 20:56:58 2010
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
@ -45,7 +45,7 @@ P23,,DIFFS,IO_L07N_3,UNUSED,,3,,,,,,,,,
|
||||
P24,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,,
|
||||
P25,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,,
|
||||
P26,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,,
|
||||
P27,hbridge<1>,IOB,IO_L02N_2/MOSI/CSI_B,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P27,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,,
|
||||
P28,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P29,,,GND,,,,,,,,,,,,
|
||||
P30,reset,IBUF,IP/VREF_2,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
|
||||
@ -65,7 +65,7 @@ P43,,DIFFM,IO_L07P_2/M0,UNUSED,,2,,,,,,,,,
|
||||
P44,,DIFFS,IO_L07N_2/DIN/D0,UNUSED,,2,,,,,,,,,
|
||||
P45,,,VCCO_2,,,2,,,,,2.50,,,,
|
||||
P46,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P47,,DIFFM,IO_L08P_2/VS2,UNUSED,,2,,,,,,,,,
|
||||
P47,hbridge<1>,IOB,IO_L08P_2/VS2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P48,,DIFFS,IO_L08N_2/VS1,UNUSED,,2,,,,,,,,,
|
||||
P49,hbridge<0>,IOB,IO_L09P_2/VS0,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P50,,DIFFS,IO_L09N_2/CCLK,UNUSED,,2,,,,,,,,,
|
||||
|
||||
|
@ -1,7 +1,7 @@
|
||||
Release 12.2 - par M.63c (lin64)
|
||||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Sun Oct 31 14:11:59 2010
|
||||
Sun Oct 31 20:56:59 2010
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
@ -46,7 +46,7 @@ Pinout by Pin Number:
|
||||
|P24 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|
||||
|P25 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|
||||
|P26 | |DIFFM |IO_L02P_2/DOUT/BUSY |UNUSED | |2 | | | | | | | | |
|
||||
|P27 |hbridge<1> |IOB |IO_L02N_2/MOSI/CSI_B |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P27 | |DIFFS |IO_L02N_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|
||||
|P28 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P29 | | |GND | | | | | | | | | | | |
|
||||
|P30 |reset |IBUF |IP/VREF_2 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|
||||
@ -66,7 +66,7 @@ Pinout by Pin Number:
|
||||
|P44 | |DIFFS |IO_L07N_2/DIN/D0 |UNUSED | |2 | | | | | | | | |
|
||||
|P45 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|
||||
|P46 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P47 | |DIFFM |IO_L08P_2/VS2 |UNUSED | |2 | | | | | | | | |
|
||||
|P47 |hbridge<1> |IOB |IO_L08P_2/VS2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P48 | |DIFFS |IO_L08N_2/VS1 |UNUSED | |2 | | | | | | | | |
|
||||
|P49 |hbridge<0> |IOB |IO_L09P_2/VS0 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P50 | |DIFFS |IO_L09N_2/CCLK |UNUSED | |2 | | | | | | | | |
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DeviceUsageSummary rev="2">
|
||||
<DesignStatistics TimeStamp="Sun Oct 31 14:12:09 2010"><group name="NetStatistics">
|
||||
<DesignStatistics TimeStamp="Sun Oct 31 20:57:09 2010"><group name="NetStatistics">
|
||||
<item name="NumNets_Active" rev="2">
|
||||
<attrib name="value" value="311"/></item>
|
||||
<item name="NumNets_Gnd" rev="2">
|
||||
@ -21,55 +21,51 @@
|
||||
<item name="NumNodesOfType_Active_CNTRLPIN" rev="2">
|
||||
<attrib name="value" value="71"/></item>
|
||||
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
|
||||
<attrib name="value" value="730"/></item>
|
||||
<attrib name="value" value="712"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMY" rev="2">
|
||||
<attrib name="value" value="359"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMYBANK" rev="2">
|
||||
<attrib name="value" value="50"/></item>
|
||||
<attrib name="value" value="56"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMYESC" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
|
||||
<attrib name="value" value="51"/></item>
|
||||
<attrib name="value" value="42"/></item>
|
||||
<item name="NumNodesOfType_Active_HFULLHEX" rev="2">
|
||||
<attrib name="value" value="10"/></item>
|
||||
<item name="NumNodesOfType_Active_HLONG" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="NumNodesOfType_Active_HUNIHEX" rev="2">
|
||||
<attrib name="value" value="98"/></item>
|
||||
<attrib name="value" value="93"/></item>
|
||||
<item name="NumNodesOfType_Active_INPUT" rev="2">
|
||||
<attrib name="value" value="590"/></item>
|
||||
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
|
||||
<attrib name="value" value="31"/></item>
|
||||
<item name="NumNodesOfType_Active_OMUX" rev="2">
|
||||
<attrib name="value" value="290"/></item>
|
||||
<attrib name="value" value="273"/></item>
|
||||
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
|
||||
<attrib name="value" value="218"/></item>
|
||||
<item name="NumNodesOfType_Active_PREBXBY" rev="2">
|
||||
<attrib name="value" value="220"/></item>
|
||||
<attrib name="value" value="207"/></item>
|
||||
<item name="NumNodesOfType_Active_VFULLHEX" rev="2">
|
||||
<attrib name="value" value="32"/></item>
|
||||
<attrib name="value" value="41"/></item>
|
||||
<item name="NumNodesOfType_Active_VLONG" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="NumNodesOfType_Active_VUNIHEX" rev="2">
|
||||
<attrib name="value" value="64"/></item>
|
||||
<attrib name="value" value="74"/></item>
|
||||
<item name="NumNodesOfType_Gnd_BRAMADDR" rev="2">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="NumNodesOfType_Gnd_BRAMDUMMY" rev="2">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="NumNodesOfType_Gnd_DOUBLE" rev="2">
|
||||
<attrib name="value" value="16"/></item>
|
||||
<attrib name="value" value="21"/></item>
|
||||
<item name="NumNodesOfType_Gnd_DUMMYBANK" rev="2">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Gnd_INPUT" rev="2">
|
||||
<attrib name="value" value="38"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OMUX" rev="2">
|
||||
<attrib name="value" value="14"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OUTPUT" rev="2">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="NumNodesOfType_Gnd_PREBXBY" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="NumNodesOfType_Gnd_VFULLHEX" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Gnd_PREBXBY" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<item name="NumNodesOfType_Vcc_BRAMDUMMY" rev="2">
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="2">
|
||||
@ -93,11 +89,11 @@
|
||||
<item name="IBUF-IOB" rev="2">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="IOB-DIFFM" rev="2">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="IOB-DIFFS" rev="2">
|
||||
<attrib name="value" value="5"/></item>
|
||||
<attrib name="value" value="4"/></item>
|
||||
<item name="SLICEL-SLICEM" rev="2">
|
||||
<attrib name="value" value="42"/></item>
|
||||
<attrib name="value" value="41"/></item>
|
||||
</group>
|
||||
<group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="1">
|
||||
@ -130,7 +126,7 @@
|
||||
<attrib name="value" value="48"/></item>
|
||||
</group>
|
||||
</DesignStatistics>
|
||||
<DeviceUsage TimeStamp="Sun Oct 31 14:12:09 2010"><group name="SiteSummary">
|
||||
<DeviceUsage TimeStamp="Sun Oct 31 20:57:09 2010"><group name="SiteSummary">
|
||||
<item name="BUFGMUX" rev="2">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="BUFGMUX_GCLKMUX" rev="2">
|
||||
@ -195,7 +191,7 @@
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="24"/></item>
|
||||
</group>
|
||||
</DeviceUsage>
|
||||
<ReportConfigData TimeStamp="Sun Oct 31 14:12:09 2010"><group name="SLICEL_CYMUXF">
|
||||
<ReportConfigData TimeStamp="Sun Oct 31 20:57:09 2010"><group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="0" value="40"/><attrib name="0_INV" value="0"/></item>
|
||||
<item name="1" rev="2">
|
||||
@ -374,7 +370,7 @@
|
||||
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
|
||||
</group>
|
||||
</ReportConfigData>
|
||||
<ReportPinData TimeStamp="Sun Oct 31 14:12:09 2010"><group name="SLICEL_CYMUXF">
|
||||
<ReportPinData TimeStamp="Sun Oct 31 20:57:09 2010"><group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="2">
|
||||
<attrib name="value" value="40"/></item>
|
||||
<item name="1" rev="2">
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
|
||||
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">9f5f0d2df28148bcb47e901093f9d1d1</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">be534f09916d4e59b80fec647873aecc</xtag-property>.<xtag-property name="ProjectIteration">1</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
|
||||
<TD><xtag-property name="TargetPackage">vq100</xtag-property></TD>
|
||||
</TR>
|
||||
@ -29,7 +29,7 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
|
||||
<TD><xtag-property name="Date Generated">2010-10-31T14:12:09</xtag-property></TD>
|
||||
<TD><xtag-property name="Date Generated">2010-10-31T20:57:09</xtag-property></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
|
||||
<TD><xtag-property name="ToolFlow">CommandLine</xtag-property></TD>
|
||||
</TR>
|
||||
@ -85,31 +85,29 @@
|
||||
<LI><xtag-item1>NumNodesOfType_Active_BRAMDUMMY=70</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=99</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=71</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=730</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=712</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMY=359</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=50</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMYBANK=56</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_DUMMYESC=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=51</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=10</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HLONG=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=98</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=42</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HFULLHEX=15</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_HUNIHEX=93</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_INPUT=590</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=31</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_OMUX=290</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_OMUX=273</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=218</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=220</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=32</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VLONG=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=64</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_PREBXBY=207</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VFULLHEX=41</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VLONG=3</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Active_VUNIHEX=74</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMADDR=22</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_BRAMDUMMY=12</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=16</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=6</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DOUBLE=21</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_DUMMYBANK=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_INPUT=38</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_OMUX=14</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_VFULLHEX=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_OUTPUT=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Gnd_PREBXBY=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_BRAMDUMMY=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>NumNodesOfType_Vcc_INPUT=9</xtag-item1></LI>
|
||||
@ -124,9 +122,9 @@
|
||||
<LI><xtag-item1>IBUF-DIFFS=9</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-DIFFSI=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>IBUF-IOB=1</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFM=7</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFS=5</xtag-item1></LI>
|
||||
<LI><xtag-item1>SLICEL-SLICEM=42</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFM=8</xtag-item1></LI>
|
||||
<LI><xtag-item1>IOB-DIFFS=4</xtag-item1></LI>
|
||||
<LI><xtag-item1>SLICEL-SLICEM=41</xtag-item1></LI>
|
||||
</UL>
|
||||
</xtag-group>
|
||||
</TD>
|
||||
@ -696,8 +694,8 @@
|
||||
<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
|
||||
<tr>
|
||||
<td><xtag-program-name>bitgen</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>93</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>93</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>94</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>94</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
@ -706,8 +704,8 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>map</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>116</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>112</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>117</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>113</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
@ -716,8 +714,8 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>120</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>120</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>121</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>121</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
@ -726,8 +724,8 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>par</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>111</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>112</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>112</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
@ -736,8 +734,8 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>trce</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>111</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>112</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>112</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
@ -746,8 +744,8 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td><xtag-program-name>xst</xtag-program-name></td>
|
||||
<td><xtag-total-run-started>213</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>210</xtag-total-run-finished></td>
|
||||
<td><xtag-total-run-started>214</xtag-total-run-started></td>
|
||||
<td><xtag-total-run-finished>211</xtag-total-run-finished></td>
|
||||
<td><xtag-total-error>0</xtag-total-error></td>
|
||||
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
|
||||
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
|
||||
|
||||
@ -3,7 +3,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Project Information
|
||||
--------------------
|
||||
ProjectID=9f5f0d2df28148bcb47e901093f9d1d1
|
||||
ProjectID=be534f09916d4e59b80fec647873aecc
|
||||
ProjectIteration=2
|
||||
|
||||
WebTalk Summary
|
||||
|
||||
Binary file not shown.
@ -1,4 +1,4 @@
|
||||
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288551148
|
||||
MO beta NULL ../beta.v vlg5C/beta.bin 1288551148
|
||||
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288551148
|
||||
MO enco NULL ../enco.v vlg6D/enco.bin 1288551148
|
||||
MO PWM NULL ../PWM.v vlg50/_p_w_m.bin 1288576575
|
||||
MO beta NULL ../beta.v vlg5C/beta.bin 1288576575
|
||||
MO PuenteH NULL ../PuenteH.v vlg69/_puente_h.bin 1288576575
|
||||
MO enco NULL ../enco.v vlg6D/enco.bin 1288576575
|
||||
|
||||
Loading…
Reference in New Issue
Block a user