Uploaded the first Beta to test in the development group

2025-04-21 12:27:27 +03:00 · 2010-10-30 18:34:22 -05:00
parent 0a65a50cff
commit 8f2a9cc1d6
68 changed files with 62913 additions and 0 deletions
--- a/Examples/Beta1/logic/bb.v
+++ b/Examples/Beta1/logic/bb.v
@@ -0,0 +1,108 @@
+`timescale 1ns / 1ps
+
+module pwm_FINAL(clk, reset, enable, we, PWM_in, PWM_out,buffer_addr,out);
+input clk;					//Clock
+input enable;				//Seal enable
+input we;					//Seal enable de escritura
+input reset;				//Seal reset
+input [7:0] PWM_in;		//Dutycycle
+input [10:0]buffer_addr;			//Direcciones ram
+output PWM_out;			//Salida PWM
+output [10:0]out;
+
+reg [7:0] PWM_accum=0;	//Acumulador PWM
+reg [7:0] PWM_in_reg=0;	//Registro para saber cambios en registro de RAM
+//reg [7:0] PWM_in_reg2=0;	//Registro para saber cambios en registro de RAM
+reg we1=0;				//registro write enable?
+wire [7:0] PWM_ram_reg;	//Registro que se lee desde la ram
+
+/*always @(negedge clk)//sync de addres. Por ahora lleva todo a la primera direccion
+begin
+	if(enable&we)	
+	 begin	
+	 PWM_in_reg<=PWM_in;
+	 PWM_in_reg2<=PWM_in_reg;
+	 end
+end
+*/
+    // REGISTER BANK:   Write control
+    always @(negedge clk)
+    begin
+        /*if(reset) 
+            {PWM_in_reg,we1} <= 0;
+        else */if(we & enable) begin
+            /*case (buffer_addr)   
+                    0: begin PWM_in_reg<=PWM_in;      end
+                    1: begin PWM_in_reg<=PWM_in;      end
+                    2: begin PWM_in_reg<=PWM_in; end            
+              default: begin we1 <= 1; end    
+            endcase */
+				we1<=1;
+        end 
+        else begin 
+            we1 <= 0; end 
+    end   
+	 
+/*always @(posedge clk)//Manejo de escritura RAM??
+begin
+//	if(reset) {PWM_accum, PWM_in_reg} <= 0;
+//	else if(enable) 
+//		begin
+//		PWM_ram_reg<=PWM_in;
+//		PWM_in_reg<=PWM_in;
+//		end
+       if(enable)
+begin
+		 case (state)   
+                    0: begin 
+						  PWM_in_reg<=PWM_in;
+						  state <= 1;      end
+                    1: begin state <= 1;      end
+              default: begin state <= 0; end  
+				endcase
+end
+end
+
+*/
+always @(posedge clk)//Manejo de escritura RAM??
+begin
+	PWM_in_reg<=PWM_ram_reg;
+	if(PWM_in_reg==PWM_ram_reg)	PWM_accum<=PWM_accum+1; else PWM_accum<=0;
+  //PWM_accum<=PWM_accum+1;
+end
+/*RAMB16_S9 ba0( .CLK(~clk), 
+			.EN(enable),
+			.DOP(),
+			.SSR(1'b0), 
+			.ADDR(buffer_addr[10:0]), 
+			.WE(we1), 
+			.DI(PWM_in),
+			.DIP(1'b0), 
+			.DO(out));
+*/
+    // Dual-port RAM instatiation
+    RAMB16_S9_S9 ba0(
+            .DOA(out),         // Port A 8-bit Data Output
+            .DOB(PWM_ram_reg),     // Port B 8-bit Data Output
+            .DOPA(),              // Port A 1-bit Parity Output
+            .DOPB(),              // Port B 1-bit Parity Output
+            .ADDRA(buffer_addr[10:0]),   // Port A 11-bit Address Input
+            .ADDRB(1'b0),  // Port B 11-bit Address Input
+            .CLKA(~clk),          // Port A Clock
+            .CLKB(~clk),          // Port B Clock
+            .DIA(PWM_in),     // Port A 8-bit Data Input
+            .DIB(),    // Port B 8-bit Data Input
+            .DIPA(1'b0),          // Port A 1-bit parity Input
+            .DIPB(1'b0),          // Port-B 1-bit parity Input
+            .ENA(1'b1),           // Port A RAM Enable Input
+            .ENB(1'b1),           // Port B RAM Enable Input
+            .SSRA(1'b0),          // Port A Synchronous Set/Reset Input
+            .SSRB(1'b0),          // Port B Synchronous Set/Reset Input
+            .WEA(we1),            // Port A Write Enable Input
+            .WEB(1'b0) );          // Port B Write Enable Input 
+//Salida para el PWM
+
+assign PWM_out=(PWM_accum<PWM_ram_reg);
+
+
+endmodule