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108 lines
3.3 KiB
Verilog
108 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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module pwm_FINAL(clk, reset, enable, we, PWM_in, PWM_out,buffer_addr,out);
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input clk; //Clock
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input enable; //Seal enable
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input we; //Seal enable de escritura
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input reset; //Seal reset
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input [7:0] PWM_in; //Dutycycle
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input [10:0]buffer_addr; //Direcciones ram
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output PWM_out; //Salida PWM
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output [10:0]out;
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reg [7:0] PWM_accum=0; //Acumulador PWM
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reg [7:0] PWM_in_reg=0; //Registro para saber cambios en registro de RAM
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//reg [7:0] PWM_in_reg2=0; //Registro para saber cambios en registro de RAM
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reg we1=0; //registro write enable?
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wire [7:0] PWM_ram_reg; //Registro que se lee desde la ram
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/*always @(negedge clk)//sync de addres. Por ahora lleva todo a la primera direccion
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begin
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if(enable&we)
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begin
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PWM_in_reg<=PWM_in;
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PWM_in_reg2<=PWM_in_reg;
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end
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end
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*/
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// REGISTER BANK: Write control
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always @(negedge clk)
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begin
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/*if(reset)
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{PWM_in_reg,we1} <= 0;
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else */if(we & enable) begin
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/*case (buffer_addr)
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0: begin PWM_in_reg<=PWM_in; end
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1: begin PWM_in_reg<=PWM_in; end
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2: begin PWM_in_reg<=PWM_in; end
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default: begin we1 <= 1; end
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endcase */
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we1<=1;
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end
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else begin
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we1 <= 0; end
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end
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/*always @(posedge clk)//Manejo de escritura RAM??
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begin
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// if(reset) {PWM_accum, PWM_in_reg} <= 0;
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// else if(enable)
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// begin
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// PWM_ram_reg<=PWM_in;
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// PWM_in_reg<=PWM_in;
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// end
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if(enable)
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begin
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case (state)
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0: begin
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PWM_in_reg<=PWM_in;
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state <= 1; end
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1: begin state <= 1; end
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default: begin state <= 0; end
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endcase
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end
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end
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*/
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always @(posedge clk)//Manejo de escritura RAM??
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begin
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PWM_in_reg<=PWM_ram_reg;
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if(PWM_in_reg==PWM_ram_reg) PWM_accum<=PWM_accum+1; else PWM_accum<=0;
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//PWM_accum<=PWM_accum+1;
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end
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/*RAMB16_S9 ba0( .CLK(~clk),
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.EN(enable),
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.DOP(),
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.SSR(1'b0),
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.ADDR(buffer_addr[10:0]),
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.WE(we1),
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.DI(PWM_in),
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.DIP(1'b0),
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.DO(out));
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*/
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// Dual-port RAM instatiation
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RAMB16_S9_S9 ba0(
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.DOA(out), // Port A 8-bit Data Output
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.DOB(PWM_ram_reg), // Port B 8-bit Data Output
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.DOPA(), // Port A 1-bit Parity Output
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.DOPB(), // Port B 1-bit Parity Output
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.ADDRA(buffer_addr[10:0]), // Port A 11-bit Address Input
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.ADDRB(1'b0), // Port B 11-bit Address Input
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.CLKA(~clk), // Port A Clock
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.CLKB(~clk), // Port B Clock
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.DIA(PWM_in), // Port A 8-bit Data Input
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.DIB(), // Port B 8-bit Data Input
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.DIPA(1'b0), // Port A 1-bit parity Input
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.DIPB(1'b0), // Port-B 1-bit parity Input
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.ENA(1'b1), // Port A RAM Enable Input
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.ENB(1'b1), // Port B RAM Enable Input
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.SSRA(1'b0), // Port A Synchronous Set/Reset Input
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.SSRB(1'b0), // Port B Synchronous Set/Reset Input
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.WEA(we1), // Port A Write Enable Input
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.WEB(1'b0) ); // Port B Write Enable Input
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//Salida para el PWM
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assign PWM_out=(PWM_accum<PWM_ram_reg);
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endmodule |