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03456560f3
sie-ceimtun/Examples/Beta1/logic/build/project_r.twr
Erwin Lopez 03456560f3 Pins corrected again
2010-10-31 14:13:54 -05:00

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--------------------------------------------------------------------------------
Release 12.2 Trace (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 25
project_r.ncd project.pcf
Design file: project_r.ncd
Physical constraint file: project.pcf
Device,package,speed: xc3s500e,vq100,-4 (PRODUCTION 1.27 2010-06-22)
Report level: verbose report, limited to 25 items per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
|Max Setup to|Max Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
addr<0> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
addr<1> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
addr<2> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
addr<3> | 4.652(F)| -0.775(F)|clk_BUFGP | 0.000|
addr<4> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
addr<5> | 4.648(F)| -0.771(F)|clk_BUFGP | 0.000|
addr<6> | 4.650(F)| -0.772(F)|clk_BUFGP | 0.000|
addr<7> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
addr<8> | 4.693(F)| -0.823(F)|clk_BUFGP | 0.000|
addr<9> | 4.669(F)| -0.795(F)|clk_BUFGP | 0.000|
addr<10> | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
addr<11> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
addr<12> | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
ncs | 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
nwe | 4.666(F)| -0.791(F)|clk_BUFGP | 0.000|
quadA | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
quadB | 4.665(R)| -0.790(R)|clk_BUFGP | 0.000|
quadC | 4.669(R)| -0.795(R)|clk_BUFGP | 0.000|
quadD | 4.663(R)| -0.788(R)|clk_BUFGP | 0.000|
reset | 3.422(R)| -0.258(R)|clk_BUFGP | 0.000|
| 3.958(F)| -0.175(F)|clk_BUFGP | 0.000|
sram_data<0>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<1>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<2>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<3>| 4.664(F)| -0.789(F)|clk_BUFGP | 0.000|
sram_data<4>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
sram_data<5>| 4.667(F)| -0.792(F)|clk_BUFGP | 0.000|
sram_data<6>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
sram_data<7>| 4.651(F)| -0.774(F)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
hbridge<0> | 12.986(R)|clk_BUFGP | 0.000|
| 12.791(F)|clk_BUFGP | 0.000|
hbridge<1> | 12.097(R)|clk_BUFGP | 0.000|
| 12.323(F)|clk_BUFGP | 0.000|
hbridge<2> | 12.361(R)|clk_BUFGP | 0.000|
| 12.576(F)|clk_BUFGP | 0.000|
hbridge<3> | 12.249(R)|clk_BUFGP | 0.000|
| 12.533(F)|clk_BUFGP | 0.000|
sram_data<0>| 13.558(F)|clk_BUFGP | 0.000|
sram_data<1>| 13.456(F)|clk_BUFGP | 0.000|
sram_data<2>| 13.303(F)|clk_BUFGP | 0.000|
sram_data<3>| 13.306(F)|clk_BUFGP | 0.000|
sram_data<4>| 13.100(F)|clk_BUFGP | 0.000|
sram_data<5>| 12.982(F)|clk_BUFGP | 0.000|
sram_data<6>| 13.549(F)|clk_BUFGP | 0.000|
sram_data<7>| 14.331(F)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 5.484| 4.651| 4.353| 8.989|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
ncs |sram_data<0> | 9.401|
ncs |sram_data<1> | 9.145|
ncs |sram_data<2> | 9.411|
ncs |sram_data<3> | 9.425|
ncs |sram_data<4> | 9.674|
ncs |sram_data<5> | 9.658|
ncs |sram_data<6> | 11.147|
ncs |sram_data<7> | 11.413|
noe |sram_data<0> | 9.064|
noe |sram_data<1> | 8.808|
noe |sram_data<2> | 9.074|
noe |sram_data<3> | 9.088|
noe |sram_data<4> | 9.337|
noe |sram_data<5> | 9.321|
noe |sram_data<6> | 10.810|
noe |sram_data<7> | 11.076|
---------------+---------------+---------+
Analysis completed Sun Oct 31 14:12:02 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 239 MB
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