m1/case/: added rear panel with JTAG hole

m1/case/doit

@@ -14,6 +14,9 @@ PATH=$PATH:/home/qi/cae-tools/gp2rml
 # CLEARANCE	tool clearance above PCB surface, default: 2mm
 #
 
+NAME=$1
+shift
+
 while [ "$1" ]; do
     eval "$1"
     shift
@@ -34,7 +37,7 @@ while [ $yi -lt $YN ]; do
 
 	cat <<EOF >_job
 mm
-gnuplot $MILL case.gp
+gnuplot $MILL $NAME.gp
 
 align 1 $X0 $Y0		# align relative to board corner
 translate 4mm 4mm	# move to PCB zone assigned to project
@@ -42,9 +45,8 @@ array +3mm +3mm `expr $X + $xi` `expr $Y + $yi`
 z 0 $Z0			# board surface (tool fully retracted)
 z -$BOARD_Z		# board thickness
 
-write merged.gp
 offset
-write mill.gp
+write _$NAME.gp
 EOF
 
 	cameo _job || exit
@@ -56,4 +58,4 @@ EOF
     yi=`expr $yi + 1`
 done
 
-gp2rml $CLEARANCE 10 10 mill.gp >mill.rml || exit
+gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit