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m1/case/: added rear panel with JTAG hole
This commit is contained in:
Werner Almesberger
parent
f1af1b8181
commit
054df9f90e
@ -1,19 +1,33 @@
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SPOOL=/home/moko/svn.openmoko.org/developers/werner/cncmap/spool/spool
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CNGT=/home/qi/cae-tools/cngt/cngt
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BOARD=X0=5.0mm Y0=0.0mm Z0=-56.0mm BOARD_Z=4mm
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Z0=-55.0
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BOARD=X0=5.0mm Y0=0.0mm Z0=$(Z0)mm BOARD_Z=4.5mm
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TASK=Y=1
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.PHONY: all mill clean
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.PHONY: all front rear cng clean
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all: mill.rml
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all: front.rml rear.rml
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case.gp: case.fpd
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fped -g $<
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front.gp: case.fpd
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fped -g -1 M1-front $< $@
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mill.rml: case.gp
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./doit $(BOARD) CLEARANCE=5mm || { rm -f $@; exit 1; }
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rear.gp: case.fpd
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fped -g -1 M1-rear $< $@
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mill: mill.rml
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PORT=/dev/ttyUSB0 $(SPOOL) mill.rml
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%.rml: %.gp
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./doit `basename $< .gp` $(BOARD) $(TASK) CLEARANCE=5mm || \
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{ rm -f $@; exit 1; }
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front: front.rml
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PORT=/dev/ttyUSB0 $(SPOOL) $<
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rear: rear.rml
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PORT=/dev/ttyUSB0 $(SPOOL) $<
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cng: front.gp
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$(CNGT) $(Z0) 20 front.gp
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clean:
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rm -f case.gp mill.gp mill.rml
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rm -f front.gp _front.gp front.rml
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rm -f rear.gp _rear.gp rear.rml
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22
m1/case/README
Normal file
22
m1/case/README
Normal file
@ -0,0 +1,22 @@
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Reengineered M1 case parts
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==========================
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case.fpd contains an fped-based design of the front and rear panel.
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The geometry is based on
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http://projects.qi-hardware.com/index.php/p/m1/source/tree/master/cad/protocase_v7_laser.dxf
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by Joachim Steiger.
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This design is fully parametrized and contains the following changes:
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- the holes for the USB sockets are raised by 1.4 mm, for the M1pre-rc4
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prototype (parameter Iusby):
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http://en.qi-hardware.com/wiki/File:M1pre-rc4-u-A022.JPG
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- additional hole in the rear panel for a mini-USB cable going to
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the JTAG board (parameters Idbgx and Idbgy, with frame "debug")
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Known issues:
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- button holes are a bit too tight
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- DC connector hole is too tight on all sides
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@ -58,10 +58,79 @@ frame short {
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line . __19 w
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}
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frame usb {
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set Wusb = 8.5mm
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frame debug {
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table
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{ Wdbg, Hdbg }
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{ 14.5mm, 9.5mm }
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set Husb = 15.5mm
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__0: vec @(Wdbg, Hdbg)
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rect @ . w
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}
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frame dc {
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table
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{ Wdc, Hdc }
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{ 9.4mm, 11.4mm }
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__0: vec @(-Wdc, Hdc)
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rect @ . w
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}
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frame ether {
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table
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{ Weth, Heth }
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{ 16.5mm, 14mm }
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__0: vec @(Weth, Heth)
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rect @ . w
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}
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frame rgb {
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set Rrgb = 6.3mm
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__0: vec @(0mm, Rrgb)
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circ @ . w
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}
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frame rear {
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table
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{ Irgbx, Irgby, Drgb }
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{ 25.5mm, 14.5mm, 15mm }
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table
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{ Iethx, Iethy }
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{ 67mm, 7mm }
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table
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{ Idcx, Idcy }
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{ 14.8mm, 6.6mm }
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table
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{ Idbgx, Idbgy }
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{ 88.1mm, 14.5mm }
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loop if = 1, rear
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__0: vec @(Irgbx, Irgby)
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frame rgb .
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__1: vec .(Drgb, 0mm)
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frame rgb .
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__2: vec .(Drgb, 0mm)
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frame rgb .
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__3: vec @(Iethx, Iethy)
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frame ether .
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__4: vec @(Ws, 0mm)
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__5: vec .(-Idcx, Idcy)
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frame dc .
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__6: vec @(Idbgx, Idbgy)
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frame debug .
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frame short @
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}
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frame usb {
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table
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{ Wusb, Husb }
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{ 8.5mm, 15.5mm }
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__0: vec @(-Wusb, Husb)
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rect . @ w
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@ -81,7 +150,9 @@ frame front {
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table
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{ Iusbx, Iusby, Dusb }
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{ 18.5mm, 6.5mm+1.3mm, 12.5mm }
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{ 18.5mm, 6.5mm+1.4mm, 12.5mm }
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loop if = 1, front
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__0: vec @(Ibutx, Ibuty)
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frame but .
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@ -97,7 +168,7 @@ frame front {
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frame short @
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}
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package "M1"
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package "M1-$part"
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unit mm
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table
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@ -110,4 +181,10 @@ table
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{ H, Ws }
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{ 36.5mm, 2*(Iox+Lox+Iix)+Lix }
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table
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{ part, front, rear }
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{ "front", 1, 0 }
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{ "rear", 0, 1 }
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frame front @
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frame rear @
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10
m1/case/doit
10
m1/case/doit
@ -14,6 +14,9 @@ PATH=$PATH:/home/qi/cae-tools/gp2rml
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# CLEARANCE tool clearance above PCB surface, default: 2mm
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#
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NAME=$1
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shift
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while [ "$1" ]; do
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eval "$1"
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shift
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@ -34,7 +37,7 @@ while [ $yi -lt $YN ]; do
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cat <<EOF >_job
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mm
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gnuplot $MILL case.gp
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gnuplot $MILL $NAME.gp
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align 1 $X0 $Y0 # align relative to board corner
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translate 4mm 4mm # move to PCB zone assigned to project
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@ -42,9 +45,8 @@ array +3mm +3mm `expr $X + $xi` `expr $Y + $yi`
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z 0 $Z0 # board surface (tool fully retracted)
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z -$BOARD_Z # board thickness
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write merged.gp
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offset
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write mill.gp
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write _$NAME.gp
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EOF
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cameo _job || exit
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@ -56,4 +58,4 @@ EOF
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yi=`expr $yi + 1`
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done
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gp2rml $CLEARANCE 10 10 mill.gp >mill.rml || exit
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gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit
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