m1/case/: added rear panel with JTAG hole

m1/case/Makefile

@@ -1,19 +1,33 @@
 SPOOL=/home/moko/svn.openmoko.org/developers/werner/cncmap/spool/spool
+CNGT=/home/qi/cae-tools/cngt/cngt
 
-BOARD=X0=5.0mm Y0=0.0mm Z0=-56.0mm BOARD_Z=4mm
+Z0=-55.0
+BOARD=X0=5.0mm Y0=0.0mm Z0=$(Z0)mm BOARD_Z=4.5mm
+TASK=Y=1
 
-.PHONY:		all mill clean
+.PHONY:		all front rear cng clean
 
-all:		mill.rml
+all:		front.rml rear.rml
 
-case.gp:	case.fpd
+front.gp:	case.fpd
-		fped -g $<
+		fped -g -1 M1-front $< $@
 
-mill.rml:	case.gp
+rear.gp:	case.fpd
-		./doit $(BOARD) CLEARANCE=5mm || { rm -f $@; exit 1; }
+		fped -g -1 M1-rear $< $@
 
-mill:		mill.rml
+%.rml:		%.gp
-		PORT=/dev/ttyUSB0 $(SPOOL) mill.rml
+		./doit `basename $< .gp` $(BOARD) $(TASK) CLEARANCE=5mm || \
+		    { rm -f $@; exit 1; }
+
+front:		front.rml
+		PORT=/dev/ttyUSB0 $(SPOOL) $<
+
+rear:		rear.rml
+		PORT=/dev/ttyUSB0 $(SPOOL) $<
+
+cng:		front.gp
+		$(CNGT) $(Z0) 20 front.gp
 
 clean:
-		rm -f case.gp mill.gp mill.rml
+		rm -f front.gp _front.gp front.rml
+		rm -f rear.gp _rear.gp rear.rml

m1/case/README

@@ -0,0 +1,22 @@
+Reengineered M1 case parts
+==========================
+
+case.fpd contains an fped-based design of the front and rear panel.
+The geometry is based on
+http://projects.qi-hardware.com/index.php/p/m1/source/tree/master/cad/protocase_v7_laser.dxf
+by Joachim Steiger.
+
+This design is fully parametrized and contains the following changes:
+
+- the holes for the USB sockets are raised by 1.4 mm, for the M1pre-rc4
+  prototype (parameter Iusby):
+  http://en.qi-hardware.com/wiki/File:M1pre-rc4-u-A022.JPG
+
+- additional hole in the rear panel for a mini-USB cable going to
+  the JTAG board (parameters Idbgx and Idbgy, with frame "debug")
+
+Known issues:
+
+- button holes are a bit too tight
+
+- DC connector hole is too tight on all sides

m1/case/case.fpd

@@ -58,10 +58,79 @@ frame short {
 	line . __19 w
 }
 
-frame usb {
+frame debug {
-	set Wusb = 8.5mm
+	table
+	    { Wdbg, Hdbg }
+	    { 14.5mm, 9.5mm }
 
-	set Husb = 15.5mm
+	__0: vec @(Wdbg, Hdbg)
+	rect @ . w
+}
+
+frame dc {
+	table
+	    { Wdc, Hdc }
+	    { 9.4mm, 11.4mm }
+
+	__0: vec @(-Wdc, Hdc)
+	rect @ . w
+}
+
+frame ether {
+	table
+	    { Weth, Heth }
+	    { 16.5mm, 14mm }
+
+	__0: vec @(Weth, Heth)
+	rect @ . w
+}
+
+frame rgb {
+	set Rrgb = 6.3mm
+
+	__0: vec @(0mm, Rrgb)
+	circ @ . w
+}
+
+frame rear {
+	table
+	    { Irgbx, Irgby, Drgb }
+	    { 25.5mm, 14.5mm, 15mm }
+
+	table
+	    { Iethx, Iethy }
+	    { 67mm, 7mm }
+
+	table
+	    { Idcx, Idcy }
+	    { 14.8mm, 6.6mm }
+
+	table
+	    { Idbgx, Idbgy }
+	    { 88.1mm, 14.5mm }
+
+	loop if = 1, rear
+
+	__0: vec @(Irgbx, Irgby)
+	frame rgb .
+	__1: vec .(Drgb, 0mm)
+	frame rgb .
+	__2: vec .(Drgb, 0mm)
+	frame rgb .
+	__3: vec @(Iethx, Iethy)
+	frame ether .
+	__4: vec @(Ws, 0mm)
+	__5: vec .(-Idcx, Idcy)
+	frame dc .
+	__6: vec @(Idbgx, Idbgy)
+	frame debug .
+	frame short @
+}
+
+frame usb {
+	table
+	    { Wusb, Husb }
+	    { 8.5mm, 15.5mm }
 
 	__0: vec @(-Wusb, Husb)
 	rect . @ w
@@ -81,7 +150,9 @@ frame front {
 
 	table
 	    { Iusbx, Iusby, Dusb }
-	    { 18.5mm, 6.5mm+1.3mm, 12.5mm }
+	    { 18.5mm, 6.5mm+1.4mm, 12.5mm }
+
+	loop if = 1, front
 
 	__0: vec @(Ibutx, Ibuty)
 	frame but .
@@ -97,7 +168,7 @@ frame front {
 	frame short @
 }
 
-package "M1"
+package "M1-$part"
 unit mm
 
 table
@@ -110,4 +181,10 @@ table
     { H, Ws }
     { 36.5mm, 2*(Iox+Lox+Iix)+Lix }
 
+table
+    { part, front, rear }
+    { "front", 1, 0 }
+    { "rear", 0, 1 }
+
 frame front @
+frame rear @

m1/case/doit

@@ -14,6 +14,9 @@ PATH=$PATH:/home/qi/cae-tools/gp2rml
 # CLEARANCE	tool clearance above PCB surface, default: 2mm
 #
 
+NAME=$1
+shift
+
 while [ "$1" ]; do
     eval "$1"
     shift
@@ -34,7 +37,7 @@ while [ $yi -lt $YN ]; do
 
 	cat <<EOF >_job
 mm
-gnuplot $MILL case.gp
+gnuplot $MILL $NAME.gp
 
 align 1 $X0 $Y0		# align relative to board corner
 translate 4mm 4mm	# move to PCB zone assigned to project
@@ -42,9 +45,8 @@ array +3mm +3mm `expr $X + $xi` `expr $Y + $yi`
 z 0 $Z0			# board surface (tool fully retracted)
 z -$BOARD_Z		# board thickness
 
-write merged.gp
 offset
-write mill.gp
+write _$NAME.gp
 EOF
 
 	cameo _job || exit
@@ -56,4 +58,4 @@ EOF
     yi=`expr $yi + 1`
 done
 
-gp2rml $CLEARANCE 10 10 mill.gp >mill.rml || exit
+gp2rml $CLEARANCE 10 10 _$NAME.gp >$NAME.rml || exit