labsw/: power bypassing is now the way SiLabs recommend

2024-11-15 05:53:09 +02:00 · 2011-09-10 20:00:05 -03:00 · 2011-09-10 20:00:05 -03:00 · 5d32ade1e5
commit 5d32ade1e5
parent 2310466805
3 changed files with 274 additions and 213 deletions
--- a/labsw/LOG
+++ b/labsw/LOG
@ -217,6 +217,7 @@ To do: debounce buttons (in software) before accepting a state change.
  - made 5V relay traces go clearly for the centers of the respective pins
  - changed DIP hole size from 0.5 mm to 0.8 mm, hole-to-copper ratio from
    2.5 to 2
+  - bypass VBUS and VDD with 4.7 uF and 100 nF each

 Pending:
 - widen column cavities by 0.2 mm on each side
--- a/labsw/labsw.cmp
+++ b/labsw/labsw.cmp
@ -1,19 +1,33 @@
-Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Sun Aug 28 09:41:48 2011
+Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Sat Sep 10 19:58:29 2011
+
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 ValeurCmp = 4.7uF;
 IdModule  = 0603;
 EndCmp

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@ -115,42 +129,42 @@ EndCmp
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 TimeStamp = /4E55BEC4/4E55BFD4;
 Reference = R1;
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--- a/labsw/labsw.sch
+++ b/labsw/labsw.sch
@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Sat Sep  3 11:33:29 2011
+EESchema Schematic File Version 2  date Sat Sep 10 19:57:25 2011
 LIBS:power
 LIBS:device
 LIBS:conn
@ -14,323 +14,369 @@ EELAYER END
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 Sheet 1 3
 Title "Lab Switch (Overview and CPU)"
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 Comp "Werner Almesberger"
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