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Code

labsw/: re-layout for the various design changes (including potential separation)

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This commit is contained in:
Werner Almesberger 2011-09-30 03:06:10 -03:00
parent 9ffb0c8c0d
commit 7bc6c89b26
8 changed files with 2714 additions and 1586 deletions
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4
labsw/back.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue Sep 27 11:55:43 2011
EESchema Schematic File Version 2 date Fri Sep 30 02:13:49 2011
LIBS:power
LIBS:device
LIBS:conn
@ -14,7 +14,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 3 4
Title "Lab Switch (Back panel)"
Date "27 sep 2011"
Date "30 sep 2011"
Rev "1"
Comp "Werner Almesberger"
Comment1 ""

40
labsw/ch12.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue Sep 27 11:55:43 2011
EESchema Schematic File Version 2 date Fri Sep 30 02:13:49 2011
LIBS:power
LIBS:device
LIBS:conn
@ -14,7 +14,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 2 4
Title "Lab Switch (CH1/2)"
Date "27 sep 2011"
Date "30 sep 2011"
Rev "1"
Comp "Werner Almesberger"
Comment1 ""
@ -22,6 +22,24 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L OPTO-TRANS-4 U7
U 1 1 4E854A18
P 5300 5650
F 0 "U7" H 5150 5850 60 0000 C CNN
F 1 "OPTO-TRANS-4" H 5300 5425 60 0000 C CNN
1 5300 5650
-1 0 0 -1
$EndComp
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L OPTO-TRANS-4 U6
U 1 1 4E854A0D
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Wire Wire Line
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Connection ~ 6000 2750
@ -352,22 +370,4 @@ F 1 "DS" H 6200 4600 40 0000 C CNN
$EndComp
NoConn ~ 6400 2500
NoConn ~ 6400 5000
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L OPTO-TRANS-2X4 U6
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L OPTO-TRANS-2X4 U6
U 1 1 4E6BEEE3
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$EndComp
$EndSCHEMATC

276
labsw/cpu.sch Normal file
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@ -0,0 +1,276 @@
EESchema Schematic File Version 2 date Thu Aug 25 00:20:19 2011
LIBS:power
LIBS:device
LIBS:conn
LIBS:c8051f320
LIBS:mini_usb_b
LIBS:opto-trans-4
LIBS:spdt-c
LIBS:labsw-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
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Comp ""
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$EndComp
$Comp
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$EndComp
$Comp
L OPTO-TRANS-4 U?
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$Comp
L OPTO-TRANS-4 U?
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-1 0 0 -1
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L CONN_3 K?
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1 2650 4550
-1 0 0 1
$EndComp
$Comp
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$EndComp
$Comp
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$EndComp
$Comp
L DIODE D?
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P 4900 4550
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0 -1 -1 0
$EndComp
$Comp
L +5V #PWR?
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F 0 "#PWR?" H 5100 3990 20 0001 C CNN
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1 5100 3900
1 0 0 -1
$EndComp
$Comp
L +5V #PWR?
U 1 1 4E55BF6E
P 5100 1400
F 0 "#PWR?" H 5100 1490 20 0001 C CNN
F 1 "+5V" H 5100 1490 50 0000 C CNN
1 5100 1400
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$EndComp
Text Label 4750 3050 0 60 ~ 0
CH1_OPT
Text Label 4750 5550 0 60 ~ 0
CH2_OPT
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 4900 1550
Wire Wire Line
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Connection ~ 5100 4050
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 3400 5050
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 5100 1550
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$EndSCHEMATC

4
labsw/front.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue Sep 27 11:55:43 2011
EESchema Schematic File Version 2 date Fri Sep 30 02:13:49 2011
LIBS:power
LIBS:device
LIBS:conn
@ -14,7 +14,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 4 4
Title "Lab Switch (Front panel)"
Date "27 sep 2011"
Date "30 sep 2011"
Rev "1"
Comp "Werner Almesberger"
Comment1 ""

3891
labsw/labsw.brd
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File diff suppressed because it is too large Load Diff

31
labsw/labsw.cmp
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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Mon Sep 26 20:27:15 2011
Cmp-Mod V01 Created by CvPCB (2010-12-27 BZR 2685)-unstable date = Fri Sep 30 01:49:38 2011
BeginCmp
TimeStamp = /4E55CABB;
@ -365,38 +365,45 @@ IdModule = LQFP32;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E5A35D5;
TimeStamp = /4E55BED6/4E81E398;
Reference = U2;
ValeurCmp = OPTO-TRANS-2X4;
ValeurCmp = OPTO-TRANS-2X4R;
IdModule = DIP-8-300mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E5A35CF;
TimeStamp = /4E55BED6/4E81E391;
Reference = U3;
ValeurCmp = OPTO-TRANS-2X4;
ValeurCmp = OPTO-TRANS-2X4R;
IdModule = DIP-8-300mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E5A3480;
TimeStamp = /4E55BED6/4E81E39B;
Reference = U4;
ValeurCmp = OPTO-TRANS-2X4;
ValeurCmp = OPTO-TRANS-2X4R;
IdModule = DIP-8-300mil;
EndCmp
BeginCmp
TimeStamp = /4E55BED6/4E5A347B;
TimeStamp = /4E55BED6/4E81E39D;
Reference = U5;
ValeurCmp = OPTO-TRANS-2X4;
ValeurCmp = OPTO-TRANS-2X4R;
IdModule = DIP-8-300mil;
EndCmp
BeginCmp
TimeStamp = /4E6BEDF0/4E6BEEE4;
TimeStamp = /4E6BEDF0/4E854A0D;
Reference = U6;
ValeurCmp = OPTO-TRANS-2X4;
IdModule = DIP-8-300mil;
ValeurCmp = OPTO-TRANS-4;
IdModule = DIP-4-300mil;
EndCmp
BeginCmp
TimeStamp = /4E6BEDF0/4E854A18;
Reference = U7;
ValeurCmp = OPTO-TRANS-4;
IdModule = DIP-4-300mil;
EndCmp
BeginCmp

2
labsw/labsw.pro
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@ -1,4 +1,4 @@
update=Thu Sep 1 04:40:51 2011
update=Fri Sep 30 03:05:49 2011
last_client=pcbnew
[eeschema]
version=1

52
labsw/labsw.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue Sep 27 11:55:43 2011
EESchema Schematic File Version 2 date Fri Sep 30 02:13:49 2011
LIBS:power
LIBS:device
LIBS:conn
@ -14,7 +14,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 1 4
Title "Lab Switch (Overview and CPU)"
Date "27 sep 2011"
Date "30 sep 2011"
Rev "1"
Comp "Werner Almesberger"
Comment1 ""
@ -25,7 +25,7 @@ $EndDescr
Wire Notes Line
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Wire Notes Line
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8550 6100 10900 6100
Wire Wire Line
9150 5200 9150 5400
Wire Wire Line
@ -172,7 +172,7 @@ Wire Wire Line
Wire Notes Line
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Text Notes 9150 6400 0 60 ~ 0
1 (external pull-ups)
1 (external pull-ups; I/O reassigned)
Text Notes 9150 6250 0 60 ~ 0
0 (internal pull-ups)
Text Notes 8550 6400 0 60 ~ 0
@ -311,35 +311,35 @@ F 1 "+5V" H 3150 3640 50 0000 C CNN
1 3150 3550
1 0 0 -1
$EndComp
Text GLabel 7350 5400 3 60 Output ~ 0
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OUT_3
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OUT_2
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OUT_4
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OUT_3
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OUT_2
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OUT_1
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CH2_OPT
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CH2_RELAY
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CH1_OPT
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CH2_RELAY
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CH1_OPT
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CH1_RELAY
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LED_CH2_G
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LED_CH2_G
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LED_CH2_R
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LED_CH1_G
Text GLabel 7950 2200 1 60 Output ~ 0
LED_CH1_R
Text GLabel 9950 3750 2 60 Output ~ 0
LED_MAIN_G
Text GLabel 9950 3600 2 60 Output ~ 0
LED_CH1_G
Text GLabel 9950 3750 2 60 Output ~ 0
LED_CH1_R
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LED_MAIN_G
Text GLabel 8100 2200 1 60 Output ~ 0
LED_MAIN_R
Text GLabel 7050 2200 1 60 Input ~ 0
Text GLabel 7200 2200 1 60 Input ~ 0
IN_4
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BUT_CH2
@ -348,11 +348,11 @@ BUT_CH1
Text GLabel 7500 2200 1 60 Input ~ 0
BUT_MAIN
NoConn ~ 7350 2400
Text GLabel 7200 2200 1 60 Input ~ 0
Text GLabel 7050 2200 1 60 Input ~ 0
IN_3
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IN_2
Text GLabel 5950 3300 0 60 Input ~ 0
IN_2
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IN_1
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C2D