1
0
mirror of git://projects.qi-hardware.com/wernermisc.git synced 2024-11-27 18:03:44 +02:00
wernermisc/labsw
2012-05-21 01:01:59 -03:00
..
components labsw/: redesigned rear connections to pair in/out by "near" potential 2011-09-27 11:55:57 -03:00
draft labsw/: moved base and front Xfig drawings to draft/ 2011-09-01 10:16:48 -03:00
fw labsw/fw/labsw.c: improved debouncing and cleaned up button logic 2011-09-11 13:03:20 -03:00
mech labsw/mech/Makefile: rm -f will do nicely, no need for rm -rf 2011-12-15 16:58:28 -03:00
modules labsw/modules/spacer.fpd: changed pad to "bare" (no solder paste); added measurements 2012-05-21 01:01:59 -03:00
pcb labsw/pcb/Makefile: increased clearance from 2 mm to 3 mm 2011-09-01 12:04:02 -03:00
tool labsw/tool/: basic labsw control utility 2011-09-06 04:21:36 -03:00
web labsw/web/: added visual indication of test loop 2011-09-12 08:27:36 -03:00
back.sch labsw/: re-layout for the various design changes (including potential separation) 2011-09-30 03:06:10 -03:00
BOM labsw/BOM: almost complete BOM 2011-10-21 21:45:00 -03:00
BOOKSHELF labsw/BOOKSHELF: added the BAS16WT flyback diode 2011-09-05 15:34:16 -03:00
ch12.sch labsw/ch12.sch: added BJT and diode current 2011-10-21 20:54:45 -03:00
cpu.sch labsw/: re-layout for the various design changes (including potential separation) 2011-09-30 03:06:10 -03:00
front.sch labsw/: re-layout for the various design changes (including potential separation) 2011-09-30 03:06:10 -03:00
labsw.brd labsw/labsw.brd: tightened some traces 2011-09-30 06:54:36 -03:00
labsw.cmp labsw/: added partially populated DIP6 sockets since DIP4 is hard to source 2011-09-30 04:03:08 -03:00
labsw.pro labsw/: added partially populated DIP6 sockets since DIP4 is hard to source 2011-09-30 04:03:08 -03:00
labsw.sch labsw/: re-layout for the various design changes (including potential separation) 2011-09-30 03:06:10 -03:00
LOG labsw/: made column cavities 0.2 mm wider on each side 2011-09-18 00:49:38 -03:00
Makefile labsw/Makefile (bom): generate .lst file from eeschema 2011-10-09 22:21:23 -03:00
README labsw/README: all opto headers need wider spacing for high voltage 2011-09-11 13:13:18 -03:00

Opto-isolated inputs
--------------------

The C8051F320 needs a current of at least 50 uA to drive an input low.
The current transfer ratio of the opto coupler is 50% or better.
Thus we need an input current of at least 100 uA.

If we allow for a loss of at least 100 mV (yielding a minimum input
voltage of 1.5 V), the protection resistor can be at most 1 kOhm.

If the maximum power dissipation of the protection resistor is
limited to 1 W, we can allow up to 30 mA into 1 kOhm +/- 10%.

The maximum input voltage would thus be 30 V.


Future changes for higher voltages
----------------------------------

The circuit is currently not designed for voltages exceeding about
30 V between any two points !

To allow the use with mains voltages, be it across the relays or be
it as a difference in "ground" potential of separate loops, at least
the following changes will be necessary:

- air gaps must be 2 mm or larger (6 kV)
- conducting elements closer than 2 mm must be isolated if high
  voltage may exist between them

In particular, this means:

- the PCB must be coated
- opto couplers may not share the same socket
- the opto coupler headers (inputs and outputs) need wider spacing
- clearances need to be verified