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git://projects.qi-hardware.com/xburst-tools.git
synced 2024-11-22 08:10:37 +02:00
add nand init for u-boot
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4c8e0f1763
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@ -35,15 +35,17 @@ void gpio_init();
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void pll_init();
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void serial_init();
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void sdram_init();
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void nand_init();
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void c_main(void)
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{
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load_args();
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gpio_init();
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pll_init();
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serial_init();
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pll_init();
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serial_puts("XBurst boot stage1...\n");
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sdram_init();
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nand_init();
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serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup - now jump back to BOOT ROM...\n");
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}
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@ -89,6 +91,8 @@ void gpio_init()
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__gpio_as_nand();
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__gpio_as_sdram_32bit();
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__gpio_as_uart0();
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__gpio_as_lcd_18bit();
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__gpio_as_msc();
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}
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void pll_init()
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@ -201,7 +205,14 @@ void sdram_init()
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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dmcr0 = (ARG_BUS_WIDTH_16<<EMC_DMCR_BW_BIT) |
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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#define SDRAM_BW16 1
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dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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@ -269,3 +280,9 @@ void sdram_init()
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/* everything is ok now */
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}
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void nand_init()
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{
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REG_EMC_SMCR1 = 0x094c4400;
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REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1; //__nand_enable()
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}
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