xue/kicad/xue-rnc/xue-rnc.net

# EESchema Netlist Version 1.1 created  Tue 10 Aug 2010 09:23:17 PM COT
(
 ( /4C5F1EDC/4C5F2D27 $noname  R10 1M {Lib=R}
  (    1 N-000361 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D1E $noname  C16 4.7nF {Lib=C}
  (    1 N-000361 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA7 $noname  V1 V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000359 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA3 $noname  V2 V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000358 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2B55 $noname  F1 MICROSMD075F {Lib=MICROSMD075F}
  (    1 N-000360 )
  (    2 ? )
 )
 ( /4C5F1EDC/4C5F23DD $noname  J5 USB-48204-0001 {Lib=USB-48204-0001}
  (   S1 N-000361 )
  (   S2 N-000361 )
  (   S3 N-000361 )
  (   S4 N-000361 )
  (    1 N-000360 )
  (    2 N-000358 )
  (    3 N-000359 )
  (    4 GND )
 )
 ( /4C5F1EDC/4C5F2039 $noname  C15 470nF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2037 $noname  C14 1uF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2033 $noname  C13 1uF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2025 $noname  U6 MIC2550AYTS {Lib=MIC2550AYTS}
  (    1 N-000069 )
  (    2 /FPGA_Spartan6/USBA_SPD )
  (    3 /FPGA_Spartan6/USBA_RCV )
  (    4 /FPGA_Spartan6/USBA_VP )
  (    5 /FPGA_Spartan6/USBA_VM )
  (    7 GND )
  (    8 GND )
  (    9 /FPGA_Spartan6/USBA_OE_N )
  (   10 N-000358 )
  (   11 N-000359 )
  (   12 N-000069 )
  (   14 N-000069 )
 )
 ( /4C431A63/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   H9 +2.5V )
  (  U11 +2.5V )
  (  F11 +2.5V )
  (   R6 +2.5V )
  (  M15 +2.5V )
  (   V6 +2.5V )
  (  G12 +2.5V )
  (  H15 +2.5V )
  (  D16 +2.5V )
  (  K15 +2.5V )
  (  R12 +2.5V )
  (   N8 +2.5V )
  (  R10 +2.5V )
  (   L8 +2.5V )
  (  N10 +1.2V )
  (  P11 +1.2V )
  (  P13 +1.2V )
  (   P9 +1.2V )
  (  R14 +1.2V )
  (  N12 +1.2V )
  (  J10 +1.2V )
  (  J12 +1.2V )
  (  J14 +1.2V )
  (   J8 +1.2V )
  (  K11 +1.2V )
  (  K13 +1.2V )
  (   K9 +1.2V )
  (  L10 +1.2V )
  (  L12 +1.2V )
  (  L14 +1.2V )
  (  M11 +1.2V )
  (  M13 +1.2V )
  (   M9 +1.2V )
  (  N14 +1.2V )
  (  G13 ? )
  (   G8 ? )
  (   G9 ? )
  (  H10 ? )
  (  H11 ? )
  (  H12 ? )
  (  H13 ? )
  (  H14 ? )
  (  P16 ? )
  (  D13 ? )
  (  AA1 ? )
  (  N15 ? )
  (  G15 ? )
  (  E18 ? )
  (  A19 ? )
  (  C18 ? )
  (  G11 ? )
  (   F9 ? )
  (   F8 ? )
  (  F15 ? )
  (  F14 ? )
  (  F13 ? )
  (  F12 ? )
  (  F10 ? )
  (   E8 ? )
  (  E14 ? )
  (  E12 ? )
  (  E10 ? )
  (  D12 ? )
  (  P15 ? )
  (  R17 ? )
  (  Y22 ? )
  (  P10 GND )
  (  V10 GND )
  (  M10 GND )
  (  K10 GND )
  (  L13 GND )
  (   A1 GND )
  (  N13 GND )
  (  A22 GND )
  (   R5 GND )
  ( AA13 GND )
  (  W19 GND )
  ( AA17 GND )
  (  K14 GND )
  (  AA5 GND )
  (   L5 GND )
  (  AA9 GND )
  (  M14 GND )
  (  AB1 GND )
  (   N2 GND )
  ( AB22 GND )
  (  P14 GND )
  (  B13 GND )
  (  U21 GND )
  (  B17 GND )
  (   V4 GND )
  (   B5 GND )
  (   J9 GND )
  (   B9 GND )
  (  K12 ? )
  (  D18 GND )
  (  L11 GND )
  (   D4 GND )
  (  L18 GND )
  (  E11 ? )
  (   L9 GND )
  (  E15 GND )
  (  M12 GND )
  (   E2 GND )
  (  N11 GND )
  (  E21 GND )
  (  N17 GND )
  (   E7 GND )
  (  N21 GND )
  (  G18 GND )
  (  P12 GND )
  (   G5 GND )
  (  R18 GND )
  (   H7 GND )
  (   U2 GND )
  (  J11 GND )
  (   U7 GND )
  (  J13 GND )
  (  V14 GND )
  (  J15 GND )
  (  W16 GND )
  (   J2 GND )
  (   W7 GND )
  (  J21 GND )
  (   N9 GND )
  ( AA15 N-000101 )
  (  V16 N-000101 )
  (  T13 N-000101 )
  (   V8 N-000101 )
  (  V12 N-000101 )
  (  AA3 N-000101 )
  (   T9 N-000101 )
  ( AA19 N-000101 )
  ( AA11 N-000101 )
  (   W5 N-000101 )
  (  AA7 N-000101 )
  ( AA12 ? )
  ( AB12 ? )
  (  Y11 ? )
  ( AB11 ? )
  (  R11 ? )
  (  T11 ? )
  ( AA10 ? )
  ( AB10 ? )
  (  V11 ? )
  (  W11 ? )
  (   Y9 ? )
  (  AB9 ? )
  (  W10 ? )
  (  Y10 ? )
  (  AA8 ? )
  (  AB8 ? )
  (   W8 ? )
  (   V7 ? )
  (   W9 ? )
  (   Y8 ? )
  (   Y7 ? )
  (  AB7 ? )
  (  AA6 ? )
  (  AB6 ? )
  (   U9 ? )
  (   V9 ? )
  (   T8 ? )
  (   U8 ? )
  (  T10 ? )
  (  U10 ? )
  (   W6 ? )
  (   Y6 ? )
  (   Y5 ? )
  (  AB5 ? )
  (  AA4 ? )
  (  AB4 ? )
  (   Y3 ? )
  (  AB3 ? )
  (   R9 ? )
  (   R8 ? )
  (   T7 ? )
  (   R7 ? )
  (   W4 ? )
  (   Y4 ? )
  (   U6 ? )
  (   V5 ? )
  (  AA2 ? )
  (  AB2 ? )
  (   T6 ? )
  (   T5 ? )
  ( AB13 ? )
  (  Y13 ? )
  (  Y12 ? )
  (  W12 ? )
  (  R13 ? )
  (  T14 ? )
  (  U12 ? )
  (  T12 ? )
  ( AB15 ? )
  (  Y15 ? )
  (  Y14 ? )
  (  W14 ? )
  ( AB16 ? )
  ( AA16 ? )
  (  W13 ? )
  (  V13 ? )
  (  W15 ? )
  (  Y16 ? )
  ( AB14 ? )
  ( AA14 ? )
  ( AB17 ? )
  (  Y17 ? )
  ( AB18 ? )
  ( AA18 ? )
  (  V15 ? )
  (  U15 ? )
  (  U13 ? )
  (  U14 ? )
  (  W17 ? )
  (  V17 ? )
  (  R15 ? )
  (  R16 ? )
  (  V18 ? )
  (  V19 ? )
  (  U16 ? )
  (  U17 ? )
  (  T15 ? )
  (  T16 ? )
  (  Y18 ? )
  (  W18 ? )
  ( AB19 ? )
  (  Y19 ? )
  (  T17 ? )
  (  T18 ? )
  ( AB20 ? )
  ( AA20 ? )
  ( AB21 ? )
  ( AA21 ? )
  ( AA22 ? )
  (   W2 +2.5V )
  (   L2 +2.5V )
  (   L7 +2.5V )
  (   C2 +2.5V )
  (   N5 +2.5V )
  (   R2 +2.5V )
  (   U5 +2.5V )
  (   G2 +2.5V )
  (   F4 +2.5V )
  (   F6 +2.5V )
  (   J5 +2.5V )
  (   M3 /DDR_Banks/M0_UDM )
  (   L4 /DDR_Banks/M0_LDM )
  (   K5 /DDR_Banks/M0_RAS# )
  (   K4 /DDR_Banks/M0_CAS# )
  (   K3 /DDR_Banks/M0_A5 )
  (   J4 /DDR_Banks/M0_A6 )
  (   K6 /DDR_Banks/M0_A3 )
  (   J6 ? )
  (   H4 /DDR_Banks/M0_CLK )
  (   H3 /DDR_Banks/M0_CLK# )
  (   H2 /DDR_Banks/M0_A0 )
  (   H1 /DDR_Banks/M0_A1 )
  (   G3 /DDR_Banks/M0_BA0 )
  (   G1 /DDR_Banks/M0_BA1 )
  (   H6 /DDR_Banks/M0_A7 )
  (   H5 /DDR_Banks/M0_A2 )
  (   F2 /DDR_Banks/M0_WE# )
  (   F1 ? )
  (   G4 /DDR_Banks/M0_A10 )
  (   F3 /DDR_Banks/M0_A4 )
  (   E3 /DDR_Banks/M0_A8 )
  (   E1 /DDR_Banks/M0_A9 )
  (   D2 /DDR_Banks/M0_CKE )
  (   D1 /DDR_Banks/M0_A12 )
  (   C3 ? )
  (   C1 /DDR_Banks/M0_A11 )
  (   G6 ? )
  (   F5 ? )
  (   K7 ? )
  (   K8 ? )
  (   D5 ? )
  (   E4 ? )
  (   J7 ? )
  (   H8 ? )
  (   B2 ? )
  (   B1 ? )
  (   G7 ? )
  (   F7 ? )
  (   D3 ? )
  (   C4 ? )
  (   E5 ? )
  (   E6 ? )
  (   A2 ? )
  (   B3 ? )
  (   J1 /DDR_Banks/M0_DQ5 )
  (   J3 /DDR_Banks/M0_DQ4 )
  (   K1 /DDR_Banks/M0_DQ7 )
  (   K2 /DDR_Banks/M0_DQ6 )
  (   L1 ? )
  (   L3 /DDR_Banks/M0_LDQS )
  (   M1 /DDR_Banks/M0_DQ3 )
  (   M2 /DDR_Banks/M0_DQ2 )
  (   N1 /DDR_Banks/M0_DQ1 )
  (   N3 /DDR_Banks/M0_DQ0 )
  (   P1 /DDR_Banks/M0_DQ9 )
  (   P2 /DDR_Banks/M0_DQ8 )
  (   R1 /DDR_Banks/M0_DQ11 )
  (   R3 /DDR_Banks/M0_DQ10 )
  (   T1 ? )
  (   T2 /DDR_Banks/M0_UDQS )
  (   U1 /DDR_Banks/M0_DQ13 )
  (   U3 /DDR_Banks/M0_DQ12 )
  (   V1 /DDR_Banks/M0_DQ15 )
  (   V2 /DDR_Banks/M0_DQ14 )
  (   M4 ? )
  (   M5 ? )
  (   N4 ? )
  (   P3 ? )
  (   L6 ? )
  (   M6 ? )
  (   P4 ? )
  (   R4 ? )
  (   M8 ? )
  (   M7 ? )
  (   N7 ? )
  (   N6 ? )
  (   V3 ? )
  (   U4 ? )
  (   T3 ? )
  (   T4 ? )
  (   P5 ? )
  (   P6 ? )
  (   P7 ? )
  (   P8 ? )
  (   W1 ? )
  (   W3 ? )
  (   Y1 ? )
  (  W21 +2.5V )
  (  C21 +2.5V )
  (  G21 +2.5V )
  (  J18 +2.5V )
  (  L16 +2.5V )
  (  L21 +2.5V )
  (  N18 +2.5V )
  (  R21 +2.5V )
  (  U18 +2.5V )
  (  E19 +2.5V )
  (  L19 /DDR_Banks/M1_LDM )
  (  J20 /DDR_Banks/M1_DQ4 )
  (  J22 /DDR_Banks/M1_DQ5 )
  (  K21 /DDR_Banks/M1_DQ6 )
  (  K22 /DDR_Banks/M1_DQ7 )
  (  L20 /DDR_Banks/M1_LDQS )
  (  L22 ? )
  (  M21 /DDR_Banks/M1_DQ2 )
  (  M22 /DDR_Banks/M1_DQ3 )
  (  N20 /DDR_Banks/M1_DQ0 )
  (  N22 /DDR_Banks/M1_DQ1 )
  (  P21 /DDR_Banks/M1_DQ8 )
  (  P22 /DDR_Banks/M1_DQ9 )
  (  R20 /DDR_Banks/M1_DQ10 )
  (  R22 /DDR_Banks/M1_DQ11 )
  (  T21 /DDR_Banks/M1_UDQS )
  (  T22 ? )
  (  U20 /DDR_Banks/M1_DQ12 )
  (  U22 /DDR_Banks/M1_DQ13 )
  (  V21 /DDR_Banks/M1_DQ14 )
  (  V22 /DDR_Banks/M1_DQ15 )
  (  M19 ? )
  (  N19 ? )
  (  M16 ? )
  (  L15 ? )
  (  P19 ? )
  (  P20 ? )
  (  W20 ? )
  (  W22 ? )
  (  L17 ? )
  (  K18 ? )
  (  U19 ? )
  (  V20 ? )
  (  M17 ? )
  (  M18 ? )
  (  P17 ? )
  (  N16 ? )
  (  P18 ? )
  (  R19 ? )
  (  T19 ? )
  (  T20 ? )
  (  M20 /DDR_Banks/M1_UDM )
  (  H22 /DDR_Banks/M1_CAS# )
  (  H21 /DDR_Banks/M1_RAS# )
  (  K19 /DDR_Banks/M1_A6 )
  (  K20 /DDR_Banks/M1_A5 )
  (  G22 ? )
  (  G20 /DDR_Banks/M1_A3 )
  (  J19 /DDR_Banks/M1_CLK# )
  (  H20 /DDR_Banks/M1_CLK )
  (  F22 /DDR_Banks/M1_A1 )
  (  F21 /DDR_Banks/M1_A0 )
  (  K17 /DDR_Banks/M1_BA1 )
  (  J17 /DDR_Banks/M1_BA0 )
  (  E22 /DDR_Banks/M1_A2 )
  (  E20 /DDR_Banks/M1_A7 )
  (  H18 ? )
  (  H19 /DDR_Banks/M1_WE# )
  (  F20 /DDR_Banks/M1_A4 )
  (  G19 /DDR_Banks/M1_A10 )
  (  C22 /DDR_Banks/M1_A9 )
  (  C20 /DDR_Banks/M1_A8 )
  (  D22 /DDR_Banks/M1_A12 )
  (  D21 /DDR_Banks/M1_CKE )
  (  F19 /DDR_Banks/M1_A11 )
  (  F18 ? )
  (  D20 ? )
  (  D19 ? )
  (  H17 ? )
  (  H16 ? )
  (  J16 ? )
  (  K16 ? )
  (  A21 ? )
  (  A20 ? )
  (  B22 ? )
  (  B21 ? )
  (  F17 ? )
  (  F16 ? )
  (  G17 ? )
  (  G16 ? )
  (  B20 ? )
  (   B4 +3.3V )
  (   B7 +3.3V )
  (  E13 +3.3V )
  (  E17 +3.3V )
  (  G10 +3.3V )
  (  G14 +3.3V )
  (  B11 +3.3V )
  (  B15 +3.3V )
  (  B19 +3.3V )
  (   E9 +3.3V )
  (  A11 ? )
  (  D11 ? )
  (  C12 ? )
  (  B12 ? )
  (  A12 ? )
  (  C13 ? )
  (  A13 ? )
  (  D14 ? )
  (  C14 ? )
  (  B14 ? )
  (  A14 ? )
  (  C15 ? )
  (  A15 /Non_volatile_memories/SD_DAT3 )
  (  D15 /Non_volatile_memories/SD_DAT2 )
  (  C16 /Non_volatile_memories/SD_DAT1 )
  (  B16 /Non_volatile_memories/SD_DAT0 )
  (  A16 /Non_volatile_memories/SD_CLK )
  (  C17 /Non_volatile_memories/SD_CMD )
  (  A17 /FPGA_Spartan6/USBA_VM )
  (  B18 /FPGA_Spartan6/USBA_VP )
  (  A18 /FPGA_Spartan6/USBA_RCV )
  (  E16 /FPGA_Spartan6/USBA_OE_N )
  (  D17 /FPGA_Spartan6/USBA_SPD )
  (  C11 ? )
  (  A10 /FPGA_Spartan6/ETH_COL )
  (  B10 /FPGA_Spartan6/ETH_CRS )
  (  C10 /FPGA_Spartan6/ETH_CLK )
  (  D10 /FPGA_Spartan6/ETH_RXC )
  (   D8 /FPGA_Spartan6/ETH_TXC )
  (   D7 /FPGA_Spartan6/ETH_TXD3 )
  (   A9 /FPGA_Spartan6/ETH_TXD2 )
  (   C9 /FPGA_Spartan6/ETH_TXD1 )
  (   C8 /FPGA_Spartan6/ETH_TXD0 )
  (   D9 /FPGA_Spartan6/ETH_TXEN )
  (   A8 /FPGA_Spartan6/ETH_TXER )
  (   B8 /FPGA_Spartan6/ETH_RXER )
  (   A7 /FPGA_Spartan6/ETH_RXDV )
  (   C7 /FPGA_Spartan6/ETH_RXD0 )
  (   A6 /FPGA_Spartan6/ETH_RXD1 )
  (   B6 /FPGA_Spartan6/ETH_RXD2 )
  (   C6 /FPGA_Spartan6/ETH_RXD3 )
  (   D6 /FPGA_Spartan6/ETH_RESET_N )
  (   A5 /FPGA_Spartan6/ETH_MDIO )
  (   C5 /FPGA_Spartan6/ETH_MDC )
  (   A4 /FPGA_Spartan6/ETH_INT )
 )
 ( /4C4320F3/4C5D8114 $noname  C9 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_PLL1.8V )
  (    2 N-000347 )
 )
 ( /4C4320F3/4C5D810A $noname  L3 INDUCTOR {Lib=INDUCTOR}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 /Ethernet_Phy/ETH_PLL1.8V )
 )
 ( /4C4320F3/4C5D8104 $noname  C6 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 N-000347 )
 )
 ( /4C4320F3/4C5D80F3 $noname  L1 INDUCTOR {Lib=INDUCTOR}
  (    1 N-000346 )
  (    2 /Ethernet_Phy/ETH_A1.8V )
 )
 ( /4C4320F3/4C5D80F0 $noname  C4 C {Lib=C}
  (    1 N-000346 )
  (    2 N-000347 )
 )
 ( /4C4320F3/4C5D80ED $noname  C2 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FB7 $noname  L2 FB {Lib=INDUCTOR}
  (    1 N-000069 )
  (    2 /Ethernet_Phy/ETH_A3.3V )
 )
 ( /4C4320F3/4C5D7FA7 $noname  C8 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA5 $noname  C7 1uF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA3 $noname  C5 100nF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA1 $noname  C3 100nF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F9F $noname  C1 1uF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F39 $noname  R1 4.7K {Lib=R}
  (    1 /FPGA_Spartan6/ETH_MDIO )
  (    2 N-000069 )
 )
 ( /4C4320F3/4C5D7ECF $noname  R2 6.65K {Lib=R}
  (    1 N-000336 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E43 $noname  C11 100nF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E41 $noname  C10 100nF {Lib=C}
  (    1 N-000069 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DCB $noname  C12 47nF {Lib=C}
  (    1 N-000345 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DC4 $noname  R9 1M {Lib=R}
  (    1 N-000345 )
  (    2 GND )
 )
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 /FPGA_Spartan6/ETH_MDIO )
  (    2 /FPGA_Spartan6/ETH_MDC )
  (    3 /FPGA_Spartan6/ETH_RXD3 )
  (    4 /FPGA_Spartan6/ETH_RXD2 )
  (    5 /FPGA_Spartan6/ETH_RXD1 )
  (    6 /FPGA_Spartan6/ETH_RXD0 )
  (    7 N-000069 )
  (    8 GND )
  (    9 /FPGA_Spartan6/ETH_RXDV )
  (   10 /FPGA_Spartan6/ETH_RXC )
  (   11 /FPGA_Spartan6/ETH_RXER )
  (   12 GND )
  (   13 /Ethernet_Phy/ETH_1.8V )
  (   14 /FPGA_Spartan6/ETH_TXER )
  (   15 /FPGA_Spartan6/ETH_TXC )
  (   16 /FPGA_Spartan6/ETH_TXEN )
  (   17 /FPGA_Spartan6/ETH_TXD0 )
  (   18 /FPGA_Spartan6/ETH_TXD1 )
  (   19 /FPGA_Spartan6/ETH_TXD2 )
  (   20 /FPGA_Spartan6/ETH_TXD3 )
  (   21 /FPGA_Spartan6/ETH_COL )
  (   22 /FPGA_Spartan6/ETH_CRS )
  (   23 GND )
  (   24 N-000069 )
  (   25 /FPGA_Spartan6/ETH_INT )
  (   26 /Ethernet_Phy/ETH_LED0 )
  (   27 /Ethernet_Phy/ETH_LED1 )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /Ethernet_Phy/ETH_A1.8V )
  (   32 N-000337 )
  (   33 N-000344 )
  (   34 ? )
  (   35 GND )
  (   36 GND )
  (   37 N-000336 )
  (   38 /Ethernet_Phy/ETH_A3.3V )
  (   39 GND )
  (   40 N-000338 )
  (   41 N-000343 )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 ? )
  (   46 /FPGA_Spartan6/ETH_CLK )
  (   47 /Ethernet_Phy/ETH_PLL1.8V )
  (   48 /FPGA_Spartan6/ETH_RESET_N )
 )
 ( /4C4320F3/4C5D7AFE $noname  R3 49.9 {Lib=R}
  (    1 N-000069 )
  (    2 N-000343 )
 )
 ( /4C4320F3/4C5D7AFC $noname  R4 49.9 {Lib=R}
  (    1 N-000069 )
  (    2 N-000338 )
 )
 ( /4C4320F3/4C5D7AF9 $noname  R6 49.9 {Lib=R}
  (    1 N-000069 )
  (    2 N-000337 )
 )
 ( /4C4320F3/4C5D7AF7 $noname  R5 49.9 {Lib=R}
  (    1 N-000069 )
  (    2 N-000344 )
 )
 ( /4C4320F3/4C5D71DB $noname  R8 220 {Lib=R}
  (    1 N-000340 )
  (    2 /Ethernet_Phy/ETH_LED1 )
 )
 ( /4C4320F3/4C5D719D $noname  R7 220 {Lib=R}
  (    1 N-000341 )
  (    2 /Ethernet_Phy/ETH_LED0 )
 )
 ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
  (    1 N-000343 )
  (    2 N-000338 )
  (    3 N-000069 )
  (    4 GND )
  (    5 GND )
  (    6 N-000069 )
  (    7 N-000344 )
  (    8 N-000337 )
  (    9 N-000069 )
  (   10 N-000341 )
  (   11 N-000069 )
  (   12 N-000340 )
  (   13 N-000345 )
  (   14 N-000345 )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  ( CASE GND )
  (   CD ? )
  (  COM GND )
  (    1 /Non_volatile_memories/SD_DAT2 )
  (    2 /Non_volatile_memories/SD_DAT3 )
  (    3 /Non_volatile_memories/SD_CMD )
  (    4 ? )
  (    5 /Non_volatile_memories/SD_CLK )
  (    6 GND )
  (    7 /Non_volatile_memories/SD_DAT0 )
  (    8 /Non_volatile_memories/SD_DAT1 )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /Non_volatile_memories/FRB_N )
  (    7 /Non_volatile_memories/FRB_N )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 N-000069 )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 N-000069 )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 ? )
  (   32 ? )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 N-000069 )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 ? )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C421DD3/4C61D1D4 1206  C34 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61D151 1206  C33 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA5 0402  C28 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA4 0402  C29 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA3 0402  C31 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA2 0402  C30 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA1 0402  C32 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CFA0 0603  C27 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF2F 0603  C21 1uF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF27 0402  C26 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF17 0402  C24 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CF16 0402  C25 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEF7 0402  C23 10nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CEB9 0402  C22 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 GND )
 )
 ( /4C421DD3/4C61CE31 0402  R13 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 N-000047 )
 )
 ( /4C421DD3/4C61CE30 0402  R14 1K_1% {Lib=R}
  (    1 N-000047 )
  (    2 N-000048 )
 )
 ( /4C421DD3/4C61CDB5 0402  R12 1K_1% {Lib=R}
  (    1 N-000046 )
  (    2 N-000045 )
 )
 ( /4C421DD3/4C61CD4A 0402  R11 1K_1% {Lib=R}
  (    1 +2.5V )
  (    2 N-000046 )
 )
 ( /4C421DD3/4C61CCE3 0402  C19 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 N-000047 )
 )
 ( /4C421DD3/4C61CCE2 0402  C20 100nF {Lib=CAP}
  (    1 N-000047 )
  (    2 N-000048 )
 )
 ( /4C421DD3/4C61CC96 0402  C18 100nF {Lib=CAP}
  (    1 N-000046 )
  (    2 N-000045 )
 )
 ( /4C421DD3/4C61CC73 0402  C17 100nF {Lib=CAP}
  (    1 +2.5V )
  (    2 N-000046 )
 )
 ( /4C421DD3/4C609C8E $noname  U3 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /DDR_Banks/M1_DQ0 )
  (    3 +2.5V )
  (    4 /DDR_Banks/M1_DQ1 )
  (    5 /DDR_Banks/M1_DQ2 )
  (    6 GND )
  (    7 /DDR_Banks/M1_DQ3 )
  (    8 /DDR_Banks/M1_DQ4 )
  (    9 +2.5V )
  (   10 /DDR_Banks/M1_DQ5 )
  (   11 /DDR_Banks/M1_DQ6 )
  (   12 GND )
  (   13 /DDR_Banks/M1_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /DDR_Banks/M1_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M1_LDM )
  (   21 /DDR_Banks/M1_WE# )
  (   22 /DDR_Banks/M1_CAS# )
  (   23 /DDR_Banks/M1_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 /DDR_Banks/M1_BA0 )
  (   27 /DDR_Banks/M1_BA1 )
  (   28 /DDR_Banks/M1_A10 )
  (   29 /DDR_Banks/M1_A0 )
  (   30 /DDR_Banks/M1_A1 )
  (   31 /DDR_Banks/M1_A2 )
  (   32 /DDR_Banks/M1_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /DDR_Banks/M1_A4 )
  (   36 /DDR_Banks/M1_A5 )
  (   37 /DDR_Banks/M1_A6 )
  (   38 /DDR_Banks/M1_A7 )
  (   39 /DDR_Banks/M1_A8 )
  (   40 /DDR_Banks/M1_A9 )
  (   41 /DDR_Banks/M1_A11 )
  (   42 /DDR_Banks/M1_A12 )
  (   43 ? )
  (   44 /DDR_Banks/M1_CLK# )
  (   45 /DDR_Banks/M1_CKE )
  (   46 /DDR_Banks/M1_CLK )
  (   47 /DDR_Banks/M1_UDM )
  (   48 GND )
  (   49 N-000047 )
  (   50 ? )
  (   51 /DDR_Banks/M1_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M1_DQ8 )
  (   55 +2.5V )
  (   56 /DDR_Banks/M1_DQ9 )
  (   57 /DDR_Banks/M1_DQ10 )
  (   58 GND )
  (   59 /DDR_Banks/M1_DQ11 )
  (   60 /DDR_Banks/M1_DQ12 )
  (   61 +2.5V )
  (   62 /DDR_Banks/M1_DQ13 )
  (   63 /DDR_Banks/M1_DQ14 )
  (   64 GND )
  (   65 /DDR_Banks/M1_DQ15 )
  (   66 GND )
 )
 ( /4C421DD3/4C609B99 $noname  U2 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 +2.5V )
  (    2 /DDR_Banks/M0_DQ0 )
  (    3 +2.5V )
  (    4 /DDR_Banks/M0_DQ1 )
  (    5 /DDR_Banks/M0_DQ2 )
  (    6 GND )
  (    7 /DDR_Banks/M0_DQ3 )
  (    8 /DDR_Banks/M0_DQ4 )
  (    9 +2.5V )
  (   10 /DDR_Banks/M0_DQ5 )
  (   11 /DDR_Banks/M0_DQ6 )
  (   12 GND )
  (   13 /DDR_Banks/M0_DQ7 )
  (   14 ? )
  (   15 +2.5V )
  (   16 /DDR_Banks/M0_LDQS )
  (   17 ? )
  (   18 +2.5V )
  (   19 ? )
  (   20 /DDR_Banks/M0_LDM )
  (   21 /DDR_Banks/M0_WE# )
  (   22 /DDR_Banks/M0_CAS# )
  (   23 /DDR_Banks/M0_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 /DDR_Banks/M0_BA0 )
  (   27 /DDR_Banks/M0_BA1 )
  (   28 /DDR_Banks/M0_A10 )
  (   29 /DDR_Banks/M0_A0 )
  (   30 /DDR_Banks/M0_A1 )
  (   31 /DDR_Banks/M0_A2 )
  (   32 /DDR_Banks/M0_A3 )
  (   33 +2.5V )
  (   34 GND )
  (   35 /DDR_Banks/M0_A4 )
  (   36 /DDR_Banks/M0_A5 )
  (   37 /DDR_Banks/M0_A6 )
  (   38 /DDR_Banks/M0_A7 )
  (   39 /DDR_Banks/M0_A8 )
  (   40 /DDR_Banks/M0_A9 )
  (   41 /DDR_Banks/M0_A11 )
  (   42 /DDR_Banks/M0_A12 )
  (   43 ? )
  (   44 /DDR_Banks/M0_CLK# )
  (   45 /DDR_Banks/M0_CKE )
  (   46 /DDR_Banks/M0_CLK )
  (   47 /DDR_Banks/M0_UDM )
  (   48 GND )
  (   49 N-000046 )
  (   50 ? )
  (   51 /DDR_Banks/M0_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M0_DQ8 )
  (   55 +2.5V )
  (   56 /DDR_Banks/M0_DQ9 )
  (   57 /DDR_Banks/M0_DQ10 )
  (   58 GND )
  (   59 /DDR_Banks/M0_DQ11 )
  (   60 /DDR_Banks/M0_DQ12 )
  (   61 +2.5V )
  (   62 /DDR_Banks/M0_DQ13 )
  (   63 /DDR_Banks/M0_DQ14 )
  (   64 GND )
  (   65 /DDR_Banks/M0_DQ15 )
  (   66 GND )
 )
)
*
{ Allowed footprints by component:
$component R10
 R?
 SM0603
 SM0805
$endlist
$component C16
 SM*
 C?
 C1-1
$endlist
$component C15
 SM*
 C?
 C1-1
$endlist
$component C14
 SM*
 C?
 C1-1
$endlist
$component C13
 SM*
 C?
 C1-1
$endlist
$component C9
 SM*
 C?
 C1-1
$endlist
$component C6
 SM*
 C?
 C1-1
$endlist
$component C4
 SM*
 C?
 C1-1
$endlist
$component C2
 SM*
 C?
 C1-1
$endlist
$component C8
 SM*
 C?
 C1-1
$endlist
$component C7
 SM*
 C?
 C1-1
$endlist
$component C5
 SM*
 C?
 C1-1
$endlist
$component C3
 SM*
 C?
 C1-1
$endlist
$component C1
 SM*
 C?
 C1-1
$endlist
$component R1
 R?
 SM0603
 SM0805
$endlist
$component R2
 R?
 SM0603
 SM0805
$endlist
$component C11
 SM*
 C?
 C1-1
$endlist
$component C10
 SM*
 C?
 C1-1
$endlist
$component C12
 SM*
 C?
 C1-1
$endlist
$component R9
 R?
 SM0603
 SM0805
$endlist
$component R3
 R?
 SM0603
 SM0805
$endlist
$component R4
 R?
 SM0603
 SM0805
$endlist
$component R6
 R?
 SM0603
 SM0805
$endlist
$component R5
 R?
 SM0603
 SM0805
$endlist
$component R8
 R?
 SM0603
 SM0805
$endlist
$component R7
 R?
 SM0603
 SM0805
$endlist
$component C34
 SM*
 C?
 C1-1
$endlist
$component C33
 SM*
 C?
 C1-1
$endlist
$component C28
 SM*
 C?
 C1-1
$endlist
$component C29
 SM*
 C?
 C1-1
$endlist
$component C31
 SM*
 C?
 C1-1
$endlist
$component C30
 SM*
 C?
 C1-1
$endlist
$component C32
 SM*
 C?
 C1-1
$endlist
$component C27
 SM*
 C?
 C1-1
$endlist
$component C21
 SM*
 C?
 C1-1
$endlist
$component C26
 SM*
 C?
 C1-1
$endlist
$component C24
 SM*
 C?
 C1-1
$endlist
$component C25
 SM*
 C?
 C1-1
$endlist
$component C23
 SM*
 C?
 C1-1
$endlist
$component C22
 SM*
 C?
 C1-1
$endlist
$component R13
 R?
 SM0603
 SM0805
$endlist
$component R14
 R?
 SM0603
 SM0805
$endlist
$component R12
 R?
 SM0603
 SM0805
$endlist
$component R11
 R?
 SM0603
 SM0805
$endlist
$component C19
 SM*
 C?
 C1-1
$endlist
$component C20
 SM*
 C?
 C1-1
$endlist
$component C18
 SM*
 C?
 C1-1
$endlist
$component C17
 SM*
 C?
 C1-1
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 2 "/FPGA Spartan6/ETH_COL" "ETH_COL"
 U1 A10
 U4 21
Net 3 "/Non volatile memories/SD_CLK" "SD_CLK"
 J1 5
 U1 A16
Net 4 "/FPGA Spartan6/USBA_VM" "USBA_VM"
 U1 A17
 U6 5
Net 5 "/FPGA Spartan6/USBA_RCV" "USBA_RCV"
 U1 A18
 U6 3
Net 6 "/FPGA Spartan6/USBA_SPD" "USBA_SPD"
 U1 D17
 U6 2
Net 7 "/FPGA Spartan6/ETH_TXER" "ETH_TXER"
 U1 A8
 U4 14
Net 8 "/FPGA Spartan6/ETH_RXER" "ETH_RXER"
 U1 B8
 U4 11
Net 9 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO"
 U1 A5
 R1 1
 U4 1
Net 10 "/FPGA Spartan6/ETH_RXC" "ETH_RXC"
 U1 D10
 U4 10
Net 11 "GND" "GND"
 C34 2
 C33 2
 C28 2
 C29 2
 C31 2
 C30 2
 C32 2
 C27 2
 C21 2
 C26 2
 C24 2
 C25 2
 C23 2
 C22 2
 U3 24
 U3 34
 U3 48
 U3 66
 U3 6
 U3 12
 U3 52
 U3 58
 U3 64
 U2 24
 U2 34
 U2 48
 U2 66
 U2 6
 U2 12
 U2 52
 U2 58
 U2 64
 J1 CASE
 J1 CASE
 J1 CASE
 J1 6
 J1 COM
 U5 36
 U5 13
 U1 P10
 U1 V10
 U1 M10
 U1 K10
 U1 L13
 U1 A1
 U1 N13
 U1 A22
 U1 R5
 U1 AA13
 U1 W19
 U1 AA17
 U1 K14
 U1 AA5
 U1 L5
 U1 AA9
 U1 M14
 U1 AB1
 U1 N2
 U1 AB22
 U1 P14
 U1 B13
 U1 U21
 U1 B17
 U1 V4
 U1 B5
 U1 J9
 U1 B9
 U1 D18
 U1 L11
 U1 D4
 U1 L18
 U1 L9
 U1 E15
 U1 M12
 U1 E2
 U1 N11
 U1 E21
 U1 N17
 U1 E7
 U1 N21
 U1 G18
 U1 P12
 U1 G5
 U1 R18
 U1 H7
 U1 U2
 U1 J11
 U1 U7
 U1 J13
 U1 V14
 U1 J15
 U1 W16
 U1 J2
 U1 W7
 U1 J21
 U1 N9
 C2 2
 C8 2
 C7 2
 C5 2
 C3 2
 C1 2
 R2 2
 C11 2
 C10 2
 C12 2
 R9 2
 U4 8
 U4 12
 U4 23
 U4 35
 U4 36
 U4 39
 U4 44
 J4 5
 J4 4
 R10 2
 C16 2
 V1 2
 V2 2
 J5 4
 C15 2
 C14 2
 C13 2
 U6 8
 U6 7
Net 12 "/DDR Banks/M1_LDM" "M1_LDM"
 U3 20
 U1 L19
Net 13 "/DDR Banks/M1_CKE" "M1_CKE"
 U3 45
 U1 D21
Net 14 "/DDR Banks/M1_CAS#" "M1_CAS#"
 U3 22
 U1 H22
Net 15 "/DDR Banks/M0_CKE" "M0_CKE"
 U2 45
 U1 D2
Net 16 "/DDR Banks/M0_WE#" "M0_WE#"
 U2 21
 U1 F2
Net 17 "/DDR Banks/M0_CAS#" "M0_CAS#"
 U2 22
 U1 K4
Net 18 "/DDR Banks/M0_UDM" "M0_UDM"
 U2 47
 U1 M3
Net 19 "/DDR Banks/M0_UDQS" "M0_UDQS"
 U2 51
 U1 T2
Net 20 "/DDR Banks/M1_CLK#" "M1_CLK#"
 U3 44
 U1 J19
Net 21 "/DDR Banks/M0_CLK#" "M0_CLK#"
 U2 44
 U1 H3
Net 22 "/DDR Banks/M0_CLK" "M0_CLK"
 U2 46
 U1 H4
Net 23 "/DDR Banks/M1_CLK" "M1_CLK"
 U3 46
 U1 H20
Net 24 "/DDR Banks/M0_LDM" "M0_LDM"
 U2 20
 U1 L4
Net 25 "/DDR Banks/M0_LDQS" "M0_LDQS"
 U2 16
 U1 L3
Net 26 "/DDR Banks/M0_RAS#" "M0_RAS#"
 U2 23
 U1 K5
Net 27 "/DDR Banks/M1_RAS#" "M1_RAS#"
 U3 23
 U1 H21
Net 28 "/DDR Banks/M1_WE#" "M1_WE#"
 U3 21
 U1 H19
Net 29 "/DDR Banks/M1_UDM" "M1_UDM"
 U3 47
 U1 M20
Net 30 "/DDR Banks/M1_LDQS" "M1_LDQS"
 U3 16
 U1 L20
Net 31 "/DDR Banks/M1_UDQS" "M1_UDQS"
 U3 51
 U1 T21
Net 32 "/FPGA Spartan6/ETH_INT" "ETH_INT"
 U1 A4
 U4 25
Net 33 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
 U1 D6
 U4 48
Net 34 "/FPGA Spartan6/ETH_MDC" "ETH_MDC"
 U1 C5
 U4 2
Net 35 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV"
 U1 A7
 U4 9
Net 36 "/FPGA Spartan6/ETH_TXC" "ETH_TXC"
 U1 D8
 U4 15
Net 37 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN"
 U1 D9
 U4 16
Net 38 "/FPGA Spartan6/ETH_CLK" "ETH_CLK"
 U1 C10
 U4 46
Net 39 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N"
 U1 E16
 U6 9
Net 40 "/FPGA Spartan6/USBA_VP" "USBA_VP"
 U1 B18
 U6 4
Net 41 "/Non volatile memories/SD_CMD" "SD_CMD"
 J1 3
 U1 C17
Net 42 "/FPGA Spartan6/ETH_CRS" "ETH_CRS"
 U1 B10
 U4 22
Net 44 "+2.5V" "+2.5V"
 C34 1
 C33 1
 C28 1
 C29 1
 C31 1
 C30 1
 C32 1
 C27 1
 C21 1
 C26 1
 C24 1
 C25 1
 C23 1
 C22 1
 R13 1
 R11 1
 C19 1
 C17 1
 U3 1
 U3 18
 U3 33
 U3 3
 U3 9
 U3 15
 U3 55
 U3 61
 U2 1
 U2 18
 U2 33
 U2 3
 U2 9
 U2 15
 U2 55
 U2 61
 U1 H9
 U1 U11
 U1 F11
 U1 R6
 U1 M15
 U1 V6
 U1 G12
 U1 H15
 U1 D16
 U1 K15
 U1 R12
 U1 N8
 U1 R10
 U1 L8
 U1 W2
 U1 L2
 U1 L7
 U1 C2
 U1 N5
 U1 R2
 U1 U5
 U1 G2
 U1 F4
 U1 F6
 U1 J5
 U1 W21
 U1 C21
 U1 G21
 U1 J18
 U1 L16
 U1 L21
 U1 N18
 U1 R21
 U1 U18
 U1 E19
Net 45 "" ""
 R12 2
 C18 2
Net 46 "" ""
 R12 1
 R11 2
 C18 1
 C17 2
 U2 49
Net 47 "" ""
 R13 2
 R14 1
 C19 2
 C20 1
 U3 49
Net 48 "" ""
 R14 2
 C20 2
Net 64 "/Non volatile memories/FRB_N" "FRB_N"
 U5 7
 U5 6
Net 69 "" ""
 U5 37
 U5 19
 U5 12
 L2 1
 C5 1
 C3 1
 C1 1
 R1 2
 C11 1
 C10 1
 U4 7
 U4 24
 R3 1
 R4 1
 R6 1
 R5 1
 J4 11
 J4 9
 J4 6
 J4 3
 C15 1
 C14 1
 C13 1
 U6 14
 U6 12
 U6 1
Net 99 "+1.2V" "+1.2V"
 U1 N10
 U1 P11
 U1 P13
 U1 P9
 U1 R14
 U1 N12
 U1 J10
 U1 J12
 U1 J14
 U1 J8
 U1 K11
 U1 K13
 U1 K9
 U1 L10
 U1 L12
 U1 L14
 U1 M11
 U1 M13
 U1 M9
 U1 N14
Net 100 "+3.3V" "+3.3V"
 U1 B4
 U1 B7
 U1 E13
 U1 E17
 U1 G10
 U1 G14
 U1 B11
 U1 B15
 U1 B19
 U1 E9
Net 101 "" ""
 U1 AA15
 U1 V16
 U1 T13
 U1 V8
 U1 V12
 U1 AA3
 U1 T9
 U1 AA19
 U1 AA11
 U1 W5
 U1 AA7
Net 334 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
 L3 1
 C6 1
 L1 2
 U4 31
Net 335 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
 L2 2
 C8 1
 C7 1
 U4 38
Net 336 "" ""
 R2 1
 U4 37
Net 337 "" ""
 U4 32
 R6 2
 J4 8
Net 338 "" ""
 U4 40
 R4 2
 J4 2
Net 339 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
 U4 27
 R8 2
Net 340 "" ""
 R8 1
 J4 12
Net 341 "" ""
 R7 1
 J4 10
Net 342 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
 U4 26
 R7 2
Net 343 "" ""
 U4 41
 R3 2
 J4 1
Net 344 "" ""
 U4 33
 R5 2
 J4 7
Net 345 "" ""
 C12 1
 R9 1
 J4 13
 J4 14
Net 346 "" ""
 L1 1
 C4 1
Net 347 "" ""
 C9 2
 C6 2
 C4 2
Net 348 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
 C2 1
 U4 13
Net 349 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
 C9 1
 L3 2
 U4 47
Net 358 "" ""
 V2 1
 V2 1
 J5 2
 U6 10
Net 359 "" ""
 V1 1
 V1 1
 J5 3
 U6 11
Net 360 "" ""
 F1 1
 J5 1
Net 361 "" ""
 R10 1
 C16 1
 J5 S1
 J5 S2
 J5 S3
 J5 S4
Net 362 "/DDR Banks/M0_A0" "M0_A0"
 U2 29
 U1 H2
Net 363 "/DDR Banks/M0_A1" "M0_A1"
 U2 30
 U1 H1
Net 364 "/DDR Banks/M0_A2" "M0_A2"
 U2 31
 U1 H5
Net 365 "/DDR Banks/M0_A3" "M0_A3"
 U2 32
 U1 K6
Net 366 "/DDR Banks/M0_A4" "M0_A4"
 U2 35
 U1 F3
Net 367 "/DDR Banks/M0_A5" "M0_A5"
 U2 36
 U1 K3
Net 368 "/DDR Banks/M0_A6" "M0_A6"
 U2 37
 U1 J4
Net 369 "/DDR Banks/M0_A7" "M0_A7"
 U2 38
 U1 H6
Net 370 "/DDR Banks/M0_A8" "M0_A8"
 U2 39
 U1 E3
Net 371 "/DDR Banks/M0_A9" "M0_A9"
 U2 40
 U1 E1
Net 372 "/DDR Banks/M0_A10" "M0_A10"
 U2 28
 U1 G4
Net 373 "/DDR Banks/M0_A11" "M0_A11"
 U2 41
 U1 C1
Net 374 "/DDR Banks/M0_A12" "M0_A12"
 U2 42
 U1 D1
Net 375 "/DDR Banks/M1_A0" "M1_A0"
 U3 29
 U1 F21
Net 376 "/DDR Banks/M1_A1" "M1_A1"
 U3 30
 U1 F22
Net 377 "/DDR Banks/M1_A2" "M1_A2"
 U3 31
 U1 E22
Net 378 "/DDR Banks/M1_A3" "M1_A3"
 U3 32
 U1 G20
Net 379 "/DDR Banks/M1_A4" "M1_A4"
 U3 35
 U1 F20
Net 380 "/DDR Banks/M1_A5" "M1_A5"
 U3 36
 U1 K20
Net 381 "/DDR Banks/M1_A6" "M1_A6"
 U3 37
 U1 K19
Net 382 "/DDR Banks/M1_A7" "M1_A7"
 U3 38
 U1 E20
Net 383 "/DDR Banks/M1_A8" "M1_A8"
 U3 39
 U1 C20
Net 384 "/DDR Banks/M1_A9" "M1_A9"
 U3 40
 U1 C22
Net 385 "/DDR Banks/M1_A10" "M1_A10"
 U3 28
 U1 G19
Net 386 "/DDR Banks/M1_A11" "M1_A11"
 U3 41
 U1 F19
Net 387 "/DDR Banks/M1_A12" "M1_A12"
 U3 42
 U1 D22
Net 388 "/DDR Banks/M0_DQ0" "M0_DQ0"
 U2 2
 U1 N3
Net 389 "/DDR Banks/M0_DQ1" "M0_DQ1"
 U2 4
 U1 N1
Net 390 "/DDR Banks/M0_DQ2" "M0_DQ2"
 U2 5
 U1 M2
Net 391 "/DDR Banks/M0_DQ3" "M0_DQ3"
 U2 7
 U1 M1
Net 392 "/DDR Banks/M0_DQ4" "M0_DQ4"
 U2 8
 U1 J3
Net 393 "/DDR Banks/M0_DQ5" "M0_DQ5"
 U2 10
 U1 J1
Net 394 "/DDR Banks/M0_DQ6" "M0_DQ6"
 U2 11
 U1 K2
Net 395 "/DDR Banks/M0_DQ7" "M0_DQ7"
 U2 13
 U1 K1
Net 396 "/DDR Banks/M0_DQ8" "M0_DQ8"
 U2 54
 U1 P2
Net 397 "/DDR Banks/M0_DQ9" "M0_DQ9"
 U2 56
 U1 P1
Net 398 "/DDR Banks/M0_DQ10" "M0_DQ10"
 U2 57
 U1 R3
Net 399 "/DDR Banks/M0_DQ11" "M0_DQ11"
 U2 59
 U1 R1
Net 400 "/DDR Banks/M0_DQ12" "M0_DQ12"
 U2 60
 U1 U3
Net 401 "/DDR Banks/M0_DQ13" "M0_DQ13"
 U2 62
 U1 U1
Net 402 "/DDR Banks/M0_DQ14" "M0_DQ14"
 U2 63
 U1 V2
Net 403 "/DDR Banks/M0_DQ15" "M0_DQ15"
 U2 65
 U1 V1
Net 404 "/DDR Banks/M1_DQ0" "M1_DQ0"
 U3 2
 U1 N20
Net 405 "/DDR Banks/M1_DQ1" "M1_DQ1"
 U3 4
 U1 N22
Net 406 "/DDR Banks/M1_DQ2" "M1_DQ2"
 U3 5
 U1 M21
Net 407 "/DDR Banks/M1_DQ3" "M1_DQ3"
 U3 7
 U1 M22
Net 408 "/DDR Banks/M1_DQ4" "M1_DQ4"
 U3 8
 U1 J20
Net 409 "/DDR Banks/M1_DQ5" "M1_DQ5"
 U3 10
 U1 J22
Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6"
 U3 11
 U1 K21
Net 411 "/DDR Banks/M1_DQ7" "M1_DQ7"
 U3 13
 U1 K22
Net 412 "/DDR Banks/M1_DQ8" "M1_DQ8"
 U3 54
 U1 P21
Net 413 "/DDR Banks/M1_DQ9" "M1_DQ9"
 U3 56
 U1 P22
Net 414 "/DDR Banks/M1_DQ10" "M1_DQ10"
 U3 57
 U1 R20
Net 415 "/DDR Banks/M1_DQ11" "M1_DQ11"
 U3 59
 U1 R22
Net 416 "/DDR Banks/M1_DQ12" "M1_DQ12"
 U3 60
 U1 U20
Net 417 "/DDR Banks/M1_DQ13" "M1_DQ13"
 U3 62
 U1 U22
Net 418 "/DDR Banks/M1_DQ14" "M1_DQ14"
 U3 63
 U1 V21
Net 419 "/DDR Banks/M1_DQ15" "M1_DQ15"
 U3 65
 U1 V22
Net 420 "/DDR Banks/M1_BA0" "M1_BA0"
 U3 26
 U1 J17
Net 421 "/DDR Banks/M1_BA1" "M1_BA1"
 U3 27
 U1 K17
Net 422 "/DDR Banks/M0_BA0" "M0_BA0"
 U2 26
 U1 G3
Net 423 "/DDR Banks/M0_BA1" "M0_BA1"
 U2 27
 U1 G1
Net 424 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0"
 U1 C8
 U4 17
Net 425 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1"
 U1 C9
 U4 18
Net 426 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2"
 U1 A9
 U4 19
Net 427 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3"
 U1 D7
 U4 20
Net 428 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0"
 U1 C7
 U4 6
Net 429 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1"
 U1 A6
 U4 5
Net 430 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
 U1 B6
 U4 4
Net 431 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3"
 U1 C6
 U4 3
Net 432 "/Non volatile memories/SD_DAT0" "SD_DAT0"
 J1 7
 U1 B16
Net 433 "/Non volatile memories/SD_DAT1" "SD_DAT1"
 J1 8
 U1 C16
Net 434 "/Non volatile memories/SD_DAT2" "SD_DAT2"
 J1 1
 U1 D15
Net 435 "/Non volatile memories/SD_DAT3" "SD_DAT3"
 J1 2
 U1 A15
}
#End