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xue/kicad/xue-rnc/xue-rnc.brd

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fixed FPGA component bug
2010-08-14 16:23:56 +03:00
PCBNEW-BOARD Version 1 date Sat 14 Aug 2010 08:21:23 AM COT
spi memory added
2010-08-13 23:42:35 +03:00
# Created by Pcbnew(2010-07-15 BZR 2414)-unstable
initial import
2010-07-24 14:58:53 +03:00
$GENERAL
preliminary placement improved
2010-08-13 14:16:55 +03:00
LayerCount 6
Ly 1FFF801F
spi memory added
2010-08-13 23:42:35 +03:00
EnabledLayers 1FFF801F
improved placement
2010-08-14 06:09:52 +03:00
Links 538
NoConn 538
eth-phy placement
2010-08-14 15:42:37 +03:00
Di 43677 13510 70149 50342
improved placement
2010-08-14 06:09:52 +03:00
Ndraw 4
initial import
2010-07-24 14:58:53 +03:00
Ntrack 0
Nzone 0
spi memory added
2010-08-13 23:42:35 +03:00
BoardThickness 630
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Nmodule 113
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Nnets 175
initial import
2010-07-24 14:58:53 +03:00
$EndGENERAL
$SHEETDESCR
Sheet A4 11700 8267
Title ""
improved placement
2010-08-14 06:09:52 +03:00
Date "14 aug 2010"
initial import
2010-07-24 14:58:53 +03:00
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndSHEETDESCR
$SETUP
InternalUnit 0.000100 INCH
ZoneGridSize 250
preliminary placement improved
2010-08-13 14:16:55 +03:00
Layers 6
initial import
2010-07-24 14:58:53 +03:00
Layer[0] Back signal
Layer[1] Inner2 signal
Layer[2] Inner3 signal
preliminary placement improved
2010-08-13 14:16:55 +03:00
Layer[3] Inner4 signal
Layer[4] Inner5 signal
initial import
2010-07-24 14:58:53 +03:00
Layer[15] Front signal
eth-phy placement
2010-08-14 15:42:37 +03:00
TrackWidth 39
TrackClearence 39
initial import
2010-07-24 14:58:53 +03:00
ZoneClearence 200
eth-phy placement
2010-08-14 15:42:37 +03:00
TrackMinWidth 39
initial import
2010-07-24 14:58:53 +03:00
DrawSegmWidth 150
EdgeSegmWidth 150
eth-phy placement
2010-08-14 15:42:37 +03:00
ViaSize 197
ViaDrill 79
ViaMinSize 197
ViaMinDrill 79
MicroViaSize 197
MicroViaDrill 79
initial import
2010-07-24 14:58:53 +03:00
MicroViasAllowed 0
eth-phy placement
2010-08-14 15:42:37 +03:00
MicroViaMinSize 197
MicroViaMinDrill 79
initial import
2010-07-24 14:58:53 +03:00
TextPcbWidth 120
TextPcbSize 600 800
EdgeModWidth 150
TextModSize 600 600
TextModWidth 120
improved placement
2010-08-14 06:09:52 +03:00
PadSize 157 157
PadDrill 0
spi memory added
2010-08-13 23:42:35 +03:00
Pad2MaskClearance 100
initial import
2010-07-24 14:58:53 +03:00
AuxiliaryAxisOrg 0 0
$EndSETUP
$EQUIPOT
Na 0 ""
St ~
$EndEQUIPOT
$EQUIPOT
spi memory added
2010-08-13 23:42:35 +03:00
Na 1 "+1.2V"
St ~
$EndEQUIPOT
$EQUIPOT
Na 2 "+2.5V"
St ~
$EndEQUIPOT
$EQUIPOT
Na 3 "+3.3V"
St ~
$EndEQUIPOT
$EQUIPOT
Na 4 "+5V"
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 5 "/DDR_Banks/M0_A1"
spi memory added
2010-08-13 23:42:35 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 6 "/DDR_Banks/M0_A2"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 7 "/DDR_Banks/M0_BA0"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 8 "/DDR_Banks/M0_CKE"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 9 "/DDR_Banks/M0_CLK"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 10 "/DDR_Banks/M0_CLK#"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 11 "/DDR_Banks/M0_DQ0"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 12 "/DDR_Banks/M0_DQ10"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 13 "/DDR_Banks/M0_DQ11"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 14 "/DDR_Banks/M0_DQ13"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 15 "/DDR_Banks/M0_DQ15"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 16 "/DDR_Banks/M0_DQ3"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 17 "/DDR_Banks/M0_DQ4"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 18 "/DDR_Banks/M0_DQ7"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 19 "/DDR_Banks/M0_UDM"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 20 "/DDR_Banks/M0_UDQS"
only one wire connected
2010-07-28 14:48:02 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 21 "/DDR_Banks/M0_WE#"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 22 "/DDR_Banks/M1_A0"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 23 "/DDR_Banks/M1_A10"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 24 "/DDR_Banks/M1_A5"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 25 "/DDR_Banks/M1_A9"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 26 "/DDR_Banks/M1_BA0"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 27 "/DDR_Banks/M1_BA1"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 28 "/DDR_Banks/M1_CKE"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 29 "/DDR_Banks/M1_DQ10"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 30 "/DDR_Banks/M1_DQ11"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 31 "/DDR_Banks/M1_DQ13"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 32 "/DDR_Banks/M1_DQ4"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 33 "/DDR_Banks/M1_DQ5"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 34 "/DDR_Banks/M1_RAS#"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 35 "/DDR_Banks/M1_UDM"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 36 "/DDR_Banks/M1_UDQS"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 37 "/DDR_Banks/M1_WE#"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 38 "/Ethernet_Phy/ETH_1.8V"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 39 "/Ethernet_Phy/ETH_A1.8V"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 40 "/Ethernet_Phy/ETH_A3.3V"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 41 "/Ethernet_Phy/ETH_CLK"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 42 "/Ethernet_Phy/ETH_COL"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 43 "/Ethernet_Phy/ETH_LED0"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 44 "/Ethernet_Phy/ETH_LED1"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 45 "/Ethernet_Phy/ETH_MDC"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 46 "/Ethernet_Phy/ETH_MDIO"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 47 "/Ethernet_Phy/ETH_PLL1.8V"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 48 "/Ethernet_Phy/ETH_RXC"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 49 "/Ethernet_Phy/ETH_RXD0"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 50 "/Ethernet_Phy/ETH_RXD1"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 51 "/Ethernet_Phy/ETH_RXD2"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 52 "/Ethernet_Phy/ETH_RXER"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 53 "/Ethernet_Phy/ETH_TXD0"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 54 "/Ethernet_Phy/ETH_TXD1"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 55 "/Ethernet_Phy/ETH_TXD3"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 56 "/FPGA_Spartan6/ETH_CRS"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 57 "/FPGA_Spartan6/ETH_INT"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 58 "/FPGA_Spartan6/ETH_RESET_N"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 59 "/FPGA_Spartan6/ETH_RXD3"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 60 "/FPGA_Spartan6/ETH_RXDV"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 61 "/FPGA_Spartan6/ETH_TXC"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 62 "/FPGA_Spartan6/ETH_TXD2"
ddr address and data has been conected to the FPGA
2010-08-05 04:50:31 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 63 "/FPGA_Spartan6/ETH_TXEN"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 64 "/FPGA_Spartan6/ETH_TXER"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 65 "/FPGA_Spartan6/M0_A0"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 66 "/FPGA_Spartan6/M0_A10"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 67 "/FPGA_Spartan6/M0_A11"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 68 "/FPGA_Spartan6/M0_A12"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 69 "/FPGA_Spartan6/M0_A3"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 70 "/FPGA_Spartan6/M0_A4"
cleanup
2010-08-09 05:31:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 71 "/FPGA_Spartan6/M0_A5"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 72 "/FPGA_Spartan6/M0_A6"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 73 "/FPGA_Spartan6/M0_A7"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 74 "/FPGA_Spartan6/M0_A8"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 75 "/FPGA_Spartan6/M0_A9"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 76 "/FPGA_Spartan6/M0_BA1"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 77 "/FPGA_Spartan6/M0_CAS#"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 78 "/FPGA_Spartan6/M0_DQ1"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 79 "/FPGA_Spartan6/M0_DQ12"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 80 "/FPGA_Spartan6/M0_DQ14"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 81 "/FPGA_Spartan6/M0_DQ2"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 82 "/FPGA_Spartan6/M0_DQ5"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 83 "/FPGA_Spartan6/M0_DQ6"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 84 "/FPGA_Spartan6/M0_DQ8"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 85 "/FPGA_Spartan6/M0_DQ9"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 86 "/FPGA_Spartan6/M0_LDM"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 87 "/FPGA_Spartan6/M0_LDQS"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 88 "/FPGA_Spartan6/M0_RAS#"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 89 "/FPGA_Spartan6/M1_A1"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 90 "/FPGA_Spartan6/M1_A11"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 91 "/FPGA_Spartan6/M1_A12"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 92 "/FPGA_Spartan6/M1_A2"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 93 "/FPGA_Spartan6/M1_A3"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 94 "/FPGA_Spartan6/M1_A4"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 95 "/FPGA_Spartan6/M1_A6"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 96 "/FPGA_Spartan6/M1_A7"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 97 "/FPGA_Spartan6/M1_A8"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 98 "/FPGA_Spartan6/M1_CAS#"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 99 "/FPGA_Spartan6/M1_CLK"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 100 "/FPGA_Spartan6/M1_CLK#"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 101 "/FPGA_Spartan6/M1_DQ0"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 102 "/FPGA_Spartan6/M1_DQ1"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 103 "/FPGA_Spartan6/M1_DQ12"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 104 "/FPGA_Spartan6/M1_DQ14"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 105 "/FPGA_Spartan6/M1_DQ15"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 106 "/FPGA_Spartan6/M1_DQ2"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 107 "/FPGA_Spartan6/M1_DQ3"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 108 "/FPGA_Spartan6/M1_DQ6"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 109 "/FPGA_Spartan6/M1_DQ7"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 110 "/FPGA_Spartan6/M1_DQ8"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 111 "/FPGA_Spartan6/M1_DQ9"
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 112 "/FPGA_Spartan6/M1_LDM"
annotate
2010-08-10 05:55:50 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 113 "/FPGA_Spartan6/M1_LDQS"
annotate
2010-08-10 05:55:50 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 114 "/FPGA_Spartan6/NF_ALE"
annotate
2010-08-10 05:55:50 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 115 "/FPGA_Spartan6/NF_CLE"
early placement
2010-08-10 06:25:05 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 116 "/FPGA_Spartan6/NF_CS1_N"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 117 "/FPGA_Spartan6/NF_D0"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 118 "/FPGA_Spartan6/NF_D6"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 119 "/FPGA_Spartan6/NF_D7"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 120 "/FPGA_Spartan6/NF_RE_N"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 121 "/FPGA_Spartan6/NF_RNB"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 122 "/FPGA_Spartan6/PROG_CCLK"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 123 "/FPGA_Spartan6/PROG_CSO"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 124 "/FPGA_Spartan6/PROG_MISO0"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 125 "/FPGA_Spartan6/PROG_MISO1"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 126 "/FPGA_Spartan6/PROG_MISO2"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 127 "/FPGA_Spartan6/PROG_MISO3"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 128 "/FPGA_Spartan6/SD_CLK"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 129 "/FPGA_Spartan6/SD_CMD"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 130 "/FPGA_Spartan6/SD_DAT1"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 131 "/FPGA_Spartan6/SD_DAT3"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 132 "/FPGA_Spartan6/USBA_OE_N"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 133 "/FPGA_Spartan6/USBA_RCV"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 134 "/Non_volatile_memories/NF_D1"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 135 "/Non_volatile_memories/NF_D2"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 136 "/Non_volatile_memories/NF_D3"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 137 "/Non_volatile_memories/NF_D4"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 138 "/Non_volatile_memories/NF_D5"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 139 "/Non_volatile_memories/NF_WE_N"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 140 "/Non_volatile_memories/SD_DAT0"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 141 "/Non_volatile_memories/SD_DAT2"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
improved placement
2010-08-14 06:09:52 +03:00
Na 142 "/USB/USBA_SPD"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
improved placement
2010-08-14 06:09:52 +03:00
Na 143 "/USB/USBA_VM"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
improved placement
2010-08-14 06:09:52 +03:00
Na 144 "/USB/USBA_VP"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 145 "3.3V"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 146 "GND"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 147 "N-000050"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 148 "N-000051"
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 149 "N-000052"
Fixing USB connections
2010-08-11 05:25:32 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
VCC fixed
2010-08-14 01:34:12 +03:00
Na 150 "N-000054"
Fixing USB connections
2010-08-11 05:25:32 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 151 "N-000149"
initial import
2010-07-24 14:58:53 +03:00
St ~
$EndEQUIPOT
fixed placement
2010-08-13 00:12:57 +03:00
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 152 "N-000319"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 153 "N-000320"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 154 "N-000322"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 155 "N-000323"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 156 "N-000326"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 157 "N-000331"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 158 "N-000332"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 159 "N-000333"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 160 "N-000334"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 161 "N-000336"
fix
2010-08-13 05:12:14 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 162 "N-000342"
usb added
2010-08-13 17:27:10 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 163 "N-000343"
usb added
2010-08-13 17:27:10 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 164 "N-000346"
usb added
2010-08-13 17:27:10 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 165 "N-000350"
usb added
2010-08-13 17:27:10 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 166 "N-000354"
usb added
2010-08-13 17:27:10 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 167 "N-000355"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 168 "N-000356"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 169 "N-000357"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 170 "N-000358"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 171 "N-000359"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 172 "N-000360"
VCC fixed
2010-08-14 01:34:12 +03:00
St ~
$EndEQUIPOT
$EQUIPOT
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Na 173 "N-000361"
fixed placement
2010-08-13 00:12:57 +03:00
St ~
$EndEQUIPOT
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
$EQUIPOT
Na 174 "VCCO2"
St ~
$EndEQUIPOT
spi memory added
2010-08-13 23:42:35 +03:00
$NCLASS
Name "Default"
Desc "This is the default net class."
eth-phy placement
2010-08-14 15:42:37 +03:00
Clearance 39
TrackWidth 39
ViaDia 197
ViaDrill 79
uViaDia 197
uViaDrill 79
spi memory added
2010-08-13 23:42:35 +03:00
AddNet ""
AddNet "+1.2V"
AddNet "+2.5V"
AddNet "+3.3V"
AddNet "+5V"
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
AddNet "/DDR_Banks/M0_A1"
AddNet "/DDR_Banks/M0_A2"
AddNet "/DDR_Banks/M0_BA0"
AddNet "/DDR_Banks/M0_CKE"
AddNet "/DDR_Banks/M0_CLK"
AddNet "/DDR_Banks/M0_CLK#"
AddNet "/DDR_Banks/M0_DQ0"
AddNet "/DDR_Banks/M0_DQ10"
AddNet "/DDR_Banks/M0_DQ11"
AddNet "/DDR_Banks/M0_DQ13"
AddNet "/DDR_Banks/M0_DQ15"
AddNet "/DDR_Banks/M0_DQ3"
AddNet "/DDR_Banks/M0_DQ4"
AddNet "/DDR_Banks/M0_DQ7"
AddNet "/DDR_Banks/M0_UDM"
AddNet "/DDR_Banks/M0_UDQS"
AddNet "/DDR_Banks/M0_WE#"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
AddNet "/DDR_Banks/M1_A0"
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
AddNet "/DDR_Banks/M1_A10"
AddNet "/DDR_Banks/M1_A5"
AddNet "/DDR_Banks/M1_A9"
AddNet "/DDR_Banks/M1_BA0"
AddNet "/DDR_Banks/M1_BA1"
AddNet "/DDR_Banks/M1_CKE"
AddNet "/DDR_Banks/M1_DQ10"
AddNet "/DDR_Banks/M1_DQ11"
AddNet "/DDR_Banks/M1_DQ13"
AddNet "/DDR_Banks/M1_DQ4"
AddNet "/DDR_Banks/M1_DQ5"
AddNet "/DDR_Banks/M1_RAS#"
AddNet "/DDR_Banks/M1_UDM"
AddNet "/DDR_Banks/M1_UDQS"
AddNet "/DDR_Banks/M1_WE#"
AddNet "/Ethernet_Phy/ETH_1.8V"
AddNet "/Ethernet_Phy/ETH_A1.8V"
AddNet "/Ethernet_Phy/ETH_A3.3V"
AddNet "/Ethernet_Phy/ETH_CLK"
AddNet "/Ethernet_Phy/ETH_COL"
AddNet "/Ethernet_Phy/ETH_LED0"
AddNet "/Ethernet_Phy/ETH_LED1"
AddNet "/Ethernet_Phy/ETH_MDC"
AddNet "/Ethernet_Phy/ETH_MDIO"
AddNet "/Ethernet_Phy/ETH_PLL1.8V"
AddNet "/Ethernet_Phy/ETH_RXC"
AddNet "/Ethernet_Phy/ETH_RXD0"
AddNet "/Ethernet_Phy/ETH_RXD1"
AddNet "/Ethernet_Phy/ETH_RXD2"
AddNet "/Ethernet_Phy/ETH_RXER"
AddNet "/Ethernet_Phy/ETH_TXD0"
AddNet "/Ethernet_Phy/ETH_TXD1"
AddNet "/Ethernet_Phy/ETH_TXD3"
AddNet "/FPGA_Spartan6/ETH_CRS"
AddNet "/FPGA_Spartan6/ETH_INT"
AddNet "/FPGA_Spartan6/ETH_RESET_N"
AddNet "/FPGA_Spartan6/ETH_RXD3"
AddNet "/FPGA_Spartan6/ETH_RXDV"
AddNet "/FPGA_Spartan6/ETH_TXC"
AddNet "/FPGA_Spartan6/ETH_TXD2"
AddNet "/FPGA_Spartan6/ETH_TXEN"
AddNet "/FPGA_Spartan6/ETH_TXER"
AddNet "/FPGA_Spartan6/M0_A0"
AddNet "/FPGA_Spartan6/M0_A10"
AddNet "/FPGA_Spartan6/M0_A11"
AddNet "/FPGA_Spartan6/M0_A12"
AddNet "/FPGA_Spartan6/M0_A3"
AddNet "/FPGA_Spartan6/M0_A4"
AddNet "/FPGA_Spartan6/M0_A5"
AddNet "/FPGA_Spartan6/M0_A6"
AddNet "/FPGA_Spartan6/M0_A7"
AddNet "/FPGA_Spartan6/M0_A8"
AddNet "/FPGA_Spartan6/M0_A9"
AddNet "/FPGA_Spartan6/M0_BA1"
AddNet "/FPGA_Spartan6/M0_CAS#"
AddNet "/FPGA_Spartan6/M0_DQ1"
AddNet "/FPGA_Spartan6/M0_DQ12"
AddNet "/FPGA_Spartan6/M0_DQ14"
AddNet "/FPGA_Spartan6/M0_DQ2"
AddNet "/FPGA_Spartan6/M0_DQ5"
AddNet "/FPGA_Spartan6/M0_DQ6"
AddNet "/FPGA_Spartan6/M0_DQ8"
AddNet "/FPGA_Spartan6/M0_DQ9"
AddNet "/FPGA_Spartan6/M0_LDM"
AddNet "/FPGA_Spartan6/M0_LDQS"
AddNet "/FPGA_Spartan6/M0_RAS#"
AddNet "/FPGA_Spartan6/M1_A1"
AddNet "/FPGA_Spartan6/M1_A11"
AddNet "/FPGA_Spartan6/M1_A12"
AddNet "/FPGA_Spartan6/M1_A2"
AddNet "/FPGA_Spartan6/M1_A3"
AddNet "/FPGA_Spartan6/M1_A4"
AddNet "/FPGA_Spartan6/M1_A6"
AddNet "/FPGA_Spartan6/M1_A7"
AddNet "/FPGA_Spartan6/M1_A8"
AddNet "/FPGA_Spartan6/M1_CAS#"
AddNet "/FPGA_Spartan6/M1_CLK"
AddNet "/FPGA_Spartan6/M1_CLK#"
AddNet "/FPGA_Spartan6/M1_DQ0"
AddNet "/FPGA_Spartan6/M1_DQ1"
AddNet "/FPGA_Spartan6/M1_DQ12"
AddNet "/FPGA_Spartan6/M1_DQ14"
AddNet "/FPGA_Spartan6/M1_DQ15"
AddNet "/FPGA_Spartan6/M1_DQ2"
AddNet "/FPGA_Spartan6/M1_DQ3"
AddNet "/FPGA_Spartan6/M1_DQ6"
AddNet "/FPGA_Spartan6/M1_DQ7"
AddNet "/FPGA_Spartan6/M1_DQ8"
AddNet "/FPGA_Spartan6/M1_DQ9"
AddNet "/FPGA_Spartan6/M1_LDM"
AddNet "/FPGA_Spartan6/M1_LDQS"
AddNet "/FPGA_Spartan6/NF_ALE"
AddNet "/FPGA_Spartan6/NF_CLE"
AddNet "/FPGA_Spartan6/NF_CS1_N"
AddNet "/FPGA_Spartan6/NF_D0"
AddNet "/FPGA_Spartan6/NF_D6"
AddNet "/FPGA_Spartan6/NF_D7"
AddNet "/FPGA_Spartan6/NF_RE_N"
AddNet "/FPGA_Spartan6/NF_RNB"
AddNet "/FPGA_Spartan6/PROG_CCLK"
AddNet "/FPGA_Spartan6/PROG_CSO"
AddNet "/FPGA_Spartan6/PROG_MISO0"
AddNet "/FPGA_Spartan6/PROG_MISO1"
AddNet "/FPGA_Spartan6/PROG_MISO2"
AddNet "/FPGA_Spartan6/PROG_MISO3"
AddNet "/FPGA_Spartan6/SD_CLK"
AddNet "/FPGA_Spartan6/SD_CMD"
AddNet "/FPGA_Spartan6/SD_DAT1"
AddNet "/FPGA_Spartan6/SD_DAT3"
AddNet "/FPGA_Spartan6/USBA_OE_N"
AddNet "/FPGA_Spartan6/USBA_RCV"
AddNet "/Non_volatile_memories/NF_D1"
AddNet "/Non_volatile_memories/NF_D2"
AddNet "/Non_volatile_memories/NF_D3"
AddNet "/Non_volatile_memories/NF_D4"
AddNet "/Non_volatile_memories/NF_D5"
AddNet "/Non_volatile_memories/NF_WE_N"
AddNet "/Non_volatile_memories/SD_DAT0"
AddNet "/Non_volatile_memories/SD_DAT2"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
AddNet "/USB/USBA_SPD"
AddNet "/USB/USBA_VM"
improved placement
2010-08-14 06:09:52 +03:00
AddNet "/USB/USBA_VP"
spi memory added
2010-08-13 23:42:35 +03:00
AddNet "3.3V"
AddNet "GND"
AddNet "N-000050"
VCC fixed
2010-08-14 01:34:12 +03:00
AddNet "N-000051"
spi memory added
2010-08-13 23:42:35 +03:00
AddNet "N-000052"
VCC fixed
2010-08-14 01:34:12 +03:00
AddNet "N-000054"
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
AddNet "N-000149"
AddNet "N-000319"
AddNet "N-000320"
AddNet "N-000322"
AddNet "N-000323"
improved placement
2010-08-14 06:09:52 +03:00
AddNet "N-000326"
spi memory added
2010-08-13 23:42:35 +03:00
AddNet "N-000331"
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
AddNet "N-000332"
AddNet "N-000333"
AddNet "N-000334"
AddNet "N-000336"
AddNet "N-000342"
AddNet "N-000343"
AddNet "N-000346"
improved placement
2010-08-14 06:09:52 +03:00
AddNet "N-000350"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
AddNet "N-000354"
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
AddNet "N-000355"
AddNet "N-000356"
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
AddNet "N-000357"
AddNet "N-000358"
AddNet "N-000359"
AddNet "N-000360"
AddNet "N-000361"
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
AddNet "VCCO2"
spi memory added
2010-08-13 23:42:35 +03:00
$EndNCLASS
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
$MODULE 1206
spi memory added
2010-08-13 23:42:35 +03:00
Po 63780 39173 1800 15 4C5FF890 4C61D1D4 ~~
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Li 1206
Sc 4C61D1D4
AR /4C421DD3/4C61D1D4
Op 0 0 0
At SMD
spi memory added
2010-08-13 23:42:35 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C34"
T1 0 150 200 200 1800 40 N I 25 N"10uF"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
DS -798 384 -798 -384 50 21
DS -798 -384 798 -384 50 21
DS 798 -384 798 384 50 21
DS 798 384 -798 384 50 21
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "1" R 355 668 0 0 1800
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "2" R 355 668 0 0 1800
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1206
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$MODULE FGG484bga-p10
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 56299 33858 0 15 4C4325AE 4C65E045 ~~
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Li FGG484bga-p10
improved placement
2010-08-14 06:09:52 +03:00
Sc 4C65E045
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
AR /4C431A63/4C431E53
initial import
2010-07-24 14:58:53 +03:00
Op 0 0 0
At SMD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
T0 0 -150 200 200 0 40 N V 25 N"U1"
T1 0 150 200 200 0 40 N I 25 N"XC6SLX45FGG484"
DS -4527 4527 -4527 -4527 39 21
DS -4527 -4527 4527 -4527 39 21
DS 4527 -4527 4527 4527 39 21
DS 4527 4527 -4527 4527 39 21
DS -4527 -4527 -4527 -4842 39 21
DS -4527 -4842 -4842 -4842 39 21
DS -4842 -4842 -4842 -4527 39 21
DS -4842 -4527 -4527 -4527 39 21
initial import
2010-07-24 14:58:53 +03:00
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -3739 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -3346 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 41 "/Ethernet_Phy/ETH_CLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 58 "/FPGA_Spartan6/ETH_RESET_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 49 "/Ethernet_Phy/ETH_RXD0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 52 "/Ethernet_Phy/ETH_RXER"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 63 "/FPGA_Spartan6/ETH_TXEN"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 55 "/Ethernet_Phy/ETH_TXD3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 57 "/FPGA_Spartan6/ETH_INT"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 119 "/FPGA_Spartan6/NF_D7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 136 "/Non_volatile_memories/NF_D3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 134 "/Non_volatile_memories/NF_D1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 983 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 114 "/FPGA_Spartan6/NF_ALE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 121 "/FPGA_Spartan6/NF_RNB"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 141 "/Non_volatile_memories/SD_DAT2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 140 "/Non_volatile_memories/SD_DAT0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 3346 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "A22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -3346 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 50 "/Ethernet_Phy/ETH_RXD1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 64 "/FPGA_Spartan6/ETH_TXER"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 42 "/Ethernet_Phy/ETH_COL"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 137 "/Non_volatile_memories/NF_D4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 120 "/FPGA_Spartan6/NF_RE_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 130 "/FPGA_Spartan6/SD_DAT1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "B22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
some ethernet phy conections
2010-07-28 04:09:20 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 67 "/FPGA_Spartan6/M0_A11"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 46 "/Ethernet_Phy/ETH_MDIO"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 51 "/Ethernet_Phy/ETH_RXD2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 60 "/FPGA_Spartan6/ETH_RXDV"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 54 "/Ethernet_Phy/ETH_TXD1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 62 "/FPGA_Spartan6/ETH_TXD2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 56 "/FPGA_Spartan6/ETH_CRS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 138 "/Non_volatile_memories/NF_D5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 135 "/Non_volatile_memories/NF_D2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 139 "/Non_volatile_memories/NF_WE_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 116 "/FPGA_Spartan6/NF_CS1_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 131 "/FPGA_Spartan6/SD_DAT3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 97 "/FPGA_Spartan6/M1_A8"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "C22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 25 "/DDR_Banks/M1_A9"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 68 "/FPGA_Spartan6/M0_A12"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 8 "/DDR_Banks/M0_CKE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 59 "/FPGA_Spartan6/ETH_RXD3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 61 "/FPGA_Spartan6/ETH_TXC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 48 "/Ethernet_Phy/ETH_RXC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 53 "/Ethernet_Phy/ETH_TXD0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 45 "/Ethernet_Phy/ETH_MDC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 118 "/FPGA_Spartan6/NF_D6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 117 "/FPGA_Spartan6/NF_D0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 115 "/FPGA_Spartan6/NF_CLE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 129 "/FPGA_Spartan6/SD_CMD"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 28 "/DDR_Banks/M1_CKE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "D22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 91 "/FPGA_Spartan6/M1_A12"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 75 "/FPGA_Spartan6/M0_A9"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -2558
$EndPAD
initial import
2010-07-24 14:58:53 +03:00
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 74 "/FPGA_Spartan6/M0_A8"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2952 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2558 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2165 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
improved placement
2010-08-14 06:09:52 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 196 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 983 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 128 "/FPGA_Spartan6/SD_CLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 96 "/FPGA_Spartan6/M1_A7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "E22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 92 "/FPGA_Spartan6/M1_A2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 21 "/DDR_Banks/M0_WE#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 70 "/FPGA_Spartan6/M0_A4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2558 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1771 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1377 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -983 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 90 "/FPGA_Spartan6/M1_A11"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 94 "/FPGA_Spartan6/M1_A4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 22 "/DDR_Banks/M1_A0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "F22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 89 "/FPGA_Spartan6/M1_A1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 76 "/FPGA_Spartan6/M0_BA1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 7 "/DDR_Banks/M0_BA0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 66 "/FPGA_Spartan6/M0_A10"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -983 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 23 "/DDR_Banks/M1_A10"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 93 "/FPGA_Spartan6/M1_A3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "G22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 5 "/DDR_Banks/M0_A1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 65 "/FPGA_Spartan6/M0_A0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 10 "/DDR_Banks/M0_CLK#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 9 "/DDR_Banks/M0_CLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 6 "/DDR_Banks/M0_A2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 73 "/FPGA_Spartan6/M0_A7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
some ethernet phy conections
2010-07-28 04:09:20 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -590 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -196 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 37 "/DDR_Banks/M1_WE#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 99 "/FPGA_Spartan6/M1_CLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 34 "/DDR_Banks/M1_RAS#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "H22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 98 "/FPGA_Spartan6/M1_CAS#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 82 "/FPGA_Spartan6/M0_DQ5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -983
$EndPAD
$PAD
Sh "J2" O 157 157 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 17 "/DDR_Banks/M0_DQ4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 72 "/FPGA_Spartan6/M0_A6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 26 "/DDR_Banks/M1_BA0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 100 "/FPGA_Spartan6/M1_CLK#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 32 "/DDR_Banks/M1_DQ4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "J21" O 157 157 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -983
$EndPAD
$PAD
Sh "J22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 33 "/DDR_Banks/M1_DQ5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 18 "/DDR_Banks/M0_DQ7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 83 "/FPGA_Spartan6/M0_DQ6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 71 "/FPGA_Spartan6/M0_A5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 77 "/FPGA_Spartan6/M0_CAS#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 88 "/FPGA_Spartan6/M0_RAS#"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 69 "/FPGA_Spartan6/M0_A3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
some ethernet phy conections
2010-07-28 04:09:20 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
improved placement
2010-08-14 06:09:52 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 27 "/DDR_Banks/M1_BA1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 95 "/FPGA_Spartan6/M1_A6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 24 "/DDR_Banks/M1_A5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 108 "/FPGA_Spartan6/M1_DQ6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "K22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 109 "/FPGA_Spartan6/M1_DQ7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 87 "/FPGA_Spartan6/M0_LDQS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 86 "/FPGA_Spartan6/M0_LDM"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 112 "/FPGA_Spartan6/M1_LDM"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 113 "/FPGA_Spartan6/M1_LDQS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "L22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 -196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 16 "/DDR_Banks/M0_DQ3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 81 "/FPGA_Spartan6/M0_DQ2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 19 "/DDR_Banks/M0_UDM"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2952 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M9" O 157 157 0 0 0
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 196
$EndPAD
$PAD
Sh "M10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
improved placement
2010-08-14 06:09:52 +03:00
Ne 143 "/USB/USBA_VM"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 35 "/DDR_Banks/M1_UDM"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 106 "/FPGA_Spartan6/M1_DQ2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "M22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 107 "/FPGA_Spartan6/M1_DQ3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 196
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 78 "/FPGA_Spartan6/M0_DQ1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 11 "/DDR_Banks/M0_DQ0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 133 "/FPGA_Spartan6/USBA_RCV"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 101 "/FPGA_Spartan6/M1_DQ0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "N22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 102 "/FPGA_Spartan6/M1_DQ1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 590
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 85 "/FPGA_Spartan6/M0_DQ9"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 84 "/FPGA_Spartan6/M0_DQ8"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -3346 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
improved placement
2010-08-14 06:09:52 +03:00
Ne 144 "/USB/USBA_VP"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 132 "/FPGA_Spartan6/USBA_OE_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 110 "/FPGA_Spartan6/M1_DQ8"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "P22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 111 "/FPGA_Spartan6/M1_DQ9"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 983
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 13 "/DDR_Banks/M0_DQ11"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 12 "/DDR_Banks/M0_DQ10"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1377 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -196 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
some ethernet phy conections
2010-07-28 04:09:20 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
improved placement
2010-08-14 06:09:52 +03:00
Ne 142 "/USB/USBA_SPD"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 29 "/DDR_Banks/M1_DQ10"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "R22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 30 "/DDR_Banks/M1_DQ11"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 1377
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 20 "/DDR_Banks/M0_UDQS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 123 "/FPGA_Spartan6/PROG_CSO"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -590 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
some ethernet phy conections
2010-07-28 04:09:20 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 36 "/DDR_Banks/M1_UDQS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "T22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 1771
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 14 "/DDR_Banks/M0_DQ13"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 79 "/FPGA_Spartan6/M0_DQ12"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1377 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 127 "/FPGA_Spartan6/PROG_MISO3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 126 "/FPGA_Spartan6/PROG_MISO2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2558 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 103 "/FPGA_Spartan6/M1_DQ12"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "U22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 31 "/DDR_Banks/M1_DQ13"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 2165
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 15 "/DDR_Banks/M0_DQ15"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 80 "/FPGA_Spartan6/M0_DQ14"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 3346 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 104 "/FPGA_Spartan6/M1_DQ14"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "V22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 105 "/FPGA_Spartan6/M1_DQ15"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 2558
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -590 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 196 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 590 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 983 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1771 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "W22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 2952
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y1" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -4133 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y2" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y3" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y4" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2952 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y5" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y6" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y7" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y8" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y9" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y10" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y11" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y12" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y13" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y14" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 983 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y15" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y16" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y17" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y18" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y19" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y20" O 158 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 3346 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y21" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "Y22" O 157 158 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 3346
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3739 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2558 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA9" O 157 157 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 3739
$EndPAD
$PAD
Sh "AA10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 983 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1377 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2165 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 151 "N-000149"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2952 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 125 "/FPGA_Spartan6/PROG_MISO1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 122 "/FPGA_Spartan6/PROG_CCLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AA22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 3739
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB1" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -4133 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB2" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -3739 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB3" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -3346 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB4" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2952 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB5" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2558 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB6" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2165 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB7" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1771 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB8" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1377 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB9" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -983 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB10" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -590 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB11" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -196 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB12" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 196 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB13" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 590 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB14" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 983 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB15" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1377 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB16" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 1771 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB17" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2165 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB18" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2558 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB19" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po 2952 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB20" O 158 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 124 "/FPGA_Spartan6/PROG_MISO0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3346 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB21" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 3739 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Sh "AB22" O 157 157 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 4133 4133
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndMODULE FGG484bga-p10
$MODULE LQFP48
improved placement
2010-08-14 06:09:52 +03:00
Po 51575 26772 900 15 4C433D64 4C432132 ~~
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Li LQFP48
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C432132
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
AR /4C4320F3/4C432132
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 900 40 N V 25 N"U4"
T1 0 150 200 200 900 40 N I 25 N"K8001"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
DC -1574 -1574 -1574 -1653 39 21
DS -1377 -1377 -1377 1377 39 21
DS -1377 1377 1377 1377 39 21
DS 1377 1377 1377 -1377 39 21
DS 1377 -1377 -1377 -1377 39 21
initial import
2010-07-24 14:58:53 +03:00
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "12" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 1082
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "11" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 52 "/Ethernet_Phy/ETH_RXER"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 885
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "10" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 48 "/Ethernet_Phy/ETH_RXC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 688
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "9" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 60 "/FPGA_Spartan6/ETH_RXDV"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 491
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "8" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 295
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "7" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 98
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "6" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 49 "/Ethernet_Phy/ETH_RXD0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -98
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "5" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 50 "/Ethernet_Phy/ETH_RXD1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -295
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "4" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 51 "/Ethernet_Phy/ETH_RXD2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -491
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "3" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 59 "/FPGA_Spartan6/ETH_RXD3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -688
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 45 "/Ethernet_Phy/ETH_MDC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -885
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 46 "/Ethernet_Phy/ETH_MDIO"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1613 -1082
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "48" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 58 "/FPGA_Spartan6/ETH_RESET_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1082 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "47" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 47 "/Ethernet_Phy/ETH_PLL1.8V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -885 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "46" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 41 "/Ethernet_Phy/ETH_CLK"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -688 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "45" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -491 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "44" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -295 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "43" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -98 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "42" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 98 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "41" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 154 "N-000322"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 295 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "40" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 159 "N-000333"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 491 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "39" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 688 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "38" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 40 "/Ethernet_Phy/ETH_A3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 885 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "37" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 157 "N-000331"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1082 -1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "25" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 57 "/FPGA_Spartan6/ETH_INT"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 1082
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "26" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 43 "/Ethernet_Phy/ETH_LED0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 885
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "27" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 44 "/Ethernet_Phy/ETH_LED1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 688
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "28" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 491
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "29" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 295
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "30" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 98
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "31" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 39 "/Ethernet_Phy/ETH_A1.8V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -98
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "32" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 158 "N-000332"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -295
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "33" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 155 "N-000323"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -491
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "34" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -688
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "35" R 315 99 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -885
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "36" R 315 98 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1613 -1082
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "13" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 38 "/Ethernet_Phy/ETH_1.8V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1082 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "14" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 64 "/FPGA_Spartan6/ETH_TXER"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -885 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "15" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 61 "/FPGA_Spartan6/ETH_TXC"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -688 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "16" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 63 "/FPGA_Spartan6/ETH_TXEN"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -491 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "17" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 53 "/Ethernet_Phy/ETH_TXD0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -295 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "18" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 54 "/Ethernet_Phy/ETH_TXD1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -98 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "19" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 62 "/FPGA_Spartan6/ETH_TXD2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 98 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "20" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 55 "/Ethernet_Phy/ETH_TXD3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 295 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "21" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 42 "/Ethernet_Phy/ETH_COL"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 491 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "22" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 56 "/FPGA_Spartan6/ETH_CRS"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 688 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "23" R 99 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 885 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "24" R 98 315 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1082 1613
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndMODULE LQFP48
$MODULE NAND-48TSOP
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 59252 26181 900 15 4B8F4C98 4B76F108 ~~
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Li NAND-48TSOP
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Sc 4B76F108
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
AR /4C4227FE/4B76F108
Op 0 0 0
fixed placement
2010-08-13 00:12:57 +03:00
T0 -1816 4454 157 157 2700 20 N V 21 N"U5"
T1 0 118 118 118 2700 20 N I 21 N"NAND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
DS -2470 3900 -2470 -3900 60 24
DS -2470 -3900 2430 -3900 60 24
DS 2430 -3900 2430 3900 60 24
DS 2430 3900 -2470 3900 60 24
DS -2270 4320 -2470 4520 60 26
DS -2470 4520 -2070 4520 60 26
DS -2070 4520 -2270 4320 60 26
DS -2360 3500 2360 3500 60 26
DS 2360 3500 2360 -3500 60 26
DS 2360 -3500 -2360 -3500 60 26
DS -2360 -3500 -2360 3500 60 26
DS -2270 4320 -2470 4520 60 21
DS -2470 4520 -2070 4520 60 21
DS -2070 4520 -2270 4320 60 21
DS -2420 3400 2380 3400 60 21
DS 2380 3400 2380 -3450 60 21
DS 2380 -3450 -2420 -3450 60 21
DS -2420 -3450 -2420 3400 60 21
DS -2400 3500 -2290 3500 30 26
DS -2290 3500 -2290 3900 30 26
DS -2290 3900 -2240 3900 30 26
DS -2240 3900 -2240 3500 30 26
DS -2240 3500 -2090 3500 30 26
DS -2090 3500 -2090 3900 30 26
DS -2090 3900 -2040 3900 30 26
DS -2040 3900 -2040 3500 30 26
DS -2040 3500 -1900 3500 30 26
DS -1900 3500 -1900 3900 30 26
DS -1900 3900 -1850 3900 30 26
DS -1850 3900 -1850 3500 30 26
DS -1850 3500 -1700 3500 30 26
DS -1700 3500 -1700 3900 30 26
DS -1700 3900 -1650 3900 30 26
DS -1650 3900 -1650 3500 30 26
DS -1650 3500 -1500 3500 30 26
DS -1500 3500 -1500 3900 30 26
DS -1500 3900 -1450 3900 30 26
DS -1450 3900 -1450 3500 30 26
DS -1450 3500 -1300 3500 30 26
DS -1300 3500 -1300 3900 30 26
DS -1300 3900 -1250 3900 30 26
DS -1250 3900 -1250 3500 30 26
DS -1250 3500 -1110 3500 30 26
DS -1110 3500 -1110 3900 30 26
DS -1110 3900 -1060 3900 30 26
DS -1060 3900 -1060 3500 30 26
DS -1060 3500 -910 3500 30 26
DS -910 3500 -910 3900 30 26
DS -910 3900 -860 3900 30 26
DS -860 3900 -860 3500 30 26
DS -860 3500 -710 3500 30 26
DS -710 3500 -710 3900 30 26
DS -710 3900 -660 3900 30 26
DS -660 3900 -660 3500 30 26
DS -660 3500 -510 3500 30 26
DS -510 3500 -510 3900 30 26
DS -510 3900 -460 3900 30 26
DS -460 3900 -460 3500 30 26
DS -460 3500 -320 3500 30 26
DS -320 3500 -320 3900 30 26
DS -320 3900 -270 3900 30 26
DS -270 3900 -270 3500 30 26
DS -270 3500 -120 3500 30 26
DS -120 3500 -120 3900 30 26
DS -120 3900 -70 3900 30 26
DS -70 3900 -70 3500 30 26
DS -70 3500 80 3500 30 26
DS 80 3500 80 3900 30 26
DS 80 3900 130 3900 30 26
DS 130 3900 130 3500 30 26
DS 130 3500 280 3500 30 26
DS 280 3500 280 3900 30 26
DS 280 3900 330 3900 30 26
DS 330 3900 330 3500 30 26
DS 330 3500 470 3500 30 26
DS 470 3500 470 3900 30 26
DS 470 3900 520 3900 30 26
DS 520 3900 520 3500 30 26
DS 520 3500 670 3500 30 26
DS 670 3500 670 3900 30 26
DS 670 3900 720 3900 30 26
DS 720 3900 720 3500 30 26
DS 720 3500 860 3500 30 26
DS 860 3500 860 3900 30 26
DS 860 3900 910 3900 30 26
DS 910 3900 910 3500 30 26
DS 910 3500 1060 3500 30 26
DS 1060 3500 1060 3900 30 26
DS 1060 3900 1110 3900 30 26
DS 1110 3900 1110 3500 30 26
DS 1110 3500 1250 3500 30 26
DS 1250 3500 1250 3900 30 26
DS 1250 3900 1300 3900 30 26
DS 1300 3900 1300 3500 30 26
DS 1300 3500 1450 3500 30 26
DS 1450 3500 1450 3900 30 26
DS 1450 3900 1500 3900 30 26
DS 1500 3900 1500 3500 30 26
DS 1500 3500 1650 3500 30 26
DS 1650 3500 1650 3900 30 26
DS 1650 3900 1700 3900 30 26
DS 1700 3900 1700 3510 30 26
DS 1700 3510 1710 3500 30 26
DS 1710 3500 1850 3500 30 26
DS 1850 3500 1850 3900 30 26
DS 1850 3900 1900 3900 30 26
DS 1900 3900 1900 3500 30 26
DS 1900 3500 2040 3500 30 26
DS 2040 3500 2040 3900 30 26
DS 2040 3900 2090 3900 30 26
DS 2090 3900 2090 3500 30 26
DS 2090 3500 2240 3500 30 26
DS 2240 3500 2240 3900 30 26
DS 2240 3900 2290 3900 30 26
DS 2290 3900 2290 3500 30 26
DS 2290 3500 2360 3500 30 26
DS 2360 3500 2360 -3500 30 26
DS 2360 -3500 2290 -3500 30 26
DS 2290 -3500 2290 -3900 30 26
DS 2290 -3900 2240 -3900 30 26
DS 2240 -3900 2240 -3500 30 26
DS 2240 -3500 2090 -3500 30 26
DS 2090 -3500 2090 -3900 30 26
DS 2090 -3900 2040 -3900 30 26
DS 2040 -3900 2040 -3500 30 26
DS 2040 -3500 1900 -3500 30 26
DS 1900 -3500 1900 -3900 30 26
DS 1900 -3900 1850 -3900 30 26
DS 1850 -3900 1850 -3500 30 26
DS 1850 -3500 1700 -3500 30 26
DS 1700 -3500 1700 -3900 30 26
DS 1700 -3900 1650 -3900 30 26
DS 1650 -3900 1650 -3500 30 26
DS 1650 -3500 1500 -3500 30 26
DS 1500 -3500 1500 -3900 30 26
DS 1500 -3900 1450 -3900 30 26
DS 1450 -3900 1450 -3500 30 26
DS 1450 -3500 1300 -3500 30 26
DS 1300 -3500 1300 -3900 30 26
DS 1300 -3900 1250 -3900 30 26
DS 1250 -3900 1250 -3500 30 26
DS 1250 -3500 1110 -3500 30 26
DS 1110 -3500 1110 -3900 30 26
DS 1110 -3900 1060 -3900 30 26
DS 1060 -3900 1060 -3500 30 26
DS 1060 -3500 910 -3500 30 26
DS 910 -3500 910 -3900 30 26
DS 910 -3900 860 -3900 30 26
DS 860 -3900 860 -3500 30 26
DS 860 -3500 720 -3500 30 26
DS 720 -3500 720 -3900 30 26
DS 720 -3900 670 -3900 30 26
DS 670 -3900 670 -3500 30 26
DS 670 -3500 520 -3500 30 26
DS 520 -3500 520 -3900 30 26
DS 520 -3900 470 -3900 30 26
DS 470 -3900 470 -3500 30 26
DS 470 -3500 330 -3500 30 26
DS 330 -3500 330 -3900 30 26
DS 330 -3900 280 -3900 30 26
DS 280 -3900 280 -3500 30 26
DS 280 -3500 130 -3500 30 26
DS 130 -3500 130 -3900 30 26
DS 130 -3900 80 -3900 30 26
DS 80 -3900 80 -3500 30 26
DS 80 -3500 -70 -3500 30 26
DS -70 -3500 -70 -3900 30 26
DS -70 -3900 -120 -3900 30 26
DS -120 -3900 -120 -3500 30 26
DS -120 -3500 -270 -3500 30 26
DS -270 -3500 -270 -3900 30 26
DS -270 -3900 -320 -3900 30 26
DS -320 -3900 -320 -3500 30 26
DS -320 -3500 -460 -3500 30 26
DS -460 -3500 -460 -3900 30 26
DS -460 -3900 -510 -3900 30 26
DS -510 -3900 -510 -3500 30 26
DS -510 -3500 -660 -3500 30 26
DS -660 -3500 -660 -3900 30 26
DS -660 -3900 -710 -3900 30 26
DS -710 -3900 -710 -3500 30 26
DS -710 -3500 -860 -3500 30 26
DS -860 -3500 -860 -3900 30 26
DS -860 -3900 -910 -3900 30 26
DS -910 -3900 -910 -3500 30 26
DS -910 -3500 -1060 -3500 30 26
DS -1060 -3500 -1060 -3900 30 26
DS -1060 -3900 -1110 -3900 30 26
DS -1110 -3900 -1110 -3500 30 26
DS -1110 -3500 -1250 -3500 30 26
DS -1250 -3500 -1250 -3900 30 26
DS -1250 -3900 -1300 -3900 30 26
DS -1300 -3900 -1300 -3500 30 26
DS -1300 -3500 -1450 -3500 30 26
DS -1450 -3500 -1450 -3900 30 26
DS -1450 -3900 -1500 -3900 30 26
DS -1500 -3900 -1500 -3500 30 26
DS -1500 -3500 -1650 -3500 30 26
DS -1650 -3500 -1650 -3900 30 26
DS -1650 -3900 -1700 -3900 30 26
DS -1700 -3900 -1700 -3500 30 26
DS -1700 -3500 -1850 -3500 30 26
DS -1850 -3500 -1850 -3900 30 26
DS -1850 -3900 -1900 -3900 30 26
DS -1900 -3900 -1900 -3500 30 26
DS -1900 -3500 -2040 -3500 30 26
DS -2040 -3500 -2040 -3900 30 26
DS -2040 -3900 -2090 -3900 30 26
DS -2090 -3900 -2090 -3500 30 26
DS -2090 -3500 -2240 -3500 30 26
DS -2240 -3500 -2240 -3900 30 26
DS -2240 -3900 -2290 -3900 30 26
DS -2290 -3900 -2290 -3500 30 26
initial import
2010-07-24 14:58:53 +03:00
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "1" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2270 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "2" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2070 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "3" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1870 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "4" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1680 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "5" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1480 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "6" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 121 "/FPGA_Spartan6/NF_RNB"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1280 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "7" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 121 "/FPGA_Spartan6/NF_RNB"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1090 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "8" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 120 "/FPGA_Spartan6/NF_RE_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -890 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "9" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 116 "/FPGA_Spartan6/NF_CS1_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -690 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "10" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -500 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "11" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -300 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "12" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -100 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "13" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 100 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "14" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 290 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "15" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 490 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "16" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 115 "/FPGA_Spartan6/NF_CLE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 690 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "17" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 114 "/FPGA_Spartan6/NF_ALE"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 880 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "18" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 139 "/Non_volatile_memories/NF_WE_N"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1080 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "19" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1280 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "20" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1470 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "21" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1670 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "22" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1870 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "23" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2060 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "24" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2260 3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "25" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2260 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "26" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 2060 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "27" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1870 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "28" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1670 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "29" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 117 "/FPGA_Spartan6/NF_D0"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1470 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "30" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 134 "/Non_volatile_memories/NF_D1"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1280 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "31" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 135 "/Non_volatile_memories/NF_D2"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 1080 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "32" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 136 "/Non_volatile_memories/NF_D3"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 880 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "33" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 690 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "34" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 490 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "35" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 290 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "36" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po 100 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "37" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 3 "+3.3V"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -100 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "38" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -300 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "39" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -500 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "40" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -690 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "41" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 137 "/Non_volatile_memories/NF_D4"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -890 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "42" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 138 "/Non_volatile_memories/NF_D5"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1090 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "43" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 118 "/FPGA_Spartan6/NF_D6"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1280 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "44" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 119 "/FPGA_Spartan6/NF_D7"
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1480 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "45" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -1680 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "46" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -1870 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "47" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
Po -2070 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
fixed placement
2010-08-13 00:12:57 +03:00
Sh "48" R 100 600 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Po -2270 -3850
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndMODULE NAND-48TSOP
ddr footprint changed
2010-08-10 05:29:52 +03:00
$MODULE MICROSD-500901
spi memory added
2010-08-13 23:42:35 +03:00
Po 60827 16732 0 0 4C5F34DA 4B76F5E2 ~~
ddr footprint changed
2010-08-10 05:29:52 +03:00
Li MICROSD-500901
Sc 4B76F5E2
AR /4C4227FE/4B76F5E2
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Op 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
T0 -160 652 157 157 0 20 M V 20 N"J1"
T1 0 -118 118 118 1800 20 M I 20 N"MICROSD"
DS -2709 -1675 -2709 507 60 20
DS -2707 -3095 -2707 -2747 60 20
DS 2709 -1699 2709 500 60 20
DS 2706 -3088 2706 -2767 60 20
DS -1989 1553 -1989 1013 60 20
DS -1989 1013 1573 1016 60 20
DS 1573 1016 1573 1548 60 20
DS -2707 1555 2707 1555 60 20
DS -2707 -3091 2707 -3091 60 20
$PAD
Sh "1" R 315 590 0 0 0
Dr 0 0 0
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 141 "/Non_volatile_memories/SD_DAT2"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1299 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "2" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 131 "/FPGA_Spartan6/SD_DAT3"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -866 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "3" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 129 "/FPGA_Spartan6/SD_CMD"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -433 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "4" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po 0 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "5" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 128 "/FPGA_Spartan6/SD_CLK"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 433 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "6" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 866 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "7" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 140 "/Non_volatile_memories/SD_DAT0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1299 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "8" R 315 590 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 130 "/FPGA_Spartan6/SD_DAT1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1732 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "CASE" R 571 787 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po 2707 1024
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "CASE" R 571 787 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po -2707 1024
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "CASE" R 571 787 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po -2707 -2244
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
spi memory added
2010-08-13 23:42:35 +03:00
Sh "CASE" R 571 787 0 0 0
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
spi memory added
2010-08-13 23:42:35 +03:00
At STD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po 2707 -2244
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
$EndMODULE MICROSD-500901
$MODULE SD-48025
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 50197 17913 1800 15 00000000 4C5D6F5A ~~
ddr footprint changed
2010-08-10 05:29:52 +03:00
Li SD-48025
Sc 4C5D6F5A
AR /4C4320F3/4C5D6F5A
Op 0 0 0
T0 527 -694 157 157 1800 20 N V 21 N"J4"
T1 0 118 118 118 0 20 N I 21 N"RJ45-48025"
DS -3700 -5800 -3700 4300 60 21
DS -3700 -5800 3700 -5800 60 21
DS 3700 -5800 3700 4300 60 21
DS -3700 4300 3700 4300 60 21
initial import
2010-07-24 14:58:53 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "13" C 1646 1646 0 0 1800
Dr 1252 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2250 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "13" C 984 984 0 0 1800
Dr 640 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3100 -1200
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "14" C 1646 1646 0 0 1800
Dr 1252 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2250 0
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "14" C 984 984 0 0 1800
Dr 640 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3100 -1200
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "1" R 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 154 "N-000322"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1750 -2500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "3" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -750 -2500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "5" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 250 -2500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "7" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 155 "N-000323"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1250 -2500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "2" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 159 "N-000333"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1250 -3500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "4" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -250 -3500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "6" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 750 -3500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "8" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 158 "N-000332"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1750 -3500
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "9" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2150 -5400
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "10" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 153 "N-000320"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1150 -5400
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "11" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1150 -5400
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "12" C 540 540 0 0 1800
Dr 350 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 161 "N-000336"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2150 -5400
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
$EndMODULE SD-48025
$MODULE TSSOP-14
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 57430 25930 2700 0 4C60642A 4C5F2025 ~~
ddr footprint changed
2010-08-10 05:29:52 +03:00
Li TSSOP-14
Sc 4C5F2025
AR /4C5F1EDC/4C5F2025
Op 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
T0 50 1822 276 276 2700 69 M V 20 N"U6"
T1 70 -1848 276 276 2700 69 M I 20 N"MIC2550AYTS"
DC -738 -409 -666 -418 150 20
DS 987 -634 -984 -628 150 20
DS -984 -628 -984 -187 150 20
DS -984 -187 -726 -187 150 20
DS -726 -187 -726 185 150 20
DS -726 185 -987 188 150 20
DS -987 188 -984 649 150 20
DS -984 649 982 650 150 20
DS 982 650 986 -634 150 20
DS -984 787 984 787 1 20
DS 984 787 984 -787 1 20
DS -984 -787 984 -787 1 20
DS -984 787 -984 -787 1 20
initial import
2010-07-24 14:58:53 +03:00
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -767 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
improved placement
2010-08-14 06:09:52 +03:00
Ne 142 "/USB/USBA_SPD"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -511 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "3" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 133 "/FPGA_Spartan6/USBA_RCV"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -255 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "4" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
improved placement
2010-08-14 06:09:52 +03:00
Ne 144 "/USB/USBA_VP"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 0 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "5" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
improved placement
2010-08-14 06:09:52 +03:00
Ne 143 "/USB/USBA_VM"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 255 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "6" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 511 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "7" R 137 570 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 767 -1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "8" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 767 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "9" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 132 "/FPGA_Spartan6/USBA_OE_N"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 511 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "10" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 162 "N-000342"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 255 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "11" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 173 "N-000361"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 0 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "12" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -255 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "13" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
initial import
2010-07-24 14:58:53 +03:00
Ne 0 ""
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -511 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "14" R 137 570 0 0 2700
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po -767 1112
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
$EndMODULE TSSOP-14
$MODULE TSOP-66
Fixing USB connections
2010-08-11 05:25:32 +03:00
Po 63780 34055 900 15 4C6098A7 4C609C8E ~~
ddr footprint changed
2010-08-10 05:29:52 +03:00
Li TSOP-66
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C609C8E
ddr footprint changed
2010-08-10 05:29:52 +03:00
AR /4C421DD3/4C609C8E
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"U3"
T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG"
DC -4094 1881 -4094 1822 39 21
DS 4350 -1968 4350 1968 39 21
DS 4350 1968 -4350 1968 39 21
DS -4350 1968 -4350 -1968 39 21
DS -4350 -1968 4350 -1968 39 21
initial import
2010-07-24 14:58:53 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "1" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -4094 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "2" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 101 "/FPGA_Spartan6/M1_DQ0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3838 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "3" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3582 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
initial import
2010-07-24 14:58:53 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "4" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 102 "/FPGA_Spartan6/M1_DQ1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3326 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "5" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 106 "/FPGA_Spartan6/M1_DQ2"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3070 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "6" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2814 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "7" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 107 "/FPGA_Spartan6/M1_DQ3"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2558 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "8" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 32 "/DDR_Banks/M1_DQ4"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2303 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "9" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2047 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "10" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 33 "/DDR_Banks/M1_DQ5"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1791 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "11" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 108 "/FPGA_Spartan6/M1_DQ6"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1535 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "12" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1279 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "13" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 109 "/FPGA_Spartan6/M1_DQ7"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1023 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "14" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po -767 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "15" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -511 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "16" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 113 "/FPGA_Spartan6/M1_LDQS"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -255 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "17" R 136 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po 0 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "18" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 255 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "19" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po 511 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "20" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 112 "/FPGA_Spartan6/M1_LDM"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 767 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "21" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 37 "/DDR_Banks/M1_WE#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1023 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "22" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 98 "/FPGA_Spartan6/M1_CAS#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1279 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "23" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 34 "/DDR_Banks/M1_RAS#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1535 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "24" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1791 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "25" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2047 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "26" R 137 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 26 "/DDR_Banks/M1_BA0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2302 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "27" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 27 "/DDR_Banks/M1_BA1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2558 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "28" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 23 "/DDR_Banks/M1_A10"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2814 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "29" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 22 "/DDR_Banks/M1_A0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3070 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "30" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 89 "/FPGA_Spartan6/M1_A1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3326 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "31" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 92 "/FPGA_Spartan6/M1_A2"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3582 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "32" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 93 "/FPGA_Spartan6/M1_A3"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3838 2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "33" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 4094 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "34" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 4094 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "35" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 94 "/FPGA_Spartan6/M1_A4"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3838 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "36" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 24 "/DDR_Banks/M1_A5"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3582 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "37" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 95 "/FPGA_Spartan6/M1_A6"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3326 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "38" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 96 "/FPGA_Spartan6/M1_A7"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3070 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "39" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 97 "/FPGA_Spartan6/M1_A8"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2814 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "40" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 25 "/DDR_Banks/M1_A9"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2558 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "41" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 90 "/FPGA_Spartan6/M1_A11"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2303 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "42" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 91 "/FPGA_Spartan6/M1_A12"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2047 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "43" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po 1791 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "44" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 100 "/FPGA_Spartan6/M1_CLK#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1535 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "45" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 28 "/DDR_Banks/M1_CKE"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1279 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "46" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 99 "/FPGA_Spartan6/M1_CLK"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1023 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "47" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 35 "/DDR_Banks/M1_UDM"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 767 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "48" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 511 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "49" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 148 "N-000051"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 255 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "50" R 136 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr footprint changed
2010-08-10 05:29:52 +03:00
Ne 0 ""
Po 0 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "51" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 36 "/DDR_Banks/M1_UDQS"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -255 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "52" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -511 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "53" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -767 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "54" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 110 "/FPGA_Spartan6/M1_DQ8"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1023 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "55" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1279 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "56" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 111 "/FPGA_Spartan6/M1_DQ9"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1535 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "57" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 29 "/DDR_Banks/M1_DQ10"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1791 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "58" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2047 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "59" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 30 "/DDR_Banks/M1_DQ11"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2303 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "60" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 103 "/FPGA_Spartan6/M1_DQ12"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2558 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "61" R 137 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2814 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "62" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 31 "/DDR_Banks/M1_DQ13"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3070 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "63" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 104 "/FPGA_Spartan6/M1_DQ14"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3326 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "64" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3582 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "65" R 138 275 0 0 900
initial import
2010-07-24 14:58:53 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 105 "/FPGA_Spartan6/M1_DQ15"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3838 -2176
initial import
2010-07-24 14:58:53 +03:00
$EndPAD
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "66" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -4094 -2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
$EndMODULE TSOP-66
$MODULE TSOP-66
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 48819 34055 900 15 4C6098A7 4C609B99 ~~
ddr footprint changed
2010-08-10 05:29:52 +03:00
Li TSOP-66
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C609B99
ddr footprint changed
2010-08-10 05:29:52 +03:00
AR /4C421DD3/4C609B99
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"U2"
T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG"
DC -4094 1881 -4094 1822 39 21
DS 4350 -1968 4350 1968 39 21
DS 4350 1968 -4350 1968 39 21
DS -4350 1968 -4350 -1968 39 21
DS -4350 -1968 4350 -1968 39 21
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "1" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -4094 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "2" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 11 "/DDR_Banks/M0_DQ0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3838 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "3" R 138 275 0 0 900
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3582 2176
ddr mobile replaced by ddr
2010-08-04 05:23:17 +03:00
$EndPAD
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "4" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 78 "/FPGA_Spartan6/M0_DQ1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3326 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "5" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 81 "/FPGA_Spartan6/M0_DQ2"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3070 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "6" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2814 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "7" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 16 "/DDR_Banks/M0_DQ3"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2558 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "8" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 17 "/DDR_Banks/M0_DQ4"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2303 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "9" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2047 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "10" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 82 "/FPGA_Spartan6/M0_DQ5"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1791 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "11" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 83 "/FPGA_Spartan6/M0_DQ6"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1535 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "12" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1279 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "13" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 18 "/DDR_Banks/M0_DQ7"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1023 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "14" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -767 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "15" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -511 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "16" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 87 "/FPGA_Spartan6/M0_LDQS"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -255 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "17" R 136 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 0 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "18" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 255 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "19" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 511 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "20" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 86 "/FPGA_Spartan6/M0_LDM"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 767 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "21" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 21 "/DDR_Banks/M0_WE#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1023 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "22" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 77 "/FPGA_Spartan6/M0_CAS#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1279 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "23" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 88 "/FPGA_Spartan6/M0_RAS#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1535 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "24" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1791 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "25" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2047 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "26" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 7 "/DDR_Banks/M0_BA0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2302 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "27" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 76 "/FPGA_Spartan6/M0_BA1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2558 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "28" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 66 "/FPGA_Spartan6/M0_A10"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2814 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "29" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 65 "/FPGA_Spartan6/M0_A0"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3070 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "30" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 5 "/DDR_Banks/M0_A1"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3326 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "31" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 6 "/DDR_Banks/M0_A2"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3582 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "32" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 69 "/FPGA_Spartan6/M0_A3"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3838 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "33" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 4094 2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "34" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 4094 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "35" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 70 "/FPGA_Spartan6/M0_A4"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3838 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "36" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 71 "/FPGA_Spartan6/M0_A5"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3582 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "37" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 72 "/FPGA_Spartan6/M0_A6"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3326 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "38" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 73 "/FPGA_Spartan6/M0_A7"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 3070 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "39" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 74 "/FPGA_Spartan6/M0_A8"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2814 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "40" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 75 "/FPGA_Spartan6/M0_A9"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2558 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "41" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 67 "/FPGA_Spartan6/M0_A11"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2303 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "42" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 68 "/FPGA_Spartan6/M0_A12"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 2047 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "43" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1791 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "44" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 10 "/DDR_Banks/M0_CLK#"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1535 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "45" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 8 "/DDR_Banks/M0_CKE"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1279 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "46" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 9 "/DDR_Banks/M0_CLK"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 1023 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "47" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 19 "/DDR_Banks/M0_UDM"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 767 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "48" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 511 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "49" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 149 "N-000052"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 255 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "50" R 136 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po 0 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "51" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 20 "/DDR_Banks/M0_UDQS"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -255 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "52" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -511 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "53" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -767 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "54" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 84 "/FPGA_Spartan6/M0_DQ8"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1023 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "55" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1279 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "56" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 85 "/FPGA_Spartan6/M0_DQ9"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1535 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "57" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 12 "/DDR_Banks/M0_DQ10"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -1791 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "58" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2047 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "59" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 13 "/DDR_Banks/M0_DQ11"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2303 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "60" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 79 "/FPGA_Spartan6/M0_DQ12"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2558 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "61" R 137 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -2814 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "62" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 14 "/DDR_Banks/M0_DQ13"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3070 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "63" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 80 "/FPGA_Spartan6/M0_DQ14"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3326 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "64" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3582 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "65" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 15 "/DDR_Banks/M0_DQ15"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -3838 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
$PAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
Sh "66" R 138 275 0 0 900
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
ddr footprint changed
2010-08-10 05:29:52 +03:00
Po -4094 -2176
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
$EndPAD
ddr footprint changed
2010-08-10 05:29:52 +03:00
$EndMODULE TSOP-66
annotate
2010-08-10 05:55:50 +03:00
$MODULE 0402
fixed placement
2010-08-13 00:12:57 +03:00
Po 61115 22732 1800 15 4C5FF890 4C5F2D27 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2D27
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2D27
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"R10"
T1 0 150 200 200 1800 40 N I 25 N"1M"
annotate
2010-08-10 05:55:50 +03:00
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 50394 18701 0 0 4C5FF890 4C5D7DC4 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7DC4
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7DC4
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 0 40 M V 20 N"R9"
T1 0 -150 200 200 0 40 M I 20 N"1M"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 50000 24213 0 0 4C5FF890 4C5D71DB ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D71DB
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D71DB
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 0 40 M V 20 N"R8"
T1 0 -150 200 200 0 40 M I 20 N"220"
preliminary placement improved
2010-08-13 14:16:55 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "1" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 161 "N-000336"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "2" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 44 "/Ethernet_Phy/ETH_LED1"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 51575 24213 0 0 4C5FF890 4C5D719D ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D719D
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D719D
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 0 40 M V 20 N"R7"
T1 0 -150 200 200 0 40 M I 20 N"220"
preliminary placement improved
2010-08-13 14:16:55 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "1" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 153 "N-000320"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "2" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 43 "/Ethernet_Phy/ETH_LED0"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 47244 21457 0 0 4C5FF890 4C5D7AF9 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7AF9
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7AF9
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 0 40 M V 20 N"R6"
T1 0 -150 200 200 0 40 M I 20 N"49.9"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 158 "N-000332"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 47244 20866 0 0 4C5FF890 4C5D7AF7 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7AF7
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7AF7
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 0 40 M V 20 N"R5"
T1 0 -150 200 200 0 40 M I 20 N"49.9"
preliminary placement improved
2010-08-13 14:16:55 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "1" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "2" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 155 "N-000323"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 52953 21457 1800 0 4C5FF890 4C5D7AFC ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7AFC
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7AFC
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 1800 40 M V 20 N"R4"
T1 0 -150 200 200 1800 40 M I 20 N"49.9"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 159 "N-000333"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 52953 20866 1800 0 4C5FF890 4C5D7AFE ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7AFE
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7AFE
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 1800 40 M V 20 N"R3"
T1 0 -150 200 200 1800 40 M I 20 N"49.9"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 154 "N-000322"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 49803 25394 1800 0 4C5FF890 4C5D7ECF ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7ECF
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7ECF
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 1800 40 M V 20 N"R2"
T1 0 -150 200 200 1800 40 M I 20 N"6.65K"
preliminary placement improved
2010-08-13 14:16:55 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 157 "N-000331"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 53543 28937 1800 0 4C5FF890 4C5D7F39 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7F39
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7F39
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 1800 40 M V 20 N"R1"
T1 0 -150 200 200 1800 40 M I 20 N"4.7K"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 46 "/Ethernet_Phy/ETH_MDIO"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
fixed placement
2010-08-13 00:12:57 +03:00
Po 61220 23425 1800 15 4C5FF890 4C5F2D1E ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2D1E
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2D1E
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C16"
T1 0 150 200 200 1800 40 N I 25 N"4.7nF"
annotate
2010-08-10 05:55:50 +03:00
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Po 50394 19488 0 0 4C5FF890 4C5D7DCB ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7DCB
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7DCB
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 150 200 200 0 40 M V 20 N"C12"
T1 0 -150 200 200 0 40 M I 20 N"47nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 152 "N-000319"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 51575 27953 1800 0 4C5FF890 4C5D7E43 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7E43
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7E43
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C11"
T1 0 -150 200 200 1800 40 M I 20 N"100nF"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 52559 25984 1800 0 4C5FF890 4C5D7E41 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7E41
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7E41
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C10"
T1 0 -150 200 200 1800 40 M I 20 N"100nF"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
decoupling nand flash added
2010-08-14 02:38:38 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Po 50591 27559 0 0 4C5FF890 4C5D8114 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D8114
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D8114
Op 0 0 0
At SMD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
T0 0 150 200 200 0 40 M V 20 N"C9"
T1 0 -150 200 200 0 40 M I 20 N"C"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Sh "1" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
At SMD N 00440001
Ne 47 "/Ethernet_Phy/ETH_PLL1.8V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Sh "2" R 157 236 0 0 0
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
At SMD N 00440001
Ne 160 "N-000334"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 50590 25984 0 0 4C5FF890 4C5D7FA7 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7FA7
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7FA7
Op 0 0 0
At SMD
preliminary placement improved
2010-08-13 14:16:55 +03:00
T0 0 150 200 200 0 40 M V 20 N"C8"
T1 0 -150 200 200 0 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 40 "/Ethernet_Phy/ETH_A3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
preliminary placement improved
2010-08-13 14:16:55 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 51575 25984 0 0 4C5FF890 4C668981 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Sc 4C668981
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D8104
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 0 40 M V 20 N"C6"
T1 0 -150 200 200 0 40 M I 20 N"C"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 39 "/Ethernet_Phy/ETH_A1.8V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 160 "N-000334"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 44291 29330 0 15 4C5FF890 4C5D7FA3 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7FA3
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7FA3
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C5"
T1 0 150 200 200 0 40 N I 25 N"100nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 51575 26772 1800 0 4C5FF890 4C5D80F0 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D80F0
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D80F0
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C4"
T1 0 -150 200 200 1800 40 M I 20 N"C"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 156 "N-000326"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 160 "N-000334"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 44291 28740 0 15 4C5FF890 4C5D7FA1 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7FA1
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7FA1
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C3"
T1 0 150 200 200 0 40 N I 25 N"100nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 52559 27953 1800 0 4C5FF890 4C5D80ED ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D80ED
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D80ED
Op 0 0 0
At SMD
eth-phy placement
2010-08-14 15:42:37 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C2"
T1 0 -150 200 200 1800 40 M I 20 N"C"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
annotate
2010-08-10 05:55:50 +03:00
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "1" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 38 "/Ethernet_Phy/ETH_1.8V"
annotate
2010-08-10 05:55:50 +03:00
Po -176 0
$EndPAD
$PAD
eth-phy placement
2010-08-14 15:42:37 +03:00
Sh "2" R 157 236 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
eth-phy placement
2010-08-14 15:42:37 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0603
fixed placement
2010-08-13 00:12:57 +03:00
Po 60918 22141 1800 15 4C5FF890 4C5F2CA3 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2CA3
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2CA3
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"V2"
T1 0 150 200 200 1800 40 N I 25 N"V0402MHS03"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 162 "N-000342"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 61280 20050 1800 15 4C5FF890 4C5F2CA7 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2CA7
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2CA7
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"V1"
T1 0 150 200 200 1800 40 N I 25 N"V0402MHS03"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 173 "N-000361"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
fixed placement
2010-08-13 00:12:57 +03:00
Po 59843 22638 1800 15 4C5FF890 4C5F2039 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2039
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2039
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C15"
T1 0 150 200 200 1800 40 N I 25 N"470nF"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 172 "N-000360"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
fixed placement
2010-08-13 00:12:57 +03:00
Po 58465 22441 1800 15 4C5FF890 4C5F2037 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2037
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2037
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C14"
T1 0 150 200 200 1800 40 N I 25 N"1uF"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 172 "N-000360"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
preliminary placement improved
2010-08-13 14:16:55 +03:00
Po 63976 23031 1800 15 4C5FF890 4C5F2033 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2033
annotate
2010-08-10 05:55:50 +03:00
AR /4C5F1EDC/4C5F2033
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C13"
T1 0 150 200 200 1800 40 N I 25 N"1uF"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 172 "N-000360"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
fixed placement
2010-08-13 00:12:57 +03:00
Po 63674 20567 1800 15 4C5FF890 4C5D7FA5 ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7FA5
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7FA5
Op 0 0 0
At SMD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"C7"
T1 0 150 200 200 1800 40 N I 25 N"1uF"
annotate
2010-08-10 05:55:50 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 40 "/Ethernet_Phy/ETH_A3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 197 354 0 0 1800
annotate
2010-08-10 05:55:50 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 44291 29921 0 15 4C5FF890 4C5D7F9F ~~
annotate
2010-08-10 05:55:50 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5D7F9F
annotate
2010-08-10 05:55:50 +03:00
AR /4C4320F3/4C5D7F9F
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C1"
T1 0 150 200 200 0 40 N I 25 N"1uF"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
annotate
2010-08-10 05:55:50 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
annotate
2010-08-10 05:55:50 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
early placement
2010-08-10 06:25:05 +03:00
$MODULE 1210
fixed placement
2010-08-13 00:12:57 +03:00
Po 67126 18110 1800 15 4C5FF890 4C5F2B55 ~~
early placement
2010-08-10 06:25:05 +03:00
Li 1210
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F2B55
early placement
2010-08-10 06:25:05 +03:00
AR /4C5F1EDC/4C5F2B55
Op 0 0 0
At SMD
decoupling nand flash added
2010-08-14 02:38:38 +03:00
T0 0 -150 200 200 1800 40 N V 21 N"F1"
T1 0 150 200 200 1800 40 N I 21 N"MICROSMD075F"
early placement
2010-08-10 06:25:05 +03:00
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 355 984 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 171 "N-000359"
early placement
2010-08-10 06:25:05 +03:00
Po -570 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" R 355 984 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 4 "+5V"
early placement
2010-08-10 06:25:05 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE USB-48204
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 56200 18910 1800 15 4C5F28A8 4C5F23DD ~~
early placement
2010-08-10 06:25:05 +03:00
Li USB-48204
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C5F23DD
early placement
2010-08-10 06:25:05 +03:00
AR /4C5F1EDC/4C5F23DD
Op 0 0 0
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
T0 120 -3162 157 157 1800 20 N V 21 N"J5"
T1 0 118 118 118 0 20 N I 21 N"USB-48204-0001"
early placement
2010-08-10 06:25:05 +03:00
DS -1499 5299 -1704 5299 60 21
DS -1704 5299 -1704 5178 60 21
DS -1704 5178 -1502 5178 60 21
DS 1500 5298 1708 5298 60 21
DS 1708 5298 1707 5180 60 21
DS 1707 5180 1499 5181 60 21
DS -1500 -3000 -1500 5300 60 21
DS -1500 -3000 1500 -3000 60 21
DS 1500 -3000 1500 5300 60 21
DS -1500 5300 1500 5300 60 21
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "1" R 470 470 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 360 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 170 "N-000358"
early placement
2010-08-10 06:25:05 +03:00
Po 0 -2362
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "2" C 470 470 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 360 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 162 "N-000342"
early placement
2010-08-10 06:25:05 +03:00
Po 0 -1575
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "3" C 470 470 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 360 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 173 "N-000361"
early placement
2010-08-10 06:25:05 +03:00
Po 0 -787
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "3" C 470 470 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 360 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 173 "N-000361"
early placement
2010-08-10 06:25:05 +03:00
Po 0 0
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "S1" C 670 670 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 532 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
early placement
2010-08-10 06:25:05 +03:00
Po 1077 287
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "S2" C 670 670 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 532 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
early placement
2010-08-10 06:25:05 +03:00
Po -1077 287
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "S3" C 670 670 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 532 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
early placement
2010-08-10 06:25:05 +03:00
Po 1077 -2468
$EndPAD
$PAD
SD connector attached to th S6
2010-08-11 02:09:38 +03:00
Sh "S4" C 670 670 0 0 1800
early placement
2010-08-10 06:25:05 +03:00
Dr 532 0 0
At STD N 0CC0FFFF
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 163 "N-000343"
early placement
2010-08-10 06:25:05 +03:00
Po -1077 -2468
$EndPAD
$EndMODULE USB-48204
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 47441 32874 900 0 4C5FF890 4C61CC73 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CC73
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CC73
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 900 40 M V 20 N"C17"
T1 0 -150 200 200 900 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 900
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 900
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 149 "N-000052"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 47441 33661 2700 0 4C5FF890 4C61CC96 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CC96
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CC96
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 2700 40 M V 20 N"C18"
T1 0 -150 200 200 2700 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 2700
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 149 "N-000052"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 2700
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 150 "N-000054"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 62205 33858 0 0 4C5FF890 4C61CCE2 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CCE2
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CCE2
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 0 40 M V 20 N"C20"
T1 0 -150 200 200 0 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 148 "N-000051"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 147 "N-000050"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 62205 33071 1800 0 4C5FF890 4C61CCE3 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CCE3
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CCE3
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C19"
T1 0 -150 200 200 1800 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 148 "N-000051"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 48031 32874 900 0 4C5FF890 4C61CD4A ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CD4A
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CD4A
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 900 40 M V 20 N"R11"
T1 0 -150 200 200 900 40 M I 20 N"1K_1%"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 900
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 900
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 149 "N-000052"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 48031 33661 2700 0 4C5FF890 4C61CDB5 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CDB5
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CDB5
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 2700 40 M V 20 N"R12"
T1 0 -150 200 200 2700 40 M I 20 N"1K_1%"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 2700
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 149 "N-000052"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 2700
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 150 "N-000054"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 62205 32677 1800 0 4C5FF890 4C61CE31 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CE31
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CE31
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 1800 40 M V 20 N"R13"
T1 0 -150 200 200 1800 40 M I 20 N"1K_1%"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 148 "N-000051"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 50591 37598 1800 0 4C5FF890 4C61CEB9 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CEB9
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CEB9
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C22"
T1 0 -150 200 200 1800 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 50591 38189 1800 0 4C5FF890 4C61CEF7 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CEF7
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CEF7
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C23"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 50591 29921 1800 0 4C5FF890 4C61CF16 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CF16
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CF16
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C25"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 47441 37008 0 0 4C5FF890 4C61CF17 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CF17
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CF17
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 0 40 M V 20 N"C24"
T1 0 -150 200 200 0 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 47441 35433 0 0 4C5FF890 4C61CF27 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CF27
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CF27
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 0 40 M V 20 N"C26"
T1 0 -150 200 200 0 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 65354 38189 1800 0 4C5FF890 4C61CFA1 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA1
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA1
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C32"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 65354 33858 1800 0 4C5FF890 4C61CFA2 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA2
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA2
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C30"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 65354 37598 1800 0 4C5FF890 4C61CFA3 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA3
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA3
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 1800 40 M V 20 N"C31"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "1" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Sh "2" R 157 236 0 0 1800
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 62205 36811 0 0 4C5FF890 4C61CFA4 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA4
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA4
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 0 40 M V 20 N"C29"
T1 0 -150 200 200 0 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Po 62205 35433 0 0 4C5FF890 4C61CFA5 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA5
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA5
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 0 40 M V 20 N"C28"
T1 0 -150 200 200 0 40 M I 20 N"100nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0603
improved placement
2010-08-14 06:09:52 +03:00
Po 49016 29921 0 0 4C5FF890 4C61CF2F ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CF2F
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CF2F
Op 0 0 0
At SMD
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
T0 0 150 200 200 0 40 M V 20 N"C21"
T1 0 -150 200 200 0 40 M I 20 N"1uF"
DS -443 -227 -443 227 50 20
DS -443 227 443 227 50 20
DS 443 227 443 -227 50 20
DS 443 -227 -443 -227 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
fixed placement
2010-08-13 00:12:57 +03:00
Po 66339 29331 0 15 4C5FF890 4C61CFA0 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0603
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CFA0
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CFA0
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C27"
T1 0 150 200 200 0 40 N I 25 N"1uF"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 62205 33465 0 0 4C5FF890 4C61CE30 ~~
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Li 0402
Fixing USB connections
2010-08-11 05:25:32 +03:00
Sc 4C61CE30
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
AR /4C421DD3/4C61CE30
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 150 200 200 0 40 M V 20 N"R14"
T1 0 -150 200 200 0 40 M I 20 N"1K_1%"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 148 "N-000051"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
improved placement
2010-08-14 06:09:52 +03:00
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 147 "N-000050"
DDR de-coupling caps. added
2010-08-11 01:38:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
fixed placement
2010-08-13 00:12:57 +03:00
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 58920 19610 0 15 4C5FF890 4C63F248 ~~
fixed placement
2010-08-13 00:12:57 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C63F248
fixed placement
2010-08-13 00:12:57 +03:00
AR /4C5F1EDC/4C63F248
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"L5"
T1 0 150 200 200 0 40 N I 25 N"FB"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 166 "N-000354"
fixed placement
2010-08-13 00:12:57 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
fixed placement
2010-08-13 00:12:57 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 63977 19488 0 15 4C5FF890 4C63F252 ~~
fixed placement
2010-08-13 00:12:57 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C63F252
fixed placement
2010-08-13 00:12:57 +03:00
AR /4C5F1EDC/4C63F252
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"L4"
T1 0 150 200 200 0 40 N I 25 N"FB"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 171 "N-000359"
fixed placement
2010-08-13 00:12:57 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 170 "N-000358"
fixed placement
2010-08-13 00:12:57 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
usb added
2010-08-13 17:27:10 +03:00
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 65770 21890 0 15 4C5FF890 4C6552B0 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B0
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B0
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"L6"
T1 0 150 200 200 0 40 N I 25 N"FB"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 164 "N-000346"
usb added
2010-08-13 17:27:10 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 67040 22310 0 15 4C5FF890 4C6552B1 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B1
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B1
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"L7"
T1 0 150 200 200 0 40 N I 25 N"FB"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 69610 22370 0 15 4C5FF890 4C6552B6 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B6
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B6
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"R15"
T1 0 150 200 200 0 40 N I 25 N"1M"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 169 "N-000357"
usb added
2010-08-13 17:27:10 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 67770 21890 0 15 4C5FF890 4C6552B7 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B7
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B7
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C38"
T1 0 150 200 200 0 40 N I 25 N"4.7nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 169 "N-000357"
usb added
2010-08-13 17:27:10 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 65530 23810 0 15 4C5FF890 4C6552BC ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0402
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552BC
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552BC
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C37"
T1 0 150 200 200 0 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 168 "N-000356"
usb added
2010-08-13 17:27:10 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 68250 27490 0 15 4C5FF890 4C6552B9 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B9
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B9
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"V4"
T1 0 150 200 200 0 40 N I 25 N"V0402MHS03"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 167 "N-000355"
usb added
2010-08-13 17:27:10 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 68330 28770 0 15 4C5FF890 4C6552B8 ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0603
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552B8
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552B8
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"V3"
T1 0 150 200 200 0 40 N I 25 N"V0402MHS03"
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
Sh "1" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 165 "N-000350"
usb added
2010-08-13 17:27:10 +03:00
Po -294 0
$EndPAD
$PAD
Sh "2" R 197 354 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 294 0
$EndPAD
$EndMODULE 0603
$MODULE 0805
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 68490 25410 0 15 4C5FF890 4C6552BD ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0805
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552BD
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552BD
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C36"
T1 0 150 200 200 0 40 N I 25 N"1uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 168 "N-000356"
usb added
2010-08-13 17:27:10 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 66130 25290 0 15 4C5FF890 4C6552BE ~~
usb added
2010-08-13 17:27:10 +03:00
Li 0805
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552BE
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552BE
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C35"
T1 0 150 200 200 0 40 N I 25 N"1uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 168 "N-000356"
usb added
2010-08-13 17:27:10 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
usb added
2010-08-13 17:27:10 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 1210
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 67160 19800 1800 15 4C5FF890 4C6552BA ~~
usb added
2010-08-13 17:27:10 +03:00
Li 1210
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552BA
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552BA
Op 0 0 0
At SMD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
T0 0 -150 200 200 1800 40 N V 25 N"F2"
T1 0 150 200 200 1800 40 N I 25 N"MICROSMD075F"
usb added
2010-08-13 17:27:10 +03:00
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "1" R 355 984 0 0 1800
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 164 "N-000346"
usb added
2010-08-13 17:27:10 +03:00
Po -570 0
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "2" R 355 984 0 0 1800
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 4 "+5V"
usb added
2010-08-13 17:27:10 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE TSSOP-14
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 63080 25950 2700 0 4C6559CC 4C6552BF ~~
usb added
2010-08-13 17:27:10 +03:00
Li TSSOP-14
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sc 4C6552BF
usb added
2010-08-13 17:27:10 +03:00
AR /4C5F1EDC/4C6552BF
Op 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
T0 50 1822 276 276 2700 69 M V 20 N"U7"
T1 70 -1848 276 276 2700 69 M I 20 N"MIC2550AYTS"
DC -738 -409 -666 -418 150 20
DS 987 -634 -984 -628 150 20
DS -984 -628 -984 -187 150 20
DS -984 -187 -726 -187 150 20
DS -726 -187 -726 185 150 20
DS -726 185 -987 188 150 20
DS -987 188 -984 649 150 20
DS -984 649 982 650 150 20
DS 982 650 986 -634 150 20
DS -984 787 984 787 1 20
DS 984 787 984 -787 1 20
DS -984 -787 984 -787 1 20
DS -984 787 -984 -787 1 20
$PAD
Sh "1" R 137 570 0 0 900
Dr 0 0 0
At SMD N 00440001
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -767 -1112
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "2" R 137 570 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
At SMD N 00440001
usb added
2010-08-13 17:27:10 +03:00
Ne 0 ""
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -511 -1112
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "3" R 137 570 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
At SMD N 00440001
usb added
2010-08-13 17:27:10 +03:00
Ne 0 ""
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -255 -1112
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "4" R 137 570 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
At SMD N 00440001
usb added
2010-08-13 17:27:10 +03:00
Ne 0 ""
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 0 -1112
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "5" R 137 570 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
At SMD N 00440001
usb added
2010-08-13 17:27:10 +03:00
Ne 0 ""
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 255 -1112
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "6" R 137 570 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
At SMD N 00440001
Ne 0 ""
Po 511 -1112
$EndPAD
$PAD
Sh "7" R 137 570 0 0 900
Dr 0 0 0
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 767 -1112
$EndPAD
$PAD
Sh "8" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 767 1112
$EndPAD
$PAD
Sh "9" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
usb added
2010-08-13 17:27:10 +03:00
Ne 0 ""
Po 511 1112
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "10" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 167 "N-000355"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 255 1112
$EndPAD
$PAD
Sh "11" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 165 "N-000350"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 0 1112
$EndPAD
$PAD
Sh "12" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -255 1112
$EndPAD
$PAD
Sh "13" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
Ne 0 ""
Po -511 1112
$EndPAD
$PAD
Sh "14" R 137 570 0 0 2700
Dr 0 0 0
At SMD N 00440001
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 145 "3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -767 1112
$EndPAD
$EndMODULE TSSOP-14
$MODULE 0402
Po 66700 44860 900 15 4C5FF890 4C656D53 ~~
Li 0402
Sc 4C656D53
AR /4C431A63/4C656D53
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C69"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
usb added
2010-08-13 17:27:10 +03:00
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "1" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "2" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
$EndMODULE 0402
$MODULE 0402
Po 69080 44510 900 15 4C5FF890 4C656D08 ~~
Li 0402
Sc 4C656D08
AR /4C431A63/4C656D08
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C68"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
usb added
2010-08-13 17:27:10 +03:00
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "1" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "2" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
$EndMODULE 0402
$MODULE 0402
Po 66000 44830 900 15 4C5FF890 4C656D49 ~~
Li 0402
Sc 4C656D49
AR /4C431A63/4C656D49
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C67"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
usb added
2010-08-13 17:27:10 +03:00
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "1" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
$PAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Sh "2" R 157 236 0 0 900
usb added
2010-08-13 17:27:10 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
usb added
2010-08-13 17:27:10 +03:00
$EndPAD
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
$EndMODULE 0402
$MODULE 0402
Po 62600 45140 900 15 4C5FF890 4C656D9D ~~
Li 0402
Sc 4C656D9D
AR /4C431A63/4C656D9D
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C66"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 68270 44580 900 15 4C5FF890 4C656CFC ~~
Li 0402
Sc 4C656CFC
AR /4C431A63/4C656CFC
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C65"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 65190 44860 900 15 4C5FF890 4C656D46 ~~
Li 0402
Sc 4C656D46
AR /4C431A63/4C656D46
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C64"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 61240 45110 900 15 4C5FF890 4C656D9A ~~
Li 0402
Sc 4C656D9A
AR /4C431A63/4C656D9A
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C63"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 67770 44740 900 15 4C5FF890 4C656CFB ~~
Li 0402
Sc 4C656CFB
AR /4C431A63/4C656CFB
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C62"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 64550 44960 900 15 4C5FF890 4C656D45 ~~
Li 0402
Sc 4C656D45
AR /4C431A63/4C656D45
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C61"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 62000 45050 900 15 4C5FF890 4C656D99 ~~
Li 0402
Sc 4C656D99
AR /4C431A63/4C656D99
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C60"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 54760 44960 900 15 4C5FF890 4C656C49 ~~
Li 0402
Sc 4C656C49
AR /4C431A63/4C656C49
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C53"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 54080 44960 900 15 4C5FF890 4C656BFA ~~
Li 0402
Sc 4C656BFA
AR /4C431A63/4C656BFA
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C52"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 53330 45030 900 15 4C5FF890 4C656C27 ~~
Li 0402
Sc 4C656C27
AR /4C431A63/4C656C27
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C51"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 57160 45200 900 15 4C5FF890 4C656CBB ~~
Li 0402
Sc 4C656CBB
AR /4C431A63/4C656CBB
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C50"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 3 "+3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 55360 44960 900 15 4C5FF890 4C656C24 ~~
Li 0402
Sc 4C656C24
AR /4C431A63/4C656C24
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C49"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 50080 45180 900 15 4C5FF890 4C656AC2 ~~
Li 0402
Sc 4C656AC2
AR /4C431A63/4C656AC2
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C48"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 57880 45250 900 15 4C5FF890 4C656CBA ~~
Li 0402
Sc 4C656CBA
AR /4C431A63/4C656CBA
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C47"
T1 0 150 200 200 900 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 3 "+3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0805
Po 67830 46520 900 15 4C5FF890 4C656CFA ~~
Li 0805
Sc 4C656CFA
AR /4C431A63/4C656CFA
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C59"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 64620 46590 900 15 4C5FF890 4C656D44 ~~
Li 0805
Sc 4C656D44
AR /4C431A63/4C656D44
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C58"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 62000 46660 900 15 4C5FF890 4C656D98 ~~
Li 0805
Sc 4C656D98
AR /4C431A63/4C656D98
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C57"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 54900 47130 900 15 4C5FF890 4C656C16 ~~
Li 0805
Sc 4C656C16
AR /4C431A63/4C656C16
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C46"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 57450 46990 900 15 4C5FF890 4C656CB9 ~~
Li 0805
Sc 4C656CB9
AR /4C431A63/4C656CB9
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C44"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 3 "+3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 54030 46900 900 15 4C5FF890 4C656BF9 ~~
Li 0805
Sc 4C656BF9
AR /4C431A63/4C656BF9
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C43"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 0805
Po 49920 46890 900 15 4C5FF890 4C656ABD ~~
Li 0805
Sc 4C656ABD
AR /4C431A63/4C656ABD
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C42"
T1 0 150 200 200 900 40 N I 25 N"4.7uF"
DS -561 305 -561 -305 50 21
DS -561 -305 561 -305 50 21
DS 561 -305 561 305 50 21
DS 561 305 -561 305 50 21
$PAD
Sh "1" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -373 0
$EndPAD
$PAD
Sh "2" R 275 510 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 373 0
$EndPAD
$EndMODULE 0805
$MODULE 1210
Po 67820 48920 900 15 4C5FF890 4C656CF9 ~~
Li 1210
Sc 4C656CF9
AR /4C431A63/4C656CF9
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C56"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 1210
Po 64630 49060 900 15 4C5FF890 4C656D43 ~~
Li 1210
Sc 4C656D43
AR /4C431A63/4C656D43
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C55"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 1210
Po 62010 49200 900 15 4C5FF890 4C656D97 ~~
Li 1210
Sc 4C656D97
AR /4C431A63/4C656D97
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C54"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 1210
Po 57650 49210 900 15 4C5FF890 4C656CB7 ~~
Li 1210
Sc 4C656CB7
AR /4C431A63/4C656CB7
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C41"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 3 "+3.3V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 1210
Po 54100 49160 900 15 4C5FF890 4C656BF8 ~~
Li 1210
Sc 4C656BF8
AR /4C431A63/4C656BF8
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C40"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 2 "+2.5V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 1210
Po 50490 49120 900 15 4C5FF890 4C656A80 ~~
Li 1210
Sc 4C656A80
AR /4C431A63/4C656A80
Op 0 0 0
At SMD
T0 0 -150 200 200 900 40 N V 25 N"C39"
T1 0 150 200 200 900 40 N I 25 N"100uF"
DS -798 542 -798 -542 50 21
DS -798 -542 798 -542 50 21
DS 798 -542 798 542 50 21
DS 798 542 -798 542 50 21
$PAD
Sh "1" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 984 0 0 900
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 570 0
$EndPAD
$EndMODULE 1210
$MODULE 0402
spi memory added
2010-08-13 23:42:35 +03:00
Po 45669 44882 0 15 4C5FF890 4C656AC0 ~~
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Li 0402
Sc 4C656AC0
AR /4C431A63/4C656AC0
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"C45"
T1 0 150 200 200 0 40 N I 25 N"470nF"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
spi memory added
2010-08-13 23:42:35 +03:00
Ne 1 "+1.2V"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
spi memory added
2010-08-13 23:42:35 +03:00
$MODULE 1206
Po 49016 39173 1800 15 4C5FF890 4C61D151 ~~
Li 1206
Sc 4C61D151
AR /4C421DD3/4C61D151
Op 0 0 0
At SMD
T0 0 -150 200 200 1800 40 N V 25 N"C33"
T1 0 150 200 200 1800 40 N I 25 N"10uF"
DS -798 384 -798 -384 50 21
DS -798 -384 798 -384 50 21
DS 798 -384 798 384 50 21
DS 798 384 -798 384 50 21
$PAD
Sh "1" R 355 668 0 0 1800
Dr 0 0 0
At SMD N 00888000
Ne 2 "+2.5V"
Po -570 0
$EndPAD
$PAD
Sh "2" R 355 668 0 0 1800
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po 570 0
$EndPAD
$EndMODULE 1206
$MODULE SO8E
VCC fixed
2010-08-14 01:34:12 +03:00
Po 57087 39961 2700 15 42806F54 4C65A876 ~~
spi memory added
2010-08-13 23:42:35 +03:00
Li SO8E
Cd module CMS SOJ 8 pins etroit
Kw CMS SOJ
Sc 4C65A876
AR /4C4227FE/4C65A75D
Op 0 0 0
At SMD
VCC fixed
2010-08-14 01:34:12 +03:00
T0 0 -350 450 450 2700 60 N V 21 N"U8"
T1 0 400 350 350 2700 60 N V 21 N"X25X64MB"
spi memory added
2010-08-13 23:42:35 +03:00
DS -1050 700 -1050 750 50 21
DS -1050 750 1050 750 50 21
DS 1050 -750 -1050 -750 50 21
DS -1050 -750 -1050 700 50 21
DS -1050 -200 -850 -200 50 21
DS -850 -200 -850 200 50 21
DS -850 200 -1050 200 50 21
DS 1050 -750 1050 750 50 21
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "8" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
Ne 174 "VCCO2"
spi memory added
2010-08-13 23:42:35 +03:00
Po -750 -1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "1" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 123 "/FPGA_Spartan6/PROG_CSO"
spi memory added
2010-08-13 23:42:35 +03:00
Po -750 1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "7" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 127 "/FPGA_Spartan6/PROG_MISO3"
spi memory added
2010-08-13 23:42:35 +03:00
Po -250 -1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "6" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 122 "/FPGA_Spartan6/PROG_CCLK"
spi memory added
2010-08-13 23:42:35 +03:00
Po 250 -1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "5" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 124 "/FPGA_Spartan6/PROG_MISO0"
spi memory added
2010-08-13 23:42:35 +03:00
Po 750 -1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "2" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 125 "/FPGA_Spartan6/PROG_MISO1"
spi memory added
2010-08-13 23:42:35 +03:00
Po -250 1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "3" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 126 "/FPGA_Spartan6/PROG_MISO2"
spi memory added
2010-08-13 23:42:35 +03:00
Po 250 1050
$EndPAD
$PAD
VCC fixed
2010-08-14 01:34:12 +03:00
Sh "4" R 200 450 0 0 2700
spi memory added
2010-08-13 23:42:35 +03:00
Dr 0 0 0
At SMD N 00888000
VCC fixed
2010-08-14 01:34:12 +03:00
Ne 146 "GND"
spi memory added
2010-08-13 23:42:35 +03:00
Po 750 1050
$EndPAD
$SHAPE3D
Na "smd/cms_so8.wrl"
Sc 0.500000 0.320000 0.500000
Of 0.000000 0.000000 0.000000
Ro 0.000000 0.000000 0.000000
$EndSHAPE3D
$EndMODULE SO8E
decoupling DDR cap. placement
2010-08-14 02:20:50 +03:00
$MODULE 0402
Po 65354 29921 1800 0 4C5FF890 4C65D2EF ~~
Li 0402
Sc 4C65D2EF
AR /4C421DD3/4C65D28E
Op 0 0 0
At SMD
T0 0 150 200 200 1800 40 M V 20 N"C71"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
$PAD
Sh "1" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 2 "+2.5V"
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 146 "GND"
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 50591 34646 1800 0 4C5FF890 4C65D2F1 ~~
Li 0402
Sc 4C65D2F1
AR /4C421DD3/4C65D2A9
Op 0 0 0
At SMD
T0 0 150 200 200 1800 40 M V 20 N"C70"
T1 0 -150 200 200 1800 40 M I 20 N"10nF"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
$PAD
Sh "1" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 2 "+2.5V"
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
Ne 146 "GND"
Po 176 0
$EndPAD
$EndMODULE 0402
decoupling nand flash added
2010-08-14 02:38:38 +03:00
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 54528 26181 900 15 4C5FF890 4C65D736 ~~
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Li 0402
Sc 4C65D736
AR /4C4227FE/4C65D661
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 -150 200 200 900 40 N V 25 N"C72"
T1 0 150 200 200 900 40 N I 25 N"100nF"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 900
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 3 "+3.3V"
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 900
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 146 "GND"
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
Po 63780 26575 2700 15 4C5FF890 4C65D738 ~~
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Li 0402
Sc 4C65D738
AR /4C4227FE/4C65D67C
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 -150 200 200 2700 40 N V 25 N"C73"
T1 0 150 200 200 2700 40 N I 25 N"100nF"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 157 236 0 0 2700
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 3 "+3.3V"
Po -176 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 157 236 0 0 2700
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 146 "GND"
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0603
improved placement
2010-08-14 06:09:52 +03:00
Po 54528 24803 900 15 4C5FF890 4C65D739 ~~
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Li 0603
Sc 4C65D739
AR /4C4227FE/4C65D681
Op 0 0 0
At SMD
improved placement
2010-08-14 06:09:52 +03:00
T0 0 -150 200 200 900 40 N V 25 N"C74"
T1 0 150 200 200 900 40 N I 25 N"1uF"
decoupling nand flash added
2010-08-14 02:38:38 +03:00
DS -443 227 -443 -227 50 21
DS -443 -227 443 -227 50 21
DS 443 -227 443 227 50 21
DS 443 227 -443 227 50 21
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "1" R 197 354 0 0 900
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 3 "+3.3V"
Po -294 0
$EndPAD
$PAD
improved placement
2010-08-14 06:09:52 +03:00
Sh "2" R 197 354 0 0 900
decoupling nand flash added
2010-08-14 02:38:38 +03:00
Dr 0 0 0
At SMD N 00888000
Ne 146 "GND"
Po 294 0
$EndPAD
$EndMODULE 0603
eth-phy placement
2010-08-14 15:42:37 +03:00
$MODULE 0402
Po 44291 28149 0 15 4C5FF890 4C5D7FB7 ~~
Li 0402
Sc 4C5D7FB7
AR /4C4320F3/4C5D7FB7
Op 0 0 0
At SMD
T0 0 -150 200 200 0 40 N V 25 N"L2"
T1 0 150 200 200 0 40 N I 25 N"FB"
DS -305 168 -305 -168 50 21
DS -305 -168 305 -168 50 21
DS 305 -168 305 168 50 21
DS 305 168 -305 168 50 21
$PAD
Sh "1" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 145 "3.3V"
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 0
Dr 0 0 0
At SMD N 00888000
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 40 "/Ethernet_Phy/ETH_A3.3V"
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
Po 51575 26378 1800 0 4C5FF890 4C5D80F3 ~~
Li 0402
Sc 4C5D80F3
AR /4C4320F3/4C5D80F3
Op 0 0 0
At SMD
T0 0 150 200 200 1800 40 M V 20 N"L1"
T1 0 -150 200 200 1800 40 M I 20 N"INDUCTOR"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
$PAD
Sh "1" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 156 "N-000326"
eth-phy placement
2010-08-14 15:42:37 +03:00
Po -176 0
$EndPAD
$PAD
Sh "2" R 157 236 0 0 1800
Dr 0 0 0
At SMD N 00440001
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Ne 39 "/Ethernet_Phy/ETH_A1.8V"
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
$MODULE 0402
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Po 50591 27165 1800 0 4C5FF890 4C5D810A ~~
eth-phy placement
2010-08-14 15:42:37 +03:00
Li 0402
Sc 4C5D810A
AR /4C4320F3/4C5D810A
Op 0 0 0
At SMD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
T0 0 150 200 200 1800 40 M V 20 N"L3"
T1 0 -150 200 200 1800 40 M I 20 N"INDUCTOR"
DS -305 -168 -305 168 50 20
DS -305 168 305 168 50 20
DS 305 168 305 -168 50 20
DS 305 -168 -305 -168 50 20
eth-phy placement
2010-08-14 15:42:37 +03:00
$PAD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Sh "1" R 157 236 0 0 1800
eth-phy placement
2010-08-14 15:42:37 +03:00
Dr 0 0 0
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
At SMD N 00440001
Ne 39 "/Ethernet_Phy/ETH_A1.8V"
eth-phy placement
2010-08-14 15:42:37 +03:00
Po -176 0
$EndPAD
$PAD
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
Sh "2" R 157 236 0 0 1800
eth-phy placement
2010-08-14 15:42:37 +03:00
Dr 0 0 0
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
At SMD N 00440001
Ne 47 "/Ethernet_Phy/ETH_PLL1.8V"
eth-phy placement
2010-08-14 15:42:37 +03:00
Po 176 0
$EndPAD
$EndMODULE 0402
improved placement
2010-08-14 06:09:52 +03:00
$TEXTPCB
Te "otra fuente"
Po 65945 22244 600 800 120 0
De 0 1 0 Normal
$EndTEXTPCB
$TEXTPCB
Te "Una fuente por acá"
Po 44291 26772 600 800 120 0
De 0 1 0 Normal
$EndTEXTPCB
fixed placement
2010-08-13 00:12:57 +03:00
$COTATION
Ge 0 24 0
Va 21654
Te "55.001 mm"
Po 56693 42174 600 800 120 0 1
Sb 0 45866 41534 67520 41534 120
Sd 0 67520 40748 67520 42814 120
Sg 0 45866 40748 45866 42814 120
S1 0 67520 41534 67077 41764 120
S2 0 67520 41534 67077 41304 120
S3 0 45866 41534 46309 41764 120
S4 0 45866 41534 46309 41304 120
spi memory added
2010-08-13 23:42:35 +03:00
$endCOTATION
fixed placement
2010-08-13 00:12:57 +03:00
$COTATION
Ge 0 24 0
Va 32087
Te "81.501 mm"
Po 75442 29232 600 800 120 2700 1
Sb 0 74802 13189 74802 45276 120
Sd 0 70276 45276 76082 45276 120
Sg 0 70276 13189 76082 13189 120
S1 0 74802 45276 74572 44833 120
S2 0 74802 45276 75032 44833 120
S3 0 74802 13189 74572 13632 120
S4 0 74802 13189 75032 13632 120
spi memory added
2010-08-13 23:42:35 +03:00
$endCOTATION
initial import
2010-07-24 14:58:53 +03:00
$TRACK
$EndTRACK
$ZONE
$EndZONE
improved placement
2010-08-14 06:09:52 +03:00
$CZONE_OUTLINE
ZInfo 4C65DF3E 0 ""
ZLayer 15
ZAux 4 N
ZClearance 200 T
ZMinThickness 100
fixed FPGA component bug
2010-08-14 16:23:56 +03:00
ZOptions 0 16 F 200 200
improved placement
2010-08-14 06:09:52 +03:00
ZCorner 67126 44685 0
ZCorner 67126 14567 0
ZCorner 45079 14567 0
ZCorner 45079 44685 1
$endCZONE_OUTLINE
initial import
2010-07-24 14:58:53 +03:00
$EndBOARD
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