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mirror of git://projects.qi-hardware.com/xue.git synced 2024-07-24 23:28:47 +03:00

decoupling DDR cap. placement

This commit is contained in:
Andres Calderon 2010-08-13 18:20:50 -05:00
parent 333097ec1d
commit 8f8f332469
9 changed files with 1934 additions and 1817 deletions

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT
EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001
@ -56,8 +56,16 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 8000 7300 0 60 ~ 0
Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
Connection ~ 4050 6200
Wire Wire Line
4350 6200 2200 6200
Wire Wire Line
4350 6200 4350 6100
Connection ~ 9300 6200
Wire Wire Line
9600 6100 9600 6200
Wire Wire Line
9600 6200 7450 6200
Wire Bus Line
4800 3750 4800 5350
Wire Wire Line
@ -421,17 +429,13 @@ Connection ~ 10150 1600
Wire Wire Line
10150 2100 10150 1950
Wire Wire Line
2200 6100 2200 6200
Wire Wire Line
2200 6200 4050 6200
2200 6200 2200 6100
Wire Wire Line
4050 6200 4050 6100
Wire Wire Line
4050 5900 4050 5800
4050 5800 4050 5900
Wire Wire Line
4050 5800 2200 5800
Wire Wire Line
2200 5800 2200 5900
2200 5900 2200 5800
Wire Wire Line
2600 6100 2600 6200
Connection ~ 2600 6200
@ -460,14 +464,10 @@ Wire Wire Line
7850 6100 7850 6200
Wire Wire Line
7450 5900 7450 5800
Wire Wire Line
7450 5800 9300 5800
Wire Wire Line
9300 5800 9300 5900
Wire Wire Line
9300 6100 9300 6200
Wire Wire Line
9300 6200 7450 6200
9300 6200 9300 6100
Wire Wire Line
7450 6200 7450 6100
Wire Wire Line
@ -484,6 +484,38 @@ Wire Wire Line
3050 1750 3050 1800
Wire Bus Line
10050 3750 10050 5400
Wire Wire Line
9600 5900 9600 5800
Wire Wire Line
9600 5800 7450 5800
Connection ~ 9300 5800
Wire Wire Line
2200 5800 4350 5800
Wire Wire Line
4350 5800 4350 5900
Connection ~ 4050 5800
$Comp
L CAP C70
U 1 1 4C65D2A9
P 4350 6000
F 0 "C70" H 4400 6100 50 0000 L CNN
F 1 "10nF" H 4400 5900 50 0000 L CNN
F 2 "0402" H 4350 6000 60 0001 C CNN
1 4350 6000
1 0 0 -1
$EndComp
$Comp
L CAP C71
U 1 1 4C65D28E
P 9600 6000
F 0 "C71" H 9650 6100 50 0000 L CNN
F 1 "10nF" H 9650 5900 50 0000 L CNN
F 2 "0402" H 9600 6000 60 0001 C CNN
1 9600 6000
1 0 0 -1
$EndComp
Text Notes 8000 7300 0 60 ~ 0
Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
Entry Wire Line
6650 4750 6750 4650
Entry Wire Line
@ -501,37 +533,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR039
L GND #PWR038
U 1 1 4C61D1D3
P 6900 6200
F 0 "#PWR039" H 6900 6200 30 0001 C CNN
F 0 "#PWR038" H 6900 6200 30 0001 C CNN
F 1 "GND" H 6900 6130 30 0001 C CNN
1 6900 6200
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR040
L +2.5V #PWR039
U 1 1 4C61D1D2
P 6900 5800
F 0 "#PWR040" H 6900 5750 20 0001 C CNN
F 0 "#PWR039" H 6900 5750 20 0001 C CNN
F 1 "+2.5V" H 6900 5900 30 0000 C CNN
1 6900 5800
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR041
L +2.5V #PWR040
U 1 1 4C61D192
P 1700 5800
F 0 "#PWR041" H 1700 5750 20 0001 C CNN
F 0 "#PWR040" H 1700 5750 20 0001 C CNN
F 1 "+2.5V" H 1700 5900 30 0000 C CNN
1 1700 5800
1 0 0 -1
$EndComp
$Comp
L GND #PWR042
L GND #PWR041
U 1 1 4C61D17F
P 1700 6200
F 0 "#PWR042" H 1700 6200 30 0001 C CNN
F 0 "#PWR041" H 1700 6200 30 0001 C CNN
F 1 "GND" H 1700 6130 30 0001 C CNN
1 1700 6200
1 0 0 -1
@ -547,19 +579,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR043
L +2.5V #PWR042
U 1 1 4C61CFCF
P 3050 1750
F 0 "#PWR043" H 3050 1700 20 0001 C CNN
F 0 "#PWR042" H 3050 1700 20 0001 C CNN
F 1 "+2.5V" H 3050 1850 30 0000 C CNN
1 3050 1750
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR044
L +2.5V #PWR043
U 1 1 4C61CFC6
P 8300 1750
F 0 "#PWR044" H 8300 1700 20 0001 C CNN
F 0 "#PWR043" H 8300 1700 20 0001 C CNN
F 1 "+2.5V" H 8300 1850 30 0000 C CNN
1 8300 1750
1 0 0 -1
@ -625,37 +657,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR045
L +2.5V #PWR044
U 1 1 4C61CF9F
P 8300 5750
F 0 "#PWR045" H 8300 5700 20 0001 C CNN
F 0 "#PWR044" H 8300 5700 20 0001 C CNN
F 1 "+2.5V" H 8300 5850 30 0000 C CNN
1 8300 5750
1 0 0 -1
$EndComp
$Comp
L GND #PWR046
L GND #PWR045
U 1 1 4C61CF9E
P 8300 6350
F 0 "#PWR046" H 8300 6350 30 0001 C CNN
F 0 "#PWR045" H 8300 6350 30 0001 C CNN
F 1 "GND" H 8300 6280 30 0001 C CNN
1 8300 6350
1 0 0 -1
$EndComp
$Comp
L GND #PWR047
L GND #PWR046
U 1 1 4C61CF90
P 3050 6350
F 0 "#PWR047" H 3050 6350 30 0001 C CNN
F 0 "#PWR046" H 3050 6350 30 0001 C CNN
F 1 "GND" H 3050 6280 30 0001 C CNN
1 3050 6350
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR048
L +2.5V #PWR047
U 1 1 4C61CF89
P 3050 5750
F 0 "#PWR048" H 3050 5700 20 0001 C CNN
F 0 "#PWR047" H 3050 5700 20 0001 C CNN
F 1 "+2.5V" H 3050 5850 30 0000 C CNN
1 3050 5750
1 0 0 -1
@ -741,19 +773,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR049
L +2.5V #PWR048
U 1 1 4C61CE2F
P 9850 1000
F 0 "#PWR049" H 9850 950 20 0001 C CNN
F 0 "#PWR048" H 9850 950 20 0001 C CNN
F 1 "+2.5V" H 9850 1100 30 0000 C CNN
1 9850 1000
1 0 0 -1
$EndComp
$Comp
L +2.5V #PWR050
L +2.5V #PWR049
U 1 1 4C61CDF1
P 4550 900
F 0 "#PWR050" H 4550 850 20 0001 C CNN
F 0 "#PWR049" H 4550 850 20 0001 C CNN
F 1 "+2.5V" H 4550 1000 30 0000 C CNN
1 4550 900
1 0 0 -1
@ -845,10 +877,10 @@ $EndComp
Text HLabel 4950 5350 2 60 BiDi ~ 0
M0_DQ[0..15]
$Comp
L GND #PWR051
L GND #PWR050
U 1 1 4C58A712
P 3000 5200
F 0 "#PWR051" H 3000 5200 30 0001 C CNN
F 0 "#PWR050" H 3000 5200 30 0001 C CNN
F 1 "GND" H 3000 5130 30 0001 C CNN
1 3000 5200
1 0 0 -1
@ -1142,10 +1174,10 @@ Entry Wire Line
Entry Wire Line
9950 3650 10050 3750
$Comp
L GND #PWR052
L GND #PWR051
U 1 1 4C437C3F
P 8250 5200
F 0 "#PWR052" H 8250 5200 30 0001 C CNN
F 0 "#PWR051" H 8250 5200 30 0001 C CNN
F 1 "GND" H 8250 5130 30 0001 C CNN
1 8250 5200
1 0 0 -1

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT
EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT
EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT
EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001

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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 05:33:51 PM COT
EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 06:19:04 PM COT
#
# +1.2V
#

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT
EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001