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Code
8cf60ceb3c
xue/kicad/xue-rnc/xue-rnc.cmp

872 lines
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ddr termination placement
2010-08-17 04:56:08 +03:00
Cmp-Mod V01 Genere par PcbNew le Mon 16 Aug 2010 08:22:44 PM COT
Phy
2010-08-08 20:15:44 +03:00
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7F9F;
Reference = C1;
ValeurCmp = 1uF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D80ED;
Reference = C2;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = 1uF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7FA1;
Reference = C3;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D80F0;
Reference = C4;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7FA3;
Reference = C5;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D8104;
Reference = C6;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA5;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C7;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 1uF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA7;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C8;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D8114;
Reference = C9;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7E41;
Reference = C10;
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7E43;
Reference = C11;
ValeurCmp = 100nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7DCB;
Reference = C12;
ValeurCmp = 47nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2033;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C13;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = 1uF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2037;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C14;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = 1uF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2039;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C15;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = 470nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2D1E;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = C16;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = 4.7nF;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C421DD3/4C61CC73;
Reference = C17;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CC96;
Reference = C18;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CCE3;
Reference = C19;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CCE2;
Reference = C20;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CF2F;
Reference = C21;
ValeurCmp = 1uF;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CEB9;
Reference = C22;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CEF7;
Reference = C23;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CF17;
Reference = C24;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CF16;
Reference = C25;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CF27;
Reference = C26;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA0;
Reference = C27;
ValeurCmp = 1uF;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA5;
Reference = C28;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA4;
Reference = C29;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA2;
Reference = C30;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA3;
Reference = C31;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CFA1;
Reference = C32;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61D151;
Reference = C33;
spi memory added
2010-08-13 23:42:35 +03:00
ValeurCmp = 10uF;
IdModule = 1206;
usb added
2010-08-13 17:27:10 +03:00
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61D1D4;
Reference = C34;
spi memory added
2010-08-13 23:42:35 +03:00
ValeurCmp = 10uF;
IdModule = 1206;
usb added
2010-08-13 17:27:10 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552BE;
Reference = C35;
ValeurCmp = 1uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552BD;
Reference = C36;
ValeurCmp = 1uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552BC;
Reference = C37;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B7;
Reference = C38;
ValeurCmp = 4.7nF;
IdModule = 0402;
EndCmp
FPGA decoupling capacitors
2010-08-13 19:24:39 +03:00
BeginCmp
TimeStamp = /4C431A63/4C656A80;
Reference = C39;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656BF8;
Reference = C40;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CB7;
Reference = C41;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656ABD;
Reference = C42;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656BF9;
Reference = C43;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CB9;
Reference = C44;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656AC0;
Reference = C45;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656C16;
Reference = C46;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CBA;
Reference = C47;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656AC2;
Reference = C48;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656C24;
Reference = C49;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CBB;
Reference = C50;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656C27;
Reference = C51;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656BFA;
Reference = C52;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656C49;
Reference = C53;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D97;
Reference = C54;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D43;
Reference = C55;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CF9;
Reference = C56;
ValeurCmp = 100uF;
IdModule = 1210;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D98;
Reference = C57;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D44;
Reference = C58;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CFA;
Reference = C59;
ValeurCmp = 4.7uF;
IdModule = 0805;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D99;
Reference = C60;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D45;
Reference = C61;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CFB;
Reference = C62;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D9A;
Reference = C63;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D46;
Reference = C64;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656CFC;
Reference = C65;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D9D;
Reference = C66;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D49;
Reference = C67;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D08;
Reference = C68;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C656D53;
Reference = C69;
ValeurCmp = 470nF;
IdModule = 0402;
EndCmp
eth-phy placement
2010-08-14 15:42:37 +03:00
BeginCmp
TimeStamp = /4C421DD3/4C65D2A9;
Reference = C70;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C65D28E;
Reference = C71;
ValeurCmp = 10nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4227FE/4C65D661;
Reference = C72;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4227FE/4C65D67C;
Reference = C73;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4227FE/4C65D681;
Reference = C74;
ValeurCmp = 1uF;
IdModule = 0603;
EndCmp
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
BeginCmp
TimeStamp = /4C4227FE/4C6969AB;
Reference = C75;
ValeurCmp = 100nF;
IdModule = 0402;
EndCmp
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2B55;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = F1;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = MICROSMD075F;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 1210;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
initial import
2010-07-24 14:58:53 +03:00
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C6552BA;
Reference = F2;
ValeurCmp = MICROSMD075F;
IdModule = 1210;
EndCmp
initial import
2010-07-24 14:58:53 +03:00
BeginCmp
TimeStamp = /4C4227FE/4B76F5E2;
Reference = J1;
ValeurCmp = MICROSD;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
IdModule = MICROSD-500901;
initial import
2010-07-24 14:58:53 +03:00
EndCmp
Phy
2010-08-08 20:15:44 +03:00
BeginCmp
TimeStamp = /4C4320F3/4C5D6F5A;
Reference = J4;
ValeurCmp = RJ45-48025;
IdModule = SD-48025;
EndCmp
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C5F23DD;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = J5;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = USB-48204-0001;
annotate
2010-08-10 05:55:50 +03:00
IdModule = USB-48204;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
Phy
2010-08-08 20:15:44 +03:00
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D80F3;
Reference = L1;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = FB;
eth-phy placement
2010-08-14 15:42:37 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7FB7;
Reference = L2;
ValeurCmp = FB;
eth-phy placement
2010-08-14 15:42:37 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D810A;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = L3;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = FB;
eth-phy placement
2010-08-14 15:42:37 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C63F252;
Reference = L4;
ValeurCmp = FB;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C63F248;
Reference = L5;
ValeurCmp = FB;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B0;
Reference = L6;
ValeurCmp = FB;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B1;
Reference = L7;
ValeurCmp = FB;
IdModule = 0603;
EndCmp
Phy
2010-08-08 20:15:44 +03:00
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7F39;
Reference = R1;
ValeurCmp = 4.7K;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7ECF;
Reference = R2;
ValeurCmp = 6.65K;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7AFE;
Reference = R3;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 49.9;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7AFC;
Reference = R4;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 49.9;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7AF7;
Reference = R5;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 49.9;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7AF9;
Reference = R6;
Phy
2010-08-08 20:15:44 +03:00
ValeurCmp = 49.9;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D719D;
Reference = R7;
ValeurCmp = 220;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D71DB;
Reference = R8;
ValeurCmp = 220;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C4320F3/4C5D7DC4;
Reference = R9;
ValeurCmp = 1M;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2D27;
ddr footprint changed
2010-08-10 05:29:52 +03:00
Reference = R10;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = 1M;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0402;
Phy
2010-08-08 20:15:44 +03:00
EndCmp
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C421DD3/4C61CD4A;
Reference = R11;
ValeurCmp = 1K_1%;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CDB5;
Reference = R12;
ValeurCmp = 1K_1%;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CE31;
Reference = R13;
ValeurCmp = 1K_1%;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C61CE30;
Reference = R14;
ValeurCmp = 1K_1%;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B6;
Reference = R15;
ValeurCmp = 1M;
IdModule = 0402;
EndCmp
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69DF7A;
Reference = R16;
ValeurCmp = 120;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C431A63/4C69C6B2;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP1;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69CEE8;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP2;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69D3A4;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP3;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69D3A3;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP4;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69D3A9;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP5;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69DA8A;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP6;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69DC05;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP7;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69E299;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
Reference = RP8;
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
BeginCmp
ddr termination placement
2010-08-17 04:56:08 +03:00
TimeStamp = /4C431A63/4C69E3A6;
Reference = RP9;
Series resistors (DDR) added
2010-08-17 00:32:29 +03:00
ValeurCmp = R_PACK4;
IdModule = R_PACK4-0402;
EndCmp
initial import
2010-07-24 14:58:53 +03:00
BeginCmp
TimeStamp = /4C431A63/4C431E53;
Reference = U1;
ValeurCmp = XC6SLX45FGG484;
IdModule = FGG484bga-p10;
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C421DD3/4C609B99;
initial import
2010-07-24 14:58:53 +03:00
Reference = U2;
ddr footprint changed
2010-08-10 05:29:52 +03:00
ValeurCmp = MT46V32M16TG;
IdModule = TSOP-66;
initial import
2010-07-24 14:58:53 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C421DD3/4C609C8E;
initial import
2010-07-24 14:58:53 +03:00
Reference = U3;
ddr footprint changed
2010-08-10 05:29:52 +03:00
ValeurCmp = MT46V32M16TG;
IdModule = TSOP-66;
initial import
2010-07-24 14:58:53 +03:00
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C432132;
Reference = U4;
ValeurCmp = K8001;
IdModule = LQFP48;
EndCmp
BeginCmp
TimeStamp = /4C4227FE/4B76F108;
Reference = U5;
ValeurCmp = NAND;
IdModule = NAND-48TSOP;
EndCmp
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2025;
Reference = U6;
ValeurCmp = MIC2550AYTS;
IdModule = TSSOP-14;
EndCmp
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C6552BF;
Reference = U7;
ValeurCmp = MIC2550AYTS;
IdModule = TSSOP-14;
EndCmp
spi memory added
2010-08-13 23:42:35 +03:00
BeginCmp
TimeStamp = /4C4227FE/4C65A75D;
Reference = U8;
ValeurCmp = X25X64MB;
IdModule = SO8E;
EndCmp
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C5F1EDC/4C5F2CA7;
Reference = V1;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = V0402MHS03;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
BeginCmp
ddr footprint changed
2010-08-10 05:29:52 +03:00
TimeStamp = /4C5F1EDC/4C5F2CA3;
Reference = V2;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
ValeurCmp = V0402MHS03;
annotate
2010-08-10 05:55:50 +03:00
IdModule = 0603;
Ethernet-phy and USB connected to FPGA
2010-08-09 23:37:18 +03:00
EndCmp
usb added
2010-08-13 17:27:10 +03:00
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B8;
Reference = V3;
ValeurCmp = V0402MHS03;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C6552B9;
Reference = V4;
ValeurCmp = V0402MHS03;
IdModule = 0603;
EndCmp
initial import
2010-07-24 14:58:53 +03:00
EndListe
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