2010-07-28 04:09:20 +03:00
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EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:07:47 PM COT
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2010-07-24 14:58:53 +03:00
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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2010-07-24 22:02:57 +03:00
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LIBS:xue-rnc-cache
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2010-07-24 14:58:53 +03:00
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 1 5
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Title ""
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2010-07-28 04:09:20 +03:00
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Date "28 jul 2010"
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2010-07-24 14:58:53 +03:00
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2750 2100 4000 2100
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Wire Wire Line
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4000 4200 2750 4200
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2010-07-24 14:58:53 +03:00
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Wire Bus Line
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4000 1200 4000 1150
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Wire Bus Line
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4000 1150 2750 1150
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Wire Bus Line
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2750 3250 4000 3250
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Wire Bus Line
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4000 3250 4000 3300
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2010-07-28 04:09:20 +03:00
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Wire Wire Line
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2750 4100 4000 4100
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Wire Wire Line
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4000 2000 2750 2000
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2010-07-24 14:58:53 +03:00
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$Sheet
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2010-07-28 04:09:20 +03:00
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S 8650 3550 1450 2200
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2010-07-24 14:58:53 +03:00
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U 4C4320F3
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F0 "Ethernet Phy" 60
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F1 "eth_phy.sch" 60
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2010-07-28 04:09:20 +03:00
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F2 "ETH_RXC" O L 8650 3700 60
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F3 "ETH_RST_N" I L 8650 3800 60
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F4 "ETH_CRS" O L 8650 3900 60
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F5 "ETH_COL" O L 8650 4000 60
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F6 "ETH_INT" O L 8650 4100 60
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F7 "ETH_MDIO" B L 8650 4200 60
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F8 "ETH_MDC" I L 8650 4300 60
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F9 "ETH_RXD[0..3]" O L 8650 4500 60
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F10 "ETH_RXDV" O L 8650 4600 60
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F11 "ETH_RXER" O L 8650 4700 60
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F12 "ETH_TXC" B L 8650 4800 60
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F13 "ETH_TXD[0..3]" I L 8650 4900 60
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F14 "ETH_TXEN" I L 8650 5000 60
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F15 "ETH_TXER" I L 8650 5100 60
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F16 "ETH_CLK" I L 8650 5200 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$Sheet
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S 4000 900 3500 4000
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U 4C431A63
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F0 "FPGA Spartan6" 60
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F1 "FPGA.sch" 60
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2010-07-28 04:09:20 +03:00
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F2 "M1_CLK" O L 4000 2000 60
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F3 "M1_CLK#" O L 4000 2100 60
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F4 "M0_CLK" O L 4000 4100 60
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F5 "M0_CLK#" O L 4000 4200 60
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2010-07-24 14:58:53 +03:00
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$EndSheet
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$Sheet
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S 8700 900 1150 1850
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U 4C4227FE
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F0 "Non volatile memories" 60
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F1 "NV_MEMORIES.sch" 60
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$EndSheet
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$Sheet
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S 1650 900 1100 4000
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U 4C421DD3
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F0 "DDR Banks" 60
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F1 "DRAM.sch" 60
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F2 "M1_DQ[0..31]" B R 2750 1150 60
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F3 "M0_DQ[0..31]" B R 2750 3250 60
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F4 "M0_BA[0..1]" I R 2750 3700 60
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F5 "M1_BA[0..1]" I R 2750 1600 60
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F6 "M0_DM[0..3]" I R 2750 3850 60
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F7 "M1_DM[0..3]" I R 2750 1750 60
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F8 "M1_A[0..13]" I R 2750 1450 60
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F9 "M0_A[0..13]" I R 2750 3550 60
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F10 "M0_WE#" I R 2750 4600 60
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F11 "M0_RAS#" I R 2750 4450 60
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F12 "M1_RAS#" I R 2750 2350 60
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F13 "M1_WE#" I R 2750 2500 60
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F14 "M0_CAS#" I R 2750 4350 60
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F15 "M0_CKE" I R 2750 4000 60
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F16 "M0_CLK" I R 2750 4100 60
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F17 "M0_CLK#" I R 2750 4200 60
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F18 "M0_CS#" I R 2750 3100 60
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F19 "M1_CS#" I R 2750 1000 60
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F20 "M1_CLK#" I R 2750 2100 60
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F21 "M1_CLK" I R 2750 2000 60
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F22 "M1_CKE" I R 2750 1900 60
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F23 "M1_CAS#" I R 2750 2250 60
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F24 "M1_DQS[0..3]" B R 2750 1300 60
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F25 "M0_DQS[0..3]" B R 2750 3400 60
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$EndSheet
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$EndSCHEMATC
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