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mirror of git://projects.qi-hardware.com/xue.git synced 2024-12-24 20:15:30 +02:00

Somthing routing

This commit is contained in:
Juan64Bits 2010-08-18 20:15:48 -05:00
parent ef7e11688c
commit 048e8b4322
2 changed files with 273 additions and 13 deletions

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@ -1,16 +1,16 @@
PCBNEW-BOARD Version 1 date Tue 17 Aug 2010 07:47:02 PM COT
PCBNEW-BOARD Version 1 date Wed 18 Aug 2010 08:14:41 PM COT
# Created by Pcbnew(2010-07-27 BZR 2423)-unstable
# Created by Pcbnew(2010-04-19 BZR 23xx)-unstable
$GENERAL
LayerCount 6
Ly 1FFF801F
EnabledLayers 1FFF801F
EnabledLayers 13FF801F
Links 640
NoConn 640
Di 45200 13510 70149 50668
NoConn 628
Di 45200 13470 70189 50668
Ndraw 7
Ntrack 0
Ntrack 115
Nzone 0
BoardThickness 630
Nmodule 144
@ -20,7 +20,7 @@ $EndGENERAL
$SHEETDESCR
Sheet A4 11700 8267
Title ""
Date "18 aug 2010"
Date "19 aug 2010"
Rev ""
Comp ""
Comment1 ""
@ -34,13 +34,13 @@ InternalUnit 0.000100 INCH
ZoneGridSize 250
Layers 6
Layer[0] Back signal
Layer[1] Inner2 signal
Layer[1] Inner2 power
Layer[2] Inner3 signal
Layer[3] Inner4 signal
Layer[4] Inner5 signal
Layer[4] Inner5 power
Layer[15] Front signal
TrackWidth 39
TrackClearence 39
TrackClearence 59
ZoneClearence 200
TrackMinWidth 39
DrawSegmWidth 150
@ -1052,7 +1052,7 @@ $EndEQUIPOT
$NCLASS
Name "Default"
Desc "This is the default net class."
Clearance 39
Clearance 59
TrackWidth 39
ViaDia 197
ViaDrill 79
@ -1305,6 +1305,36 @@ AddNet "N-000432"
AddNet "N-000433"
AddNet "VCCO2"
$EndNCLASS
$NCLASS
Name "ADDRESS/DDR"
Desc ""
Clearance 59
TrackWidth 39
ViaDia 197
ViaDrill 79
uViaDia 197
uViaDrill 79
$EndNCLASS
$NCLASS
Name "CLK#CLK/DDR"
Desc ""
Clearance 39
TrackWidth 39
ViaDia 197
ViaDrill 79
uViaDia 197
uViaDrill 79
$EndNCLASS
$NCLASS
Name "DATA/DDR"
Desc ""
Clearance 79
TrackWidth 39
ViaDia 197
ViaDrill 79
uViaDia 197
uViaDrill 79
$EndNCLASS
$MODULE 1206
Po 63750 39693 1800 15 4C5FF890 4C61D1D4 ~~
Li 1206
@ -11630,7 +11660,7 @@ Po -295 177
$EndPAD
$EndMODULE R_PACK4-0402
$MODULE 0402
Po 51300 33300 900 0 4C5FF890 4C6B1F81 ~~
Po 51370 33417 900 0 4C5FF890 4C6B1F81 ~~
Li 0402
Sc 4C6B1F81
AR /4C431A63/4C6B1B90
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De 28 0 900 0 0
$EndDRAWSEGMENT
$TRACK
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$EndTRACK
$ZONE
$EndZONE

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@ -1,4 +1,4 @@
update=Tue 17 Aug 2010 07:49:00 PM COT
update=Wed 18 Aug 2010 07:03:19 PM COT
version=1
last_client=pcbnew
[common]