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This commit is contained in:
Andres Calderon 2010-08-09 21:55:50 -05:00
parent 11ade0f1e8
commit 171e409036
13 changed files with 1422 additions and 532 deletions
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3
kicad/modules/MICROSD-500901.mdc Normal file
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@ -0,0 +1,3 @@
PCBNEW-LibDoc----V1 27/9/2008-16:35:21
#
$EndLIBDOC

3
kicad/modules/TSSOP-14.mdc Normal file
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@ -0,0 +1,3 @@
PCBNEW-LibDoc----V1 27/9/2008-16:35:21
#
$EndLIBDOC

10
kicad/xue-rnc/DRAM.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001
@ -389,10 +389,10 @@ $EndComp
Text HLabel 4950 5700 2 60 BiDi ~ 0
M0_DQ[0..15]
$Comp
L GND #PWR1
L GND #PWR04
U 1 1 4C58A712
P 3000 5200
F 0 "#PWR1" H 3000 5200 30 0001 C CNN
F 0 "#PWR04" H 3000 5200 30 0001 C CNN
F 1 "GND" H 3000 5130 30 0001 C CNN
1 3000 5200
1 0 0 -1
@ -686,10 +686,10 @@ Entry Wire Line
Entry Wire Line
9950 3650 10050 3750
$Comp
L GND #PWR2
L GND #PWR05
U 1 1 4C437C3F
P 8250 5200
F 0 "#PWR2" H 8250 5200 30 0001 C CNN
F 0 "#PWR05" H 8250 5200 30 0001 C CNN
F 1 "GND" H 8250 5130 30 0001 C CNN
1 8250 5200
1 0 0 -1

6
kicad/xue-rnc/FPGA.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001
@ -1280,10 +1280,10 @@ M0_CLK
Text HLabel 7750 4700 2 60 Output ~ 0
M0_CLK#
$Comp
L GND #PWR5
L GND #PWR01
U 1 1 4C439B7E
P 13450 15700
F 0 "#PWR5" H 13450 15700 30 0001 C CNN
F 0 "#PWR01" H 13450 15700 30 0001 C CNN
F 1 "GND" H 13450 15630 30 0001 C CNN
1 13450 15700
1 0 0 -1

10
kicad/xue-rnc/NV_MEMORIES.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001
@ -172,19 +172,19 @@ Wire Wire Line
4400 5750 4400 5950
Connection ~ 4400 5850
$Comp
L GND #PWR4
L GND #PWR02
U 1 1 4C438ADC
P 4400 5950
F 0 "#PWR4" H 4400 5950 30 0001 C CNN
F 0 "#PWR02" H 4400 5950 30 0001 C CNN
F 1 "GND" H 4400 5880 30 0001 C CNN
1 4400 5950
1 0 0 -1
$EndComp
$Comp
L GND #PWR3
L GND #PWR03
U 1 1 4C438AD5
P 3950 6300
F 0 "#PWR3" H 3950 6300 30 0001 C CNN
F 0 "#PWR03" H 3950 6300 30 0001 C CNN
F 1 "GND" H 3950 6230 30 0001 C CNN
1 3950 6300
1 0 0 -1

2
kicad/xue-rnc/USB.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001

2
kicad/xue-rnc/eth_phy.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001

2
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 09:20:06 PM COT
EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 09:53:48 PM COT
#
# C
#

1459
kicad/xue-rnc/xue-rnc.brd
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File diff suppressed because it is too large Load Diff

68
kicad/xue-rnc/xue-rnc.cmp
View File

@ -1,122 +1,122 @@
Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:21:21 PM COT
Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:53:42 PM COT
BeginCmp
TimeStamp = /4C4320F3/4C5D7F9F;
Reference = C1;
ValeurCmp = 1uF;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D80ED;
Reference = C2;
ValeurCmp = C;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA1;
Reference = C3;
ValeurCmp = 100nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D80F0;
Reference = C4;
ValeurCmp = C;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA3;
Reference = C5;
ValeurCmp = 100nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D8104;
Reference = C6;
ValeurCmp = C;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA5;
Reference = C7;
ValeurCmp = 1uF;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FA7;
Reference = C8;
ValeurCmp = 100nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D8114;
Reference = C9;
ValeurCmp = C;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7E41;
Reference = C10;
ValeurCmp = 100nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7E43;
Reference = C11;
ValeurCmp = 100nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7DCB;
Reference = C12;
ValeurCmp = 47nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2033;
Reference = C13;
ValeurCmp = 1uF;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2037;
Reference = C14;
ValeurCmp = 1uF;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2039;
Reference = C15;
ValeurCmp = 470nF;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2D1E;
Reference = C16;
ValeurCmp = 4.7nF;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2B55;
Reference = F1;
ValeurCmp = MICROSMD075F;
IdModule = ;
IdModule = 1210;
EndCmp
BeginCmp
@ -137,98 +137,98 @@ BeginCmp
TimeStamp = /4C5F1EDC/4C5F23DD;
Reference = J5;
ValeurCmp = USB-48204-0001;
IdModule = ;
IdModule = USB-48204;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D80F3;
Reference = L1;
ValeurCmp = INDUCTOR;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7FB7;
Reference = L2;
ValeurCmp = FB;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D810A;
Reference = L3;
ValeurCmp = INDUCTOR;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7F39;
Reference = R1;
ValeurCmp = 4.7K;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7ECF;
Reference = R2;
ValeurCmp = 6.65K;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7AFE;
Reference = R3;
ValeurCmp = 49.9;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7AFC;
Reference = R4;
ValeurCmp = 49.9;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7AF7;
Reference = R5;
ValeurCmp = 49.9;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7AF9;
Reference = R6;
ValeurCmp = 49.9;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D719D;
Reference = R7;
ValeurCmp = 220;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D71DB;
Reference = R8;
ValeurCmp = 220;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C4320F3/4C5D7DC4;
Reference = R9;
ValeurCmp = 1M;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2D27;
Reference = R10;
ValeurCmp = 1M;
IdModule = ;
IdModule = 0402;
EndCmp
BeginCmp
@ -277,14 +277,14 @@ BeginCmp
TimeStamp = /4C5F1EDC/4C5F2CA7;
Reference = V1;
ValeurCmp = V0402MHS03;
IdModule = ;
IdModule = 0603;
EndCmp
BeginCmp
TimeStamp = /4C5F1EDC/4C5F2CA3;
Reference = V2;
ValeurCmp = V0402MHS03;
IdModule = ;
IdModule = 0603;
EndCmp
EndListe

360
kicad/xue-rnc/xue-rnc.net
View File

@ -1,70 +1,70 @@
# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 09:21:21 PM COT
# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 09:53:42 PM COT
(
( /4C4320F3/4C5D7F9F $noname$ C1 1uF
( /4C4320F3/4C5D7F9F 0603 C1 1uF
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D80ED $noname$ C2 C
( /4C4320F3/4C5D80ED 0402 C2 C
( 1 /Etherne1 )
( 2 GND )
)
( /4C4320F3/4C5D7FA1 $noname$ C3 100nF
( /4C4320F3/4C5D7FA1 0402 C3 100nF
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D80F0 $noname$ C4 C
( /4C4320F3/4C5D80F0 0402 C4 C
( 1 N-000417 )
( 2 N-000416 )
)
( /4C4320F3/4C5D7FA3 $noname$ C5 100nF
( /4C4320F3/4C5D7FA3 0402 C5 100nF
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D8104 $noname$ C6 C
( /4C4320F3/4C5D8104 0402 C6 C
( 1 /Etherne2 )
( 2 N-000416 )
)
( /4C4320F3/4C5D7FA5 $noname$ C7 1uF
( /4C4320F3/4C5D7FA5 0603 C7 1uF
( 1 /Etherne3 )
( 2 GND )
)
( /4C4320F3/4C5D7FA7 $noname$ C8 100nF
( /4C4320F3/4C5D7FA7 0402 C8 100nF
( 1 /Etherne3 )
( 2 GND )
)
( /4C4320F3/4C5D8114 $noname$ C9 C
( /4C4320F3/4C5D8114 0402 C9 C
( 1 /Etherne4 )
( 2 N-000416 )
)
( /4C4320F3/4C5D7E41 $noname$ C10 100nF
( /4C4320F3/4C5D7E41 0402 C10 100nF
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7E43 $noname$ C11 100nF
( /4C4320F3/4C5D7E43 0402 C11 100nF
( 1 3.3V )
( 2 GND )
)
( /4C4320F3/4C5D7DCB $noname$ C12 47nF
( /4C4320F3/4C5D7DCB 0402 C12 47nF
( 1 N-000400 )
( 2 GND )
)
( /4C5F1EDC/4C5F2033 $noname$ C13 1uF
( /4C5F1EDC/4C5F2033 0603 C13 1uF
( 1 3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2037 $noname$ C14 1uF
( /4C5F1EDC/4C5F2037 0603 C14 1uF
( 1 3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2039 $noname$ C15 470nF
( /4C5F1EDC/4C5F2039 0603 C15 470nF
( 1 3.3V )
( 2 GND )
)
( /4C5F1EDC/4C5F2D1E $noname$ C16 4.7nF
( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF
( 1 N-000428 )
( 2 GND )
)
( /4C5F1EDC/4C5F2B55 $noname$ F1 MICROSMD075F
( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F
( 1 N-000427 )
( 2 ? )
)
@ -97,7 +97,7 @@
( 13 N-000400 )
( 14 N-000400 )
)
( /4C5F1EDC/4C5F23DD $noname$ J5 USB-48204-0001
( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001
( 1 N-000427 )
( 2 N-000420 )
( 3 N-000426 )
@ -107,55 +107,55 @@
( S3 N-000428 )
( S4 N-000428 )
)
( /4C4320F3/4C5D80F3 $noname$ L1 INDUCTOR
( /4C4320F3/4C5D80F3 0603 L1 INDUCTOR
( 1 N-000417 )
( 2 /Etherne2 )
)
( /4C4320F3/4C5D7FB7 $noname$ L2 FB
( /4C4320F3/4C5D7FB7 0603 L2 FB
( 1 3.3V )
( 2 /Etherne3 )
)
( /4C4320F3/4C5D810A $noname$ L3 INDUCTOR
( /4C4320F3/4C5D810A 0603 L3 INDUCTOR
( 1 /Etherne2 )
( 2 /Etherne4 )
)
( /4C4320F3/4C5D7F39 $noname$ R1 4.7K
( /4C4320F3/4C5D7F39 0402 R1 4.7K
( 1 /ETH_MDIO )
( 2 3.3V )
)
( /4C4320F3/4C5D7ECF $noname$ R2 6.65K
( /4C4320F3/4C5D7ECF 0402 R2 6.65K
( 1 N-000402 )
( 2 GND )
)
( /4C4320F3/4C5D7AFE $noname$ R3 49.9
( /4C4320F3/4C5D7AFE 0402 R3 49.9
( 1 3.3V )
( 2 N-000398 )
)
( /4C4320F3/4C5D7AFC $noname$ R4 49.9
( /4C4320F3/4C5D7AFC 0402 R4 49.9
( 1 3.3V )
( 2 N-000406 )
)
( /4C4320F3/4C5D7AF7 $noname$ R5 49.9
( /4C4320F3/4C5D7AF7 0402 R5 49.9
( 1 3.3V )
( 2 N-000399 )
)
( /4C4320F3/4C5D7AF9 $noname$ R6 49.9
( /4C4320F3/4C5D7AF9 0402 R6 49.9
( 1 3.3V )
( 2 N-000405 )
)
( /4C4320F3/4C5D719D $noname$ R7 220
( /4C4320F3/4C5D719D 0402 R7 220
( 1 N-000396 )
( 2 /Etherne5 )
)
( /4C4320F3/4C5D71DB $noname$ R8 220
( /4C4320F3/4C5D71DB 0402 R8 220
( 1 N-000404 )
( 2 /Etherne6 )
)
( /4C4320F3/4C5D7DC4 $noname$ R9 1M
( /4C4320F3/4C5D7DC4 0402 R9 1M
( 1 N-000400 )
( 2 GND )
)
( /4C5F1EDC/4C5F2D27 $noname$ R10 1M
( /4C5F1EDC/4C5F2D27 0402 R10 1M
( 1 N-000428 )
( 2 GND )
)
@ -247,7 +247,7 @@
( B20 ? )
( B21 ? )
( B22 ? )
( C1 /DDR_Ban8 )
( C1 /FPGA_Sp8 )
( C2 N-000158 )
( C3 ? )
( C4 ? )
@ -267,9 +267,9 @@
( C18 ? )
( C20 /FPGA_Sp9 )
( C21 N-000154 )
( C22 /FPGA_Sp10 )
( D1 /DDR_Ban11 )
( D2 /DDR_Ban12 )
( C22 /DDR_Banks/M1_A9 )
( D1 /FPGA_Sp10 )
( D2 /DDR_Ban11 )
( D3 ? )
( D4 GND )
( D5 ? )
@ -288,9 +288,9 @@
( D18 GND )
( D19 ? )
( D20 ? )
( D21 /FPGA_Sp13 )
( D22 /FPGA_Sp14 )
( E1 /DDR_Banks/M0_A9 )
( D21 /FPGA_Sp12 )
( D22 /FPGA_Sp13 )
( E1 /FPGA_Sp14 )
( E2 GND )
( E3 /DDR_Banks/M0_A8 )
( E4 ? )
@ -309,12 +309,12 @@
( E17 N-000153 )
( E18 ? )
( E19 N-000154 )
( E20 /FPGA_Sp15 )
( E20 /DDR_Banks/M1_A7 )
( E21 GND )
( E22 /FPGA_Sp16 )
( E22 /DDR_Banks/M1_A2 )
( F1 ? )
( F2 /FPGA_Sp17 )
( F3 /FPGA_Sp18 )
( F2 /DDR_Ban15 )
( F3 /DDR_Banks/M0_A4 )
( F4 N-000158 )
( F5 ? )
( F6 N-000158 )
@ -330,14 +330,14 @@
( F16 ? )
( F17 ? )
( F18 ? )
( F19 /FPGA_Sp19 )
( F20 /FPGA_Sp20 )
( F21 /FPGA_Sp21 )
( F22 /FPGA_Sp22 )
( F19 /DDR_Ban16 )
( F20 /FPGA_Sp17 )
( F21 /DDR_Banks/M1_A0 )
( F22 /DDR_Banks/M1_A1 )
( G1 ? )
( G2 N-000158 )
( G3 ? )
( G4 /FPGA_Sp23 )
( G4 /FPGA_Sp18 )
( G5 GND )
( G6 ? )
( G7 ? )
@ -352,16 +352,16 @@
( G16 ? )
( G17 ? )
( G18 GND )
( G19 /FPGA_Sp24 )
( G20 /DDR_Banks/M1_A3 )
( G19 /FPGA_Sp19 )
( G20 /FPGA_Sp20 )
( G21 N-000154 )
( G22 ? )
( H1 /FPGA_Sp25 )
( H2 /FPGA_Sp26 )
( H3 /DDR_Ban27 )
( H4 /DDR_Ban28 )
( H5 /FPGA_Sp29 )
( H6 /FPGA_Sp30 )
( H1 /FPGA_Sp21 )
( H2 /DDR_Banks/M0_A0 )
( H3 /DDR_Ban22 )
( H4 /DDR_Ban23 )
( H5 /FPGA_Sp24 )
( H6 /DDR_Banks/M0_A7 )
( H7 GND )
( H8 ? )
( H9 N-000160 )
@ -374,14 +374,14 @@
( H16 ? )
( H17 ? )
( H18 ? )
( H19 /DDR_Ban31 )
( H20 /FPGA_Sp32 )
( H21 /FPGA_Sp33 )
( H22 /DDR_Ban34 )
( J1 /FPGA_Sp35 )
( H19 /DDR_Ban25 )
( H20 /DDR_Ban26 )
( H21 /FPGA_Sp27 )
( H22 /FPGA_Sp28 )
( J1 /FPGA_Sp29 )
( J2 GND )
( J3 /DDR_Ban36 )
( J4 /FPGA_Sp37 )
( J3 /DDR_Ban30 )
( J4 /FPGA_Sp31 )
( J5 N-000158 )
( J6 ? )
( J7 ? )
@ -396,16 +396,16 @@
( J16 ? )
( J17 ? )
( J18 N-000154 )
( J19 /DDR_Ban38 )
( J19 /FPGA_Sp32 )
( J20 ? )
( J21 GND )
( J22 /FPGA_Sp39 )
( K1 /FPGA_Sp40 )
( K2 /FPGA_Sp41 )
( K3 /FPGA_Sp42 )
( K4 /DDR_Ban43 )
( K5 /DDR_Ban44 )
( K6 /FPGA_Sp45 )
( J22 /FPGA_Sp33 )
( K1 /DDR_Ban34 )
( K2 /DDR_Ban35 )
( K3 /FPGA_Sp36 )
( K4 /FPGA_Sp37 )
( K5 /FPGA_Sp38 )
( K6 /FPGA_Sp39 )
( K7 ? )
( K8 ? )
( K9 N-000159 )
@ -418,14 +418,14 @@
( K16 ? )
( K17 ? )
( K18 ? )
( K19 /FPGA_Sp46 )
( K19 /DDR_Banks/M1_A6 )
( K20 /DDR_Banks/M1_A5 )
( K21 /DDR_Ban47 )
( K22 /DDR_Ban48 )
( K21 /FPGA_Sp40 )
( K22 /FPGA_Sp41 )
( L1 ? )
( L2 N-000158 )
( L3 /FPGA_Sp49 )
( L4 /FPGA_Sp50 )
( L3 /DDR_Ban42 )
( L4 /FPGA_Sp43 )
( L5 GND )
( L6 ? )
( L7 N-000158 )
@ -440,13 +440,13 @@
( L16 N-000154 )
( L17 ? )
( L18 GND )
( L19 /FPGA_Sp51 )
( L20 /FPGA_Sp52 )
( L19 /DDR_Ban44 )
( L20 /DDR_Ban45 )
( L21 N-000154 )
( L22 ? )
( M1 /FPGA_Sp53 )
( M2 /FPGA_Sp54 )
( M3 /FPGA_Sp55 )
( M1 /DDR_Ban46 )
( M2 /FPGA_Sp47 )
( M3 /FPGA_Sp48 )
( M4 ? )
( M5 ? )
( M6 ? )
@ -463,12 +463,12 @@
( M17 ? )
( M18 ? )
( M19 ? )
( M20 /FPGA_Sp56 )
( M20 /DDR_Ban49 )
( M21 ? )
( M22 ? )
( N1 /DDR_Ban57 )
( N1 /FPGA_Sp50 )
( N2 GND )
( N3 /FPGA_Sp58 )
( N3 /DDR_Ban51 )
( N4 ? )
( N5 N-000158 )
( N6 ? )
@ -485,11 +485,11 @@
( N17 GND )
( N18 N-000154 )
( N19 ? )
( N20 /FPGA_Sp59 )
( N20 /FPGA_Sp52 )
( N21 GND )
( N22 /FPGA_Sp60 )
( P1 /FPGA_Sp61 )
( P2 /DDR_Ban62 )
( N22 /FPGA_Sp53 )
( P1 /FPGA_Sp54 )
( P2 /FPGA_Sp55 )
( P3 ? )
( P4 ? )
( P5 ? )
@ -508,11 +508,11 @@
( P18 ? )
( P19 ? )
( P20 ? )
( P21 /DDR_Ban63 )
( P22 /FPGA_Sp64 )
( R1 /DDR_Ban65 )
( P21 /FPGA_Sp56 )
( P22 /FPGA_Sp57 )
( R1 /FPGA_Sp58 )
( R2 N-000158 )
( R3 /FPGA_Sp66 )
( R3 /FPGA_Sp59 )
( R4 ? )
( R5 GND )
( R6 N-000160 )
@ -529,11 +529,11 @@
( R17 ? )
( R18 GND )
( R19 ? )
( R20 /DDR_Ban67 )
( R20 /FPGA_Sp60 )
( R21 N-000154 )
( R22 /DDR_Ban68 )
( R22 /FPGA_Sp61 )
( T1 ? )
( T2 /FPGA_Sp69 )
( T2 /FPGA_Sp62 )
( T3 ? )
( T4 ? )
( T5 ? )
@ -552,11 +552,11 @@
( T18 ? )
( T19 ? )
( T20 ? )
( T21 /DDR_Ban70 )
( T21 /FPGA_Sp63 )
( T22 ? )
( U1 /FPGA_Sp71 )
( U1 /DDR_Ban64 )
( U2 GND )
( U3 /DDR_Ban72 )
( U3 /FPGA_Sp65 )
( U4 ? )
( U5 N-000158 )
( U6 ? )
@ -573,11 +573,11 @@
( U17 ? )
( U18 N-000154 )
( U19 ? )
( U20 /FPGA_Sp73 )
( U20 /FPGA_Sp66 )
( U21 GND )
( U22 /FPGA_Sp74 )
( V1 /DDR_Ban75 )
( V2 /DDR_Ban76 )
( U22 /FPGA_Sp67 )
( V1 /DDR_Ban68 )
( V2 /FPGA_Sp69 )
( V3 ? )
( V4 GND )
( V5 ? )
@ -596,8 +596,8 @@
( V18 ? )
( V19 ? )
( V20 ? )
( V21 /FPGA_Sp77 )
( V22 /DDR_Ban78 )
( V21 /FPGA_Sp70 )
( V22 /DDR_Ban71 )
( W1 ? )
( W2 N-000158 )
( W3 ? )
@ -642,138 +642,138 @@
)
( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG
( 1 N-000056 )
( 2 /FPGA_Sp58 )
( 2 /DDR_Ban51 )
( 3 N-000056 )
( 4 /DDR_Ban57 )
( 5 /FPGA_Sp54 )
( 4 /FPGA_Sp50 )
( 5 /FPGA_Sp47 )
( 6 GND )
( 7 /FPGA_Sp53 )
( 8 /DDR_Ban36 )
( 7 /DDR_Ban46 )
( 8 /DDR_Ban30 )
( 9 N-000056 )
( 10 /FPGA_Sp35 )
( 11 /FPGA_Sp41 )
( 10 /FPGA_Sp29 )
( 11 /DDR_Ban35 )
( 12 GND )
( 13 /FPGA_Sp40 )
( 13 /DDR_Ban34 )
( 14 ? )
( 15 N-000056 )
( 16 /FPGA_Sp49 )
( 16 /DDR_Ban42 )
( 17 ? )
( 18 N-000056 )
( 19 ? )
( 20 /FPGA_Sp50 )
( 21 /FPGA_Sp17 )
( 22 /DDR_Ban43 )
( 23 /DDR_Ban44 )
( 20 /FPGA_Sp43 )
( 21 /DDR_Ban15 )
( 22 /FPGA_Sp37 )
( 23 /FPGA_Sp38 )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 /FPGA_Sp23 )
( 29 /FPGA_Sp26 )
( 30 /FPGA_Sp25 )
( 31 /FPGA_Sp29 )
( 32 /FPGA_Sp45 )
( 28 /FPGA_Sp18 )
( 29 /DDR_Banks/M0_A0 )
( 30 /FPGA_Sp21 )
( 31 /FPGA_Sp24 )
( 32 /FPGA_Sp39 )
( 33 N-000056 )
( 34 GND )
( 35 /FPGA_Sp18 )
( 36 /FPGA_Sp42 )
( 37 /FPGA_Sp37 )
( 38 /FPGA_Sp30 )
( 35 /DDR_Banks/M0_A4 )
( 36 /FPGA_Sp36 )
( 37 /FPGA_Sp31 )
( 38 /DDR_Banks/M0_A7 )
( 39 /DDR_Banks/M0_A8 )
( 40 /DDR_Banks/M0_A9 )
( 41 /DDR_Ban8 )
( 42 /DDR_Ban11 )
( 40 /FPGA_Sp14 )
( 41 /FPGA_Sp8 )
( 42 /FPGA_Sp10 )
( 43 ? )
( 44 /DDR_Ban27 )
( 45 /DDR_Ban12 )
( 46 /DDR_Ban28 )
( 47 /FPGA_Sp55 )
( 44 /DDR_Ban22 )
( 45 /DDR_Ban11 )
( 46 /DDR_Ban23 )
( 47 /FPGA_Sp48 )
( 48 GND )
( 49 ? )
( 50 ? )
( 51 /FPGA_Sp69 )
( 51 /FPGA_Sp62 )
( 52 GND )
( 53 ? )
( 54 /DDR_Ban62 )
( 54 /FPGA_Sp55 )
( 55 N-000056 )
( 56 /FPGA_Sp61 )
( 57 /FPGA_Sp66 )
( 56 /FPGA_Sp54 )
( 57 /FPGA_Sp59 )
( 58 GND )
( 59 /DDR_Ban65 )
( 60 /DDR_Ban72 )
( 59 /FPGA_Sp58 )
( 60 /FPGA_Sp65 )
( 61 N-000056 )
( 62 /FPGA_Sp71 )
( 63 /DDR_Ban76 )
( 62 /DDR_Ban64 )
( 63 /FPGA_Sp69 )
( 64 GND )
( 65 /DDR_Ban75 )
( 65 /DDR_Ban68 )
( 66 GND )
)
( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG
( 1 N-000048 )
( 2 /FPGA_Sp59 )
( 2 /FPGA_Sp52 )
( 3 N-000048 )
( 4 /FPGA_Sp60 )
( 4 /FPGA_Sp53 )
( 5 ? )
( 6 GND )
( 7 ? )
( 8 ? )
( 9 N-000048 )
( 10 /FPGA_Sp39 )
( 11 /DDR_Ban47 )
( 10 /FPGA_Sp33 )
( 11 /FPGA_Sp40 )
( 12 GND )
( 13 /DDR_Ban48 )
( 13 /FPGA_Sp41 )
( 14 ? )
( 15 N-000048 )
( 16 /FPGA_Sp52 )
( 16 /DDR_Ban45 )
( 17 ? )
( 18 N-000048 )
( 19 ? )
( 20 /FPGA_Sp51 )
( 21 /DDR_Ban31 )
( 22 /DDR_Ban34 )
( 23 /FPGA_Sp33 )
( 20 /DDR_Ban44 )
( 21 /DDR_Ban25 )
( 22 /FPGA_Sp28 )
( 23 /FPGA_Sp27 )
( 24 ? )
( 25 ? )
( 26 ? )
( 27 ? )
( 28 /FPGA_Sp24 )
( 29 /FPGA_Sp21 )
( 30 /FPGA_Sp22 )
( 31 /FPGA_Sp16 )
( 32 /DDR_Banks/M1_A3 )
( 28 /FPGA_Sp19 )
( 29 /DDR_Banks/M1_A0 )
( 30 /DDR_Banks/M1_A1 )
( 31 /DDR_Banks/M1_A2 )
( 32 /FPGA_Sp20 )
( 33 N-000048 )
( 34 GND )
( 35 /FPGA_Sp20 )
( 35 /FPGA_Sp17 )
( 36 /DDR_Banks/M1_A5 )
( 37 /FPGA_Sp46 )
( 38 /FPGA_Sp15 )
( 37 /DDR_Banks/M1_A6 )
( 38 /DDR_Banks/M1_A7 )
( 39 /FPGA_Sp9 )
( 40 /FPGA_Sp10 )
( 41 /FPGA_Sp19 )
( 42 /FPGA_Sp14 )
( 40 /DDR_Banks/M1_A9 )
( 41 /DDR_Ban16 )
( 42 /FPGA_Sp13 )
( 43 ? )
( 44 /DDR_Ban38 )
( 45 /FPGA_Sp13 )
( 46 /FPGA_Sp32 )
( 47 /FPGA_Sp56 )
( 44 /FPGA_Sp32 )
( 45 /FPGA_Sp12 )
( 46 /DDR_Ban26 )
( 47 /DDR_Ban49 )
( 48 GND )
( 49 ? )
( 50 ? )
( 51 /DDR_Ban70 )
( 51 /FPGA_Sp63 )
( 52 GND )
( 53 ? )
( 54 /DDR_Ban63 )
( 54 /FPGA_Sp56 )
( 55 N-000048 )
( 56 /FPGA_Sp64 )
( 57 /DDR_Ban67 )
( 56 /FPGA_Sp57 )
( 57 /FPGA_Sp60 )
( 58 GND )
( 59 /DDR_Ban68 )
( 60 /FPGA_Sp73 )
( 59 /FPGA_Sp61 )
( 60 /FPGA_Sp66 )
( 61 N-000048 )
( 62 /FPGA_Sp74 )
( 63 /FPGA_Sp77 )
( 62 /FPGA_Sp67 )
( 63 /FPGA_Sp70 )
( 64 GND )
( 65 /DDR_Ban78 )
( 65 /DDR_Ban71 )
( 66 GND )
)
( /4C4320F3/4C432132 LQFP48 U4 K8001
@ -832,8 +832,8 @@
( 3 ? )
( 4 ? )
( 5 ? )
( 6 /Non_vol79 )
( 7 /Non_vol79 )
( 6 /Non_vol72 )
( 7 /Non_vol72 )
( 8 ? )
( 9 ? )
( 10 ? )
@ -890,11 +890,11 @@
( 12 3.3V )
( 14 3.3V )
)
( /4C5F1EDC/4C5F2CA7 $noname$ V1 V0402MHS03
( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03
( 1 N-000426 )
( 2 GND )
)
( /4C5F1EDC/4C5F2CA3 $noname$ V2 V0402MHS03
( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03
( 1 N-000420 )
( 2 GND )
)

5
kicad/xue-rnc/xue-rnc.pro
View File

@ -1,4 +1,4 @@
update=Mon 09 Aug 2010 09:19:33 PM COT
update=Mon 09 Aug 2010 09:51:02 PM COT
version=1
last_client=pcbnew
[common]
@ -130,4 +130,5 @@ LibName20=../modules/LQFP48
LibName21=../modules/48TSOP-NAND
LibName22=../modules/micro-sd
LibName23=../modules/60fbga_ddr
LibName24=/home/afc/devel/Qi/xue/kicad/modules/66-tsop
LibName24=../modules/66-tsop
LibName25=../modules/stdpass

24
kicad/xue-rnc/xue-rnc.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT
EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT
LIBS:power
LIBS:v0402mhs03
LIBS:usb-48204-0001
@ -248,17 +248,17 @@ F2 "ETH_RXC" O L 10600 6500 60
F3 "ETH_RST_N" I L 10600 6600 60
F4 "ETH_CRS" O L 10600 6700 60
F5 "ETH_COL" O L 10600 6800 60
F6 "ETH_INT" O L 10600 6350 60
F7 "ETH_MDIO" B L 10600 6900 60
F8 "ETH_MDC" I L 10600 7000 60
F9 "ETH_RXD[0..3]" O L 10600 7200 60
F10 "ETH_RXDV" O L 10600 7300 60
F11 "ETH_RXER" O L 10600 7400 60
F12 "ETH_TXC" B L 10600 7500 60
F13 "ETH_TXD[0..3]" I L 10600 7600 60
F14 "ETH_TXEN" I L 10600 7700 60
F15 "ETH_TXER" I L 10600 7800 60
F16 "ETH_CLK" I L 10600 7900 60
F6 "ETH_MDIO" B L 10600 6900 60
F7 "ETH_MDC" I L 10600 7000 60
F8 "ETH_RXD[0..3]" O L 10600 7200 60
F9 "ETH_RXDV" O L 10600 7300 60
F10 "ETH_RXER" O L 10600 7400 60
F11 "ETH_TXC" B L 10600 7500 60
F12 "ETH_TXD[0..3]" I L 10600 7600 60
F13 "ETH_TXEN" I L 10600 7700 60
F14 "ETH_TXER" I L 10600 7800 60
F15 "ETH_CLK" I L 10600 7900 60
F16 "ETH_INT" O L 10600 6350 60
$EndSheet
$Sheet
S 10650 2700 1150 1850