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Code

Kicad labels problem.

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This commit is contained in:
Juan64Bits 2010-09-09 17:56:28 -05:00
parent 1e22c59bbc
commit 1cd37e7a67
14 changed files with 13548 additions and 10402 deletions
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4
kicad/xue-rnc/DBG_PRG.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

6
kicad/xue-rnc/DRAM.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -49,9 +49,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Sheet 9 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

4
kicad/xue-rnc/FPGA_0_2_PROG.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 2 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

4
kicad/xue-rnc/FPGA_1_3.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 3 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

6
kicad/xue-rnc/NV_MEMORIES.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -49,9 +49,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Sheet 6 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

90
kicad/xue-rnc/PSU.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 5 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""
@ -59,43 +59,28 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L +BATT #PWR022
U 1 1 4C859B7F
P 1000 5200
F 0 "#PWR022" H 1000 5150 20 0001 C CNN
F 1 "+BATT" H 1000 5300 30 0000 C CNN
1 1000 5200
1 0 0 -1
$EndComp
Wire Wire Line
8250 5200 7050 5200
Wire Wire Line
7050 5200 7050 4650
Wire Wire Line
600 2100 600 1100
Wire Wire Line
600 2100 3450 2100
Wire Wire Line
3450 2100 3450 4650
Wire Wire Line
3450 4650 7050 4650
Wire Wire Line
1000 5200 1000 5250
Wire Wire Line
1000 700 1000 750
$Comp
L +BATT #PWR023
U 1 1 4C859B76
P 1000 700
F 0 "#PWR023" H 1000 650 20 0001 C CNN
F 1 "+BATT" H 1000 800 30 0000 C CNN
1 1000 700
1 0 0 -1
$EndComp
$Comp
L +BATT #PWR024
U 1 1 4C859B70
P 6200 700
F 0 "#PWR024" H 6200 650 20 0001 C CNN
F 1 "+BATT" H 6200 800 30 0000 C CNN
1 6200 700
1 0 0 -1
$EndComp
Wire Wire Line
6200 700 6200 750
Wire Wire Line
6100 2650 6100 2700
Wire Wire Line
1100 1100 600 1100
600 1100 1100 1100
Wire Wire Line
8250 6200 7650 6200
Wire Wire Line
@ -485,8 +470,6 @@ Wire Wire Line
7150 6300 7150 6200
Wire Wire Line
7350 4700 7350 4600
Wire Wire Line
7200 5500 8250 5500
Wire Wire Line
2600 1150 2600 1600
Wire Wire Line
@ -513,17 +496,34 @@ Wire Wire Line
7300 2950 7500 2950
Connection ~ 7500 2950
Wire Wire Line
600 1100 600 2400
Wire Wire Line
600 2400 5000 2400
Wire Wire Line
5000 2400 5000 4650
Wire Wire Line
5000 4650 7050 4650
Wire Wire Line
7050 4650 7050 5200
Wire Wire Line
7050 5200 8250 5200
7750 5500 8250 5500
$Comp
L +BATT #PWR022
U 1 1 4C859B7F
P 1000 5200
F 0 "#PWR022" H 1000 5150 20 0001 C CNN
F 1 "+BATT" H 1000 5300 30 0000 C CNN
1 1000 5200
1 0 0 -1
$EndComp
$Comp
L +BATT #PWR023
U 1 1 4C859B76
P 1000 700
F 0 "#PWR023" H 1000 650 20 0001 C CNN
F 1 "+BATT" H 1000 800 30 0000 C CNN
1 1000 700
1 0 0 -1
$EndComp
$Comp
L +BATT #PWR024
U 1 1 4C859B70
P 6200 700
F 0 "#PWR024" H 6200 650 20 0001 C CNN
F 1 "+BATT" H 6200 800 30 0000 C CNN
1 6200 700
1 0 0 -1
$EndComp
$Comp
L +BATT #PWR025
U 1 1 4C859B63
@ -539,8 +539,6 @@ Text Label 7750 5100 0 40 Italic 0
3.3V_EN
Text Notes 1550 4350 0 80 ~ 16
Labels problems!!
Text Label 7200 5500 0 50 ~ 10
WATCHDOG
$Comp
L CONN_4 P1
U 1 1 4C7FD562
@ -1066,7 +1064,7 @@ Text Label 7750 5400 0 40 Italic 0
Iout_1.2
Text Label 7750 5300 0 40 Italic 0
1.2V_EN
Text Label 700 1100 0 40 Italic 0
Text Label 600 1100 0 40 Italic 0
Iout_3.3
Text Label 5900 1100 0 60 ~ 12
Iout_1.2

6
kicad/xue-rnc/USB.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""
@ -427,7 +427,7 @@ F 1 "24" V 2500 2750 50 0000 C CNN
1 2500 2750
0 1 1 0
$EndComp
Text Label 5450 6600 0 40 ~ 0
Text Label 5400 6600 0 40 ~ 0
USB_CASE_DEV
Text Label 5850 2950 0 40 ~ 0
USB_CASE_HOST

6
kicad/xue-rnc/eth_phy.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -49,9 +49,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 7 9
Sheet 8 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""

2
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Mon 06 Sep 2010 09:03:31 PM COT
EESchema-LIBRARY Version 2.3 Date: Thu 09 Sep 2010 05:45:02 PM COT
#
# +1.2V
#

21930
kicad/xue-rnc/xue-rnc.brd
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File diff suppressed because it is too large Load Diff

6
kicad/xue-rnc/xue-rnc.cmp
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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2010-08-29 BZR 2460)-unstable date = Fri 03 Sep 2010 10:58:24 AM COT
Cmp-Mod V01 Created by CvPCB (2010-08-29 BZR 2460)-unstable date = Thu 09 Sep 2010 02:23:34 PM COT
BeginCmp
TimeStamp = /4C4320F3/4C5D7F9F;
@ -81,7 +81,7 @@ BeginCmp
TimeStamp = /4C4320F3/4C5D7DCB;
Reference = C12;
ValeurCmp = 47nF;
IdModule = 0402;
IdModule = 1206;
EndCmp
BeginCmp
@ -879,7 +879,7 @@ BeginCmp
TimeStamp = /4C4320F3/4C5D7DC4;
Reference = R9;
ValeurCmp = 1M;
IdModule = 0402;
IdModule = 1206;
EndCmp
BeginCmp

1874
kicad/xue-rnc/xue-rnc.net
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File diff suppressed because it is too large Load Diff

8
kicad/xue-rnc/xue-rnc.pro
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@ -1,6 +1,6 @@
update=Mon 06 Sep 2010 09:03:37 PM COT
update=Thu 09 Sep 2010 05:49:09 PM COT
version=1
last_client=kicad
last_client=pcbnew
[common]
NetDir=
[eeschema]
@ -88,6 +88,8 @@ version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PadDrlX=360
@ -140,5 +142,3 @@ LibName29=../modules/DFN10
LibName30=../modules/MLF16
LibName31=../modules/USBD
LibName32=../modules/MLP6
[general]
version=1

4
kicad/xue-rnc/xue-rnc.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 06 Sep 2010 09:03:31 PM COT
EESchema Schematic File Version 2 date Thu 09 Sep 2010 05:45:02 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -51,7 +51,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 1 9
Title ""
Date "7 sep 2010"
Date "9 sep 2010"
Rev ""
Comp ""
Comment1 ""