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Code

ddr address and data has been conected to the FPGA

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This commit is contained in:
Andres Calderon 2010-08-04 20:50:31 -05:00
parent 3e25e8dec9
commit 5197a47953
9 changed files with 1931 additions and 1146 deletions
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6
kicad/xue-rnc/DRAM.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -45,9 +45,9 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Wire Bus Line Wire Bus Line
10150 5100 10250 5100 10250 5100 10150 5100
Wire Bus Line Wire Bus Line
10150 3150 10150 5100 10150 5100 10150 3150
Wire Bus Line Wire Bus Line
1900 4250 1900 5100 1900 4250 1900 5100
Wire Wire Line Wire Wire Line

1202
kicad/xue-rnc/FPGA.sch
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File diff suppressed because it is too large Load Diff

2
kicad/xue-rnc/NV_MEMORIES.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors

2
kicad/xue-rnc/eth_phy.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors

2
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Tue 03 Aug 2010 09:21:21 PM COT EESchema-LIBRARY Version 2.3 Date: Wed 04 Aug 2010 12:20:40 PM COT
# #
# GND # GND
# #

974
kicad/xue-rnc/xue-rnc.brd
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File diff suppressed because it is too large Load Diff

856
kicad/xue-rnc/xue-rnc.net
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File diff suppressed because it is too large Load Diff

2
kicad/xue-rnc/xue-rnc.pro
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@ -1,4 +1,4 @@
update=Tue 03 Aug 2010 09:21:55 PM COT update=Wed 04 Aug 2010 07:51:52 PM COT
version=1 version=1
last_client=pcbnew last_client=pcbnew
[general] [general]

31
kicad/xue-rnc/xue-rnc.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -44,24 +44,24 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Wire Bus Line
2750 3350 4000 3350
Wire Wire Line Wire Wire Line
4000 2300 2750 2300 2750 2200 4000 2200
Wire Wire Line
2750 4250 4000 4250
Wire Bus Line
2750 3250 4000 3250
Wire Bus Line
4000 3250 4000 3300
Wire Wire Line
7800 4550 7350 4550
Wire Wire Line Wire Wire Line
2750 4350 4000 4350 2750 4350 4000 4350
Wire Wire Line Wire Wire Line
7800 4550 7350 4550 4000 2300 2750 2300
Wire Bus Line Wire Bus Line
4000 3300 4000 3250 2750 1250 4000 1250
Wire Bus Line
4000 3250 2750 3250
Wire Bus Line
4000 1200 4000 1150
Wire Wire Line
2750 4250 4000 4250
Wire Wire Line
2750 2200 4000 2200
Wire Bus Line
4000 1150 2750 1150
$Sheet $Sheet
S 7800 4450 1450 2200 S 7800 4450 1450 2200
U 4C4320F3 U 4C4320F3
@ -93,6 +93,9 @@ F3 "M1_CLK#" O L 4000 2300 60
F4 "M0_CLK" O L 4000 4250 60 F4 "M0_CLK" O L 4000 4250 60
F5 "M0_CLK#" O L 4000 4350 60 F5 "M0_CLK#" O L 4000 4350 60
F6 "ETH_INT" I R 7350 4550 60 F6 "ETH_INT" I R 7350 4550 60
F7 "M0_A[0..12]" O L 4000 3350 60
F8 "M1_A[0..12]" O L 4000 1250 60
F9 "M0_DQ[0..15]" B L 4000 3250 60
$EndSheet $EndSheet
$Sheet $Sheet
S 8700 900 1150 1850 S 8700 900 1150 1850