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ddr address and data has been conected to the FPGA
This commit is contained in:
parent
3e25e8dec9
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@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
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EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -45,9 +45,9 @@ Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Bus Line
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10150 5100 10250 5100
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10250 5100 10150 5100
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Wire Bus Line
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10150 3150 10150 5100
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10150 5100 10150 3150
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Wire Bus Line
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1900 4250 1900 5100
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Wire Wire Line
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File diff suppressed because it is too large
Load Diff
@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
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EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
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EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -1,4 +1,4 @@
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EESchema-LIBRARY Version 2.3 Date: Tue 03 Aug 2010 09:21:21 PM COT
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EESchema-LIBRARY Version 2.3 Date: Wed 04 Aug 2010 12:20:40 PM COT
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#
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# GND
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#
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File diff suppressed because it is too large
Load Diff
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update=Tue 03 Aug 2010 09:21:55 PM COT
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update=Wed 04 Aug 2010 07:51:52 PM COT
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version=1
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last_client=pcbnew
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[general]
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@ -1,4 +1,4 @@
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EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
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EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT
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LIBS:power
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LIBS:device
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LIBS:transistors
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@ -44,24 +44,24 @@ Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Bus Line
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2750 3350 4000 3350
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Wire Wire Line
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4000 2300 2750 2300
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2750 2200 4000 2200
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Wire Wire Line
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2750 4250 4000 4250
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Wire Bus Line
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2750 3250 4000 3250
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Wire Bus Line
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4000 3250 4000 3300
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Wire Wire Line
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7800 4550 7350 4550
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Wire Wire Line
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2750 4350 4000 4350
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Wire Wire Line
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7800 4550 7350 4550
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4000 2300 2750 2300
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Wire Bus Line
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4000 3300 4000 3250
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Wire Bus Line
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4000 3250 2750 3250
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Wire Bus Line
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4000 1200 4000 1150
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Wire Wire Line
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2750 4250 4000 4250
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Wire Wire Line
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2750 2200 4000 2200
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Wire Bus Line
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4000 1150 2750 1150
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2750 1250 4000 1250
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$Sheet
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S 7800 4450 1450 2200
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U 4C4320F3
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@ -93,6 +93,9 @@ F3 "M1_CLK#" O L 4000 2300 60
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F4 "M0_CLK" O L 4000 4250 60
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F5 "M0_CLK#" O L 4000 4350 60
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F6 "ETH_INT" I R 7350 4550 60
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F7 "M0_A[0..12]" O L 4000 3350 60
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F8 "M1_A[0..12]" O L 4000 1250 60
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F9 "M0_DQ[0..15]" B L 4000 3250 60
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$EndSheet
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$Sheet
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S 8700 900 1150 1850
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