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Code

Connecting some FPGA's free GPIO

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This commit is contained in:
Juan64Bits 2010-10-09 16:11:11 -05:00
parent cc01f3c764
commit 874a01d2d8
16 changed files with 1729 additions and 778 deletions
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456
kicad/modules/CON_40Pin_2mm.mod Executable file
View File

@ -0,0 +1,456 @@
PCBNEW-LibModule-V1 Sat 08 May 2010 02:28:45 PM COT
$INDEX
CON_40Pin_2mm
$EndINDEX
$MODULE CON_40Pin_2mm
Po 0 0 0 15 4BAADD91 4BE5BB49 ~~
Li CON_40Pin_2mm
Sc 4BE5BB49
AR /4B8F5BC1/4B7C65CF
Op 0 0 0
T0 16146 242 315 315 900 31 N V 21 N"CON_40Pin_2mm"
T1 0 118 118 118 -2700 20 N I 21 N"VAL"
T2 16154 -830 315 315 900 31 N V 21 N"40"
T2 -750 -822 315 315 900 31 N V 21 N"2"
T2 -654 586 315 315 900 31 N V 21 N"1"
DS 11120 -900 11120 100 40 26
DS 11120 100 10920 100 40 26
DS 10920 100 10920 -900 40 26
DS 10340 -900 10340 100 40 26
DS 10340 100 10140 100 40 26
DS 10140 100 10140 -900 40 26
DS 8760 -900 8760 100 40 26
DS 8760 100 8560 100 40 26
DS 8560 100 8560 -900 40 26
DS 9550 -900 9550 100 40 26
DS 9550 100 9350 100 40 26
DS 9350 100 9350 -900 40 26
DS 7970 -900 7970 100 40 26
DS 7970 100 7770 100 40 26
DS 7770 100 7770 -900 40 26
DS 7190 -900 7190 100 40 26
DS 7190 100 6990 100 40 26
DS 6990 100 6990 -900 40 26
DS 6400 -900 6400 100 40 26
DS 6400 100 6200 100 40 26
DS 6200 100 6200 -900 40 26
DS 5610 -900 5610 100 40 26
DS 5610 100 5410 100 40 26
DS 5410 100 5410 -900 40 26
DS 4820 -900 4820 100 40 26
DS 4820 100 4620 100 40 26
DS 4620 100 4620 -900 40 26
DS 4040 -900 4040 100 40 26
DS 4040 100 3840 100 40 26
DS 3840 100 3840 -900 40 26
DS -750 -250 -750 250 80 26
DS -750 250 -500 0 80 26
DS -500 0 -750 -250 80 26
DS 13490 -900 13490 100 40 26
DS 13490 100 13290 100 40 26
DS 13290 100 13290 -900 40 26
DS 11910 -900 11910 100 40 26
DS 11910 100 11710 100 40 26
DS 11710 100 11710 -900 40 26
DS -750 -250 -750 250 80 21
DS -750 250 -500 0 80 21
DS -500 0 -750 -250 80 21
DS -330 -790 -590 -790 60 26
DS -590 -790 -590 -1460 60 26
DS -590 -1460 15550 -1460 60 26
DS 15550 -1460 15550 -790 60 26
DS 15550 -790 15260 -790 60 26
DS 15260 -790 15260 -900 60 26
DS 15260 -900 14660 -900 60 26
DS 14660 -900 14660 -790 60 26
DS 14660 -790 14470 -790 60 26
DS 14470 -790 14470 -900 60 26
DS 14470 -900 13870 -900 60 26
DS 13870 -900 13870 -790 60 26
DS 13870 -790 13690 -790 60 26
DS 13690 -790 13690 -900 60 26
DS 13690 -900 13090 -900 60 26
DS 13090 -900 13090 -790 60 26
DS 13090 -790 12900 -790 60 26
DS 12900 -790 12900 -900 60 26
DS 12900 -900 12300 -900 60 26
DS 12300 -900 12300 -790 60 26
DS 12300 -790 12110 -790 60 26
DS 12110 -790 12110 -900 60 26
DS 12110 -900 11510 -900 60 26
DS 11510 -900 11510 -790 60 26
DS 11510 -790 11320 -790 60 26
DS 11320 -790 11320 -900 60 26
DS 11320 -900 10720 -900 60 26
DS 10720 -900 10720 -790 60 26
DS 10720 -790 10540 -790 60 26
DS 10540 -790 10540 -900 60 26
DS 10540 -900 9940 -900 60 26
DS 9940 -900 9940 -790 60 26
DS 9940 -790 9750 -790 60 26
DS 9750 -790 9750 -900 60 26
DS 9750 -900 9150 -900 60 26
DS 9150 -900 9150 -790 60 26
DS 9150 -790 8960 -790 60 26
DS 8960 -790 8960 -900 60 26
DS 8960 -900 8360 -900 60 26
DS 8360 -900 8360 -790 60 26
DS 8360 -790 8170 -790 60 26
DS 8170 -790 8170 -900 60 26
DS 8170 -900 7570 -900 60 26
DS 7570 -900 7570 -790 60 26
DS 7570 -790 7390 -790 60 26
DS 7390 -790 7390 -900 60 26
DS 7390 -900 6790 -900 60 26
DS 6790 -900 6790 -790 60 26
DS 6790 -790 6600 -790 60 26
DS 6600 -790 6600 -900 60 26
DS 6600 -900 6000 -900 60 26
DS 6000 -900 6000 -790 60 26
DS 6000 -790 5810 -790 60 26
DS 5810 -790 5810 -900 60 26
DS 5810 -900 5210 -900 60 26
DS 5210 -900 5210 -790 60 26
DS 5210 -790 5020 -790 60 26
DS 5020 -790 5020 -900 60 26
DS 5020 -900 4420 -900 60 26
DS 4420 -900 4420 -790 60 26
DS 4420 -790 4240 -790 60 26
DS 4240 -790 4240 -900 60 26
DS 4240 -900 3640 -900 60 26
DS 3640 -900 3640 -790 60 26
DS 3640 -790 3450 -790 60 26
DS 3450 -790 3450 -900 60 26
DS 3450 -900 2850 -900 60 26
DS 2850 -900 2850 -790 60 26
DS 2850 -790 2660 -790 60 26
DS 2660 -790 2660 -900 60 26
DS 2660 -900 2060 -900 60 26
DS 2060 -900 2060 -790 60 26
DS 2060 -790 1870 -790 60 26
DS 1870 -790 1870 -900 60 26
DS 1870 -900 1270 -900 60 26
DS 1270 -900 1270 -790 60 26
DS 1270 -790 1090 -790 60 26
DS 1090 -790 1090 -900 60 26
DS 1090 -900 490 -900 60 26
DS 490 -900 490 -790 60 26
DS 490 -790 300 -790 60 26
DS 300 -790 300 -900 60 26
DS 300 -900 -330 -900 60 26
DS -330 -900 -330 -790 60 26
DS 12700 -900 12700 100 40 26
DS 12700 100 12500 100 40 26
DS 12500 100 12500 -900 40 26
DS 100 -900 100 100 40 26
DS 100 100 -100 100 40 26
DS -100 100 -100 -900 40 26
DS 890 -900 890 100 40 26
DS 890 100 690 100 40 26
DS 690 100 690 -900 40 26
DS 1680 -900 1680 100 40 26
DS 1680 100 1480 100 40 26
DS 1480 100 1480 -900 40 26
DS 2470 -900 2470 100 40 26
DS 2470 100 2270 100 40 26
DS 2270 100 2270 -900 40 26
DS 3250 -900 3250 100 40 26
DS 3250 100 3050 100 40 26
DS 3050 100 3050 -900 40 26
DS 15060 -900 15060 100 40 26
DS 15060 100 14860 100 40 26
DS 14860 100 14860 -900 40 26
DS -370 -1460 15820 -1460 80 21
DS 15820 -1460 15820 560 80 21
DS 15820 560 -380 560 80 21
DS -380 560 -370 390 80 21
DS -370 390 -370 -1450 80 21
DS 14260 -900 14260 100 40 26
DS 14260 100 14060 100 40 26
DS 14060 100 14060 -900 40 26
DS -900 710 -900 -1610 10 24
DS -900 -1610 15970 -1610 10 24
DS 15970 -1610 15970 710 10 24
DS 15970 710 -900 710 10 24
$PAD
Sh "1" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 0 0
$EndPAD
$PAD
Sh "2" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 0 -790
$EndPAD
$PAD
Sh "3" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 790 0
$EndPAD
$PAD
Sh "4" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 790 -790
$EndPAD
$PAD
Sh "5" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 1570 0
$EndPAD
$PAD
Sh "6" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 1570 -790
$EndPAD
$PAD
Sh "7" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 2360 0
$EndPAD
$PAD
Sh "8" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 2360 -790
$EndPAD
$PAD
Sh "9" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 3150 0
$EndPAD
$PAD
Sh "10" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 3150 -790
$EndPAD
$PAD
Sh "11" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 3940 0
$EndPAD
$PAD
Sh "12" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 3940 -790
$EndPAD
$PAD
Sh "13" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 4720 0
$EndPAD
$PAD
Sh "14" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 4720 -790
$EndPAD
$PAD
Sh "15" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 5510 0
$EndPAD
$PAD
Sh "16" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 5510 -790
$EndPAD
$PAD
Sh "17" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 6300 0
$EndPAD
$PAD
Sh "18" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 6300 -790
$EndPAD
$PAD
Sh "19" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 7090 0
$EndPAD
$PAD
Sh "20" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 7090 -790
$EndPAD
$PAD
Sh "21" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 7870 0
$EndPAD
$PAD
Sh "22" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 7870 -790
$EndPAD
$PAD
Sh "23" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 8660 0
$EndPAD
$PAD
Sh "24" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 8660 -790
$EndPAD
$PAD
Sh "25" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 9450 0
$EndPAD
$PAD
Sh "26" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 9450 -790
$EndPAD
$PAD
Sh "27" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 10240 0
$EndPAD
$PAD
Sh "28" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 10240 -790
$EndPAD
$PAD
Sh "29" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 11020 0
$EndPAD
$PAD
Sh "30" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 11020 -790
$EndPAD
$PAD
Sh "31" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 11810 0
$EndPAD
$PAD
Sh "32" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 11810 -790
$EndPAD
$PAD
Sh "33" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 12600 0
$EndPAD
$PAD
Sh "34" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 12600 -790
$EndPAD
$PAD
Sh "35" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 13390 0
$EndPAD
$PAD
Sh "36" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 13390 -790
$EndPAD
$PAD
Sh "37" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 14170 0
$EndPAD
$PAD
Sh "38" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 14170 -790
$EndPAD
$PAD
Sh "39" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 14960 0
$EndPAD
$PAD
Sh "40" C 520 520 0 0 0
Dr 340 0 0
At STD N 00C08001
Ne 0 ""
Po 14960 -790
$EndPAD
$EndMODULE CON_40Pin_2mm
$EndLIBRARY

6
kicad/xue-rnc/DBG_PRG.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 4 11
Sheet 6 12
Title ""
Date "8 oct 2010"
Date "9 oct 2010"
Rev ""
Comp ""
Comment1 ""

6
kicad/xue-rnc/DRAM.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 9 11
Sheet 9 12
Title ""
Date "8 oct 2010"
Date "9 oct 2010"
Rev ""
Comp ""
Comment1 ""

46
kicad/xue-rnc/FPGA_0_2_PROG.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A3 16535 11700
Sheet 4 11
Sheet 5 12
Title ""
Date "8 oct 2010"
Date "9 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -63,6 +63,46 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text HLabel 3200 3950 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AA18
Text HLabel 3200 1650 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AB21
Text HLabel 3200 2350 0 40 BiDi ~ 0
FPGA_VCCO2_IO_W18
Text HLabel 3200 5050 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AB16
Text HLabel 3200 5450 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AB15
Text HLabel 7200 4650 2 40 BiDi ~ 0
FPGA_VCCO2_IO_V7
Text HLabel 7200 3350 2 40 BiDi ~ 0
FPGA_VCCO2_IO_W6
Text HLabel 7200 2150 2 40 BiDi ~ 0
FPGA_VCCO2_IO_W4
Text HLabel 7200 5050 2 40 BiDi ~ 0
FPGA_VCCO2_IO_Y10
Text HLabel 7200 5350 2 40 BiDi ~ 0
FPGA_VCCO2_IO_Y9
Text HLabel 3200 5350 0 40 BiDi ~ 0
FPGA_VCCO2_IO_Y15
Text HLabel 3200 4550 0 40 BiDi ~ 0
FPGA_VCCO2_IO_Y16
Text HLabel 7200 5150 2 40 BiDi ~ 0
FPGA_VCCO2_IO_W10
Text HLabel 7200 5450 2 40 BiDi ~ 0
FPGA_VCCO2_IO_W11
Text HLabel 3200 6150 0 40 BiDi ~ 0
FPGA_VCCO2_IO_Y12
Text HLabel 3200 4450 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AB14
Text HLabel 3200 6250 0 40 BiDi ~ 0
FPGA_VCCO2_IO_AB13
Text HLabel 7200 6150 2 40 BiDi ~ 0
FPGA_VCCO2_IO_Y11
Text HLabel 7200 4750 2 40 BiDi ~ 0
FPGA_VCCO2_IO_W8
Text HLabel 7200 3950 2 40 BiDi ~ 0
FPGA_VCCO2_IO_U9
Text HLabel 7200 1650 2 40 Input ~ 0
IS_FRAME
Text HLabel 7200 1750 2 40 Input ~ 0

482
kicad/xue-rnc/FPGA_1_3.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A3 16535 11700
Sheet 5 11
Sheet 5 12
Title ""
Date "8 oct 2010"
Date "9 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -63,8 +63,46 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Label 5600 5100 0 40 ~ 0
GND
Text HLabel 11500 7500 2 40 BiDi ~ 0
FPGA_2.5V_IO_M17
Text HLabel 11500 7200 2 40 BiDi ~ 0
FPGA_2.5V_IO_N16
Text HLabel 11500 8300 2 40 BiDi ~ 0
FPGA_2.5V_IO_P19
Text HLabel 11500 7300 2 40 BiDi ~ 0
FPGA_2.5V_IO_P17
Text HLabel 11500 7100 2 40 BiDi ~ 0
FPGA_2.5V_IO_P18
Text HLabel 11500 7700 2 40 BiDi ~ 0
FPGA_2.5V_IO_U19
Text HLabel 11500 6800 2 40 BiDi ~ 0
FPGA_2.5V_IO_T20
Text HLabel 11500 7600 2 40 BiDi ~ 0
FPGA_2.5V_IO_V20
Text HLabel 11500 8100 2 40 BiDi ~ 0
FPGA_2.5V_IO_W20
Text HLabel 11500 8000 2 40 BiDi ~ 0
FPGA_2.5V_IO_W22
Text HLabel 7700 2500 0 40 BiDi ~ 0
FPGA_2.5V_IO_V3
Text HLabel 7700 2400 0 40 BiDi ~ 0
FPGA_2.5V_IO_U4
Text HLabel 7700 2300 0 40 BiDi ~ 0
FPGA_2.5V_IO_T3
Text HLabel 7700 2200 0 40 BiDi ~ 0
FPGA_2.5V_IO_T4
Text HLabel 7700 1900 0 40 BiDi ~ 0
FPGA_2.5V_IO_P7
Text HLabel 7700 1800 0 40 BiDi ~ 0
FPGA_2.5V_IO_P8
Text HLabel 7700 1700 0 40 BiDi ~ 0
FPGA_2.5V_IO_W1
Text HLabel 7700 1600 0 40 BiDi ~ 0
FPGA_2.5V_IO_W3
Text HLabel 7700 1500 0 40 BiDi ~ 0
FPGA_2.5V_IO_Y1
Text HLabel 7700 1400 0 40 BiDi ~ 0
FPGA_2.5V_IO_Y2
Wire Wire Line
7100 9100 6650 9100
Wire Wire Line
@ -72,56 +110,58 @@ Wire Wire Line
Wire Wire Line
4500 4150 5050 4150
Wire Wire Line
11300 3600 11800 3600
11900 3600 12400 3600
Wire Wire Line
11300 5800 11800 5800
11900 5800 12400 5800
Wire Wire Line
7100 5500 6500 5500
7700 5500 7100 5500
Wire Wire Line
7100 5700 6500 5700
7700 5700 7100 5700
Wire Wire Line
7100 4600 6500 4600
7700 4600 7100 4600
Wire Wire Line
7100 4800 6500 4800
7700 4800 7100 4800
Wire Wire Line
7100 5000 6500 5000
7700 5000 7100 5000
Wire Wire Line
7100 5200 6500 5200
7700 5200 7100 5200
Wire Wire Line
7100 4200 6500 4200
7700 4200 7100 4200
Wire Wire Line
3900 4300 4000 4300
Wire Wire Line
11300 4200 11800 4200
11900 4200 12400 4200
Wire Wire Line
11300 5500 11850 5500
Connection ~ 11700 4900
11900 5500 12450 5500
Connection ~ 12300 4900
Wire Wire Line
11700 4950 11700 4850
12300 4950 12300 4900
Wire Wire Line
11700 4850 12250 4850
12300 4900 12300 4850
Wire Wire Line
11300 4900 11700 4900
12300 4850 12850 4850
Wire Wire Line
11800 5300 11300 5300
11900 4900 12300 4900
Wire Wire Line
11800 4800 11300 4800
12400 5300 11900 5300
Wire Wire Line
11800 4600 11300 4600
12400 4800 11900 4800
Wire Wire Line
11800 4400 11300 4400
12400 4600 11900 4600
Wire Wire Line
11800 4000 11300 4000
12400 4400 11900 4400
Wire Wire Line
11800 3800 11300 3800
12400 4000 11900 4000
Wire Wire Line
11800 3500 11300 3500
12400 3800 11900 3800
Wire Wire Line
12400 3500 11900 3500
Wire Bus Line
2200 1500 2250 1500
Wire Wire Line
7100 4100 6500 4100
7700 4100 7100 4100
Wire Wire Line
7100 3900 6500 3900
7700 3900 7100 3900
Wire Wire Line
5650 2950 5200 2950
Wire Wire Line
@ -259,7 +299,9 @@ Wire Wire Line
Wire Wire Line
5800 10000 5800 9900
Wire Wire Line
5700 9900 6400 9900
5700 9900 5800 9900
Wire Wire Line
5800 9900 6400 9900
Wire Wire Line
6400 9900 6400 10000
Wire Wire Line
@ -397,9 +439,57 @@ Wire Wire Line
Wire Wire Line
2750 2850 2350 2850
Wire Bus Line
2250 1500 2250 2750
2250 1500 2250 1550
Wire Bus Line
1400 6350 1400 7600
2250 1550 2250 1650
Wire Bus Line
2250 1650 2250 1750
Wire Bus Line
2250 1750 2250 1850
Wire Bus Line
2250 1850 2250 1950
Wire Bus Line
2250 1950 2250 2050
Wire Bus Line
2250 2050 2250 2150
Wire Bus Line
2250 2150 2250 2250
Wire Bus Line
2250 2250 2250 2350
Wire Bus Line
2250 2350 2250 2450
Wire Bus Line
2250 2450 2250 2550
Wire Bus Line
2250 2550 2250 2650
Wire Bus Line
2250 2650 2250 2750
Wire Bus Line
1400 6350 1400 6400
Wire Bus Line
1400 6400 1400 6500
Wire Bus Line
1400 6500 1400 6600
Wire Bus Line
1400 6600 1400 6700
Wire Bus Line
1400 6700 1400 6800
Wire Bus Line
1400 6800 1400 6900
Wire Bus Line
1400 6900 1400 7000
Wire Bus Line
1400 7000 1400 7100
Wire Bus Line
1400 7100 1400 7200
Wire Bus Line
1400 7200 1400 7300
Wire Bus Line
1400 7300 1400 7400
Wire Bus Line
1400 7400 1400 7500
Wire Bus Line
1400 7500 1400 7600
Connection ~ 9600 6350
Wire Wire Line
9600 6350 9600 6400
@ -413,42 +503,78 @@ Wire Wire Line
Wire Wire Line
9700 6400 9700 6350
Wire Wire Line
9700 6350 8800 6350
9700 6350 9600 6350
Wire Wire Line
9600 6350 9500 6350
Wire Wire Line
9500 6350 9400 6350
Wire Wire Line
9400 6350 9300 6350
Wire Wire Line
9300 6350 9200 6350
Wire Wire Line
9200 6350 9100 6350
Wire Wire Line
9100 6350 9000 6350
Wire Wire Line
9000 6350 8900 6350
Wire Wire Line
8900 6350 8800 6350
Wire Wire Line
8800 6350 8800 6400
Connection ~ 9000 950
Wire Wire Line
9000 950 9000 1000
Connection ~ 8800 950
Wire Wire Line
8800 1000 8800 950
Connection ~ 9500 950
Wire Wire Line
9500 950 9500 1000
Connection ~ 9300 950
Wire Wire Line
9300 950 9300 1000
Wire Wire Line
9700 1000 9700 950
Wire Wire Line
9700 950 8700 950
Wire Wire Line
8700 950 8700 1000
Connection ~ 9200 950
Wire Wire Line
9200 850 9200 1000
Wire Wire Line
9400 950 9400 1000
Connection ~ 9400 950
Wire Wire Line
9600 950 9600 1000
Connection ~ 9600 950
Wire Wire Line
8900 950 8900 1000
Connection ~ 8900 950
9600 950 9600 1000
Connection ~ 9400 950
Wire Wire Line
9100 950 9100 1000
Connection ~ 9100 950
9400 1000 9400 950
Connection ~ 10100 950
Wire Wire Line
10100 950 10100 1000
Connection ~ 9900 950
Wire Wire Line
9900 950 9900 1000
Wire Wire Line
10300 1000 10300 950
Wire Wire Line
10300 950 10200 950
Wire Wire Line
10200 950 10100 950
Wire Wire Line
10100 950 10000 950
Wire Wire Line
10000 950 9900 950
Wire Wire Line
9900 950 9800 950
Wire Wire Line
9800 950 9700 950
Wire Wire Line
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6
kicad/xue-rnc/NV_MEMORIES.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
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6
kicad/xue-rnc/PSU.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
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LIBS:v0402mhs03
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6
kicad/xue-rnc/USB.sch
View File

@ -1,4 +1,4 @@
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6
kicad/xue-rnc/eth_phy.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
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75
kicad/xue-rnc/expantion.sch Normal file
View File

@ -0,0 +1,75 @@
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
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LIBS:v0402mhs03
LIBS:usb-48204-0001
LIBS:microsmd075f
LIBS:mic2550
LIBS:rj45-48025
LIBS:xue-nv
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LIBS:device
LIBS:transistors
LIBS:conn
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LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
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LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
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LIBS:valves
LIBS:pasives-connectors
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$EndSCHEMATC

6
kicad/xue-rnc/sensor.sch
View File

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EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
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6
kicad/xue-rnc/sensor_psu.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
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52
kicad/xue-rnc/xue-rnc-cache.lib
View File

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EESchema-LIBRARY Version 2.3 Date: Fri 08 Oct 2010 11:41:21 AM COT
EESchema-LIBRARY Version 2.3 Date: Sat 09 Oct 2010 04:08:56 PM COT
#
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#
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#
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550
kicad/xue-rnc/xue-rnc.brd
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File diff suppressed because it is too large Load Diff

6
kicad/xue-rnc/xue-rnc.pro
View File

@ -1,4 +1,4 @@
update=Fri 08 Oct 2010 11:44:31 AM COT
update=Sat 09 Oct 2010 04:09:08 PM COT
version=1
last_client=pcbnew
[common]
@ -89,13 +89,13 @@ LibName47=../library/tps793xx
LibName48=../library/reg102
LibName49=../library/mt9m033
LibName50=../library/m12-tu400a
[general]
version=1
[cvpcb]
version=1
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EquName1=devcms
[general]
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version=1
PadDrlX=0

792
kicad/xue-rnc/xue-rnc.sch
View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 08 Oct 2010 11:41:21 AM COT
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -52,10 +52,10 @@ LIBS:m12-tu400a
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$Descr A3 16535 11700
Sheet 1 11
$Descr A2 23400 16535
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Title ""
Date "8 oct 2010"
Date "9 oct 2010"
Rev ""
Comp ""
Comment1 ""
@ -63,424 +63,470 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
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Wire Bus Line
10650 8700 9300 8700
Wire Wire Line
10650 8300 9300 8300
Wire Wire Line
10650 8400 9300 8400
Wire Wire Line
10650 8600 9300 8600
Wire Wire Line
10650 8950 9300 8950
Wire Wire Line
10650 9050 9300 9050
Wire Wire Line
5950 6550 4950 6550
Wire Wire Line
5950 6750 4950 6750
Wire Wire Line
10600 1650 9250 1650
Wire Wire Line
10600 1850 9250 1850
Wire Wire Line
3150 8600 3400 8600
Wire Wire Line
3150 8900 3400 8900
Wire Wire Line
3150 9200 3400 9200
Wire Bus Line
5950 9000 4950 9000
Wire Wire Line
4950 7700 5950 7700
Wire Wire Line
5950 7900 4950 7900
Wire Wire Line
4950 8100 5950 8100
Wire Wire Line
4950 8300 5950 8300
Wire Wire Line
4950 7500 5950 7500
Wire Wire Line
4950 8500 5950 8500
$Sheet
S 3400 7300 1550 2050
S 14800 5850 1100 5850
U 4CB0D95D
F0 "FPGA GPIOS" 60
F1 "expantion.sch" 60
$EndSheet
Wire Wire Line
9100 4950 10100 4950
Wire Wire Line
9100 4750 10100 4750
Wire Wire Line
10100 3750 9100 3750
Wire Wire Line
9100 4550 10100 4550
Wire Wire Line
9100 4350 10100 4350
Wire Wire Line
9100 4150 10100 4150
Wire Wire Line
10100 3950 9100 3950
Wire Wire Line
7300 5400 7550 5400
Wire Wire Line
7300 5100 7550 5100
Wire Wire Line
14750 13050 13400 13050
Wire Wire Line
14750 12850 13400 12850
Wire Wire Line
14750 12650 13400 12650
Wire Wire Line
9100 6950 10100 6950
Wire Wire Line
10100 6750 9100 6750
Wire Bus Line
14800 5500 13450 5500
Wire Wire Line
14800 4450 13450 4450
Wire Wire Line
14800 4850 13450 4850
Wire Wire Line
13450 4550 14800 4550
Wire Wire Line
14750 2200 13450 2200
Wire Bus Line
13450 4100 14800 4100
Wire Wire Line
13450 3900 14800 3900
Wire Wire Line
14750 12450 13400 12450
Wire Wire Line
14750 12250 13400 12250
Wire Wire Line
14750 12050 13400 12050
Wire Wire Line
13450 3200 14750 3200
Wire Wire Line
13450 2800 14750 2800
Wire Wire Line
14750 2300 13450 2300
Wire Wire Line
13450 1900 14750 1900
Wire Bus Line
8850 9850 10100 9850
Wire Wire Line
8850 9500 10100 9500
Wire Wire Line
8850 10450 10100 10450
Wire Wire Line
8850 10600 10100 10600
Wire Wire Line
8850 10950 10100 10950
Wire Wire Line
8850 12650 10100 12650
Wire Wire Line
8850 13250 10100 13250
Wire Bus Line
8850 11950 10100 11950
Wire Wire Line
8850 13000 10100 13000
Wire Wire Line
8850 12400 10100 12400
Wire Wire Line
8850 12100 10100 12100
Wire Bus Line
8850 9750 10100 9750
Wire Wire Line
10100 10800 8850 10800
Wire Wire Line
8850 12850 10100 12850
Wire Bus Line
10100 11800 10100 11750
Wire Bus Line
10100 11750 8850 11750
Wire Wire Line
8850 12750 10100 12750
Wire Wire Line
8850 10700 10100 10700
Wire Bus Line
8850 11850 10100 11850
Wire Wire Line
8850 12500 10100 12500
Wire Wire Line
8850 12200 10100 12200
Wire Wire Line
8850 13100 10100 13100
Wire Wire Line
8850 11600 10100 11600
Wire Wire Line
8850 11050 10100 11050
Wire Wire Line
8850 11200 10100 11200
Wire Wire Line
8850 10350 10100 10350
Wire Wire Line
8850 10150 10100 10150
Wire Wire Line
8850 10050 10100 10050
Wire Bus Line
8850 9650 10100 9650
Wire Wire Line
13450 1750 14750 1750
Wire Wire Line
13450 2000 14750 2000
Wire Wire Line
13450 2400 14750 2400
Wire Wire Line
13450 2700 14750 2700
Wire Wire Line
13450 2900 14750 2900
Wire Wire Line
13450 3100 14750 3100
Wire Wire Line
13450 3300 14750 3300
Wire Wire Line
14750 12150 13400 12150
Wire Wire Line
14750 12350 13400 12350
Wire Bus Line
13450 3000 14750 3000
Wire Bus Line
14750 2600 13450 2600
Wire Wire Line
13450 4000 14800 4000
Wire Wire Line
14750 2100 13450 2100
Wire Bus Line
14800 5050 13450 5050
Wire Wire Line
14800 4650 13450 4650
Wire Wire Line
14800 4750 13450 4750
Wire Wire Line
14800 4950 13450 4950
Wire Wire Line
14800 5300 13450 5300
Wire Wire Line
14800 5400 13450 5400
Wire Wire Line
10100 6850 9100 6850
Wire Wire Line
10100 7050 9100 7050
Wire Wire Line
14750 12750 13400 12750
Wire Wire Line
14750 12950 13400 12950
Wire Wire Line
7300 4950 7550 4950
Wire Wire Line
7300 5250 7550 5250
Wire Wire Line
7300 5550 7550 5550
Wire Bus Line
10100 5350 9100 5350
Wire Wire Line
9100 4050 10100 4050
Wire Wire Line
10100 4250 9100 4250
Wire Wire Line
9100 4450 10100 4450
Wire Wire Line
9100 4650 10100 4650
Wire Wire Line
9100 3850 10100 3850
Wire Wire Line
9100 4850 10100 4850
$Sheet
S 7550 3650 1550 2050
U 4C9E2AF4
F0 "Image Sensor" 60
F1 "sensor.sch" 60
F2 "+2.8_VDDIO" B L 3400 8750 60
F3 "+1.8_VDD" B L 3400 8900 60
F4 "+2.8_VAA" B L 3400 9200 60
F5 "+2.8_VAAPIX" B L 3400 9050 60
F6 "+2.8_VDDPLL" B L 3400 8600 60
F7 "IS_TRIGGER" I R 4950 7400 60
F8 "IS_FLASH" O R 4950 7500 60
F9 "IS_SDA" B R 4950 7600 60
F10 "IS_SCL" B R 4950 7700 60
F11 "IS_I2C_ADDR" I R 4950 7800 60
F12 "IS_EXTCLK" I R 4950 7900 60
F13 "IS_RESET_N" I R 4950 8000 60
F14 "IS_OE_N" I R 4950 8100 60
F15 "IS_STANDBY" I R 4950 8200 60
F16 "IS_TEST" I R 4950 8300 60
F17 "IS_PIXEL" O R 4950 8400 60
F18 "IS_LINE" O R 4950 8500 60
F19 "IS_FRAME" O R 4950 8600 60
F20 "IS_DOUT[0..11]" O R 4950 9000 60
F2 "+2.8_VDDIO" B L 7550 5100 60
F3 "+1.8_VDD" B L 7550 5250 60
F4 "+2.8_VAA" B L 7550 5550 60
F5 "+2.8_VAAPIX" B L 7550 5400 60
F6 "+2.8_VDDPLL" B L 7550 4950 60
F7 "IS_TRIGGER" I R 9100 3750 60
F8 "IS_FLASH" O R 9100 3850 60
F9 "IS_SDA" B R 9100 3950 60
F10 "IS_SCL" B R 9100 4050 60
F11 "IS_I2C_ADDR" I R 9100 4150 60
F12 "IS_EXTCLK" I R 9100 4250 60
F13 "IS_RESET_N" I R 9100 4350 60
F14 "IS_OE_N" I R 9100 4450 60
F15 "IS_STANDBY" I R 9100 4550 60
F16 "IS_TEST" I R 9100 4650 60
F17 "IS_PIXEL" O R 9100 4750 60
F18 "IS_LINE" O R 9100 4850 60
F19 "IS_FRAME" O R 9100 4950 60
F20 "IS_DOUT[0..11]" O R 9100 5350 60
$EndSheet
$Sheet
S 2050 8300 1100 1000
S 6200 4650 1100 1000
U 4C9E2B0F
F0 "Snesor PSU" 60
F1 "sensor_psu.sch" 60
F2 "+2.8_VDDPLL" B R 3150 8600 60
F3 "+2.8_VDDIO" B R 3150 8750 60
F4 "+1.8_VDD" B R 3150 8900 60
F5 "+2.8_VAAPIX" B R 3150 9050 60
F6 "+2.8_VAA" B R 3150 9200 60
F2 "+2.8_VDDPLL" B R 7300 4950 60
F3 "+2.8_VDDIO" B R 7300 5100 60
F4 "+1.8_VDD" B R 7300 5250 60
F5 "+2.8_VAAPIX" B R 7300 5400 60
F6 "+2.8_VAA" B R 7300 5550 60
$EndSheet
$Sheet
S 5950 5150 3350 4350
S 10100 1500 3350 6650
U 4C7BC2B2
F0 "FPGA, Port0, Port2, PROG IF" 60
F1 "FPGA_0_2_PROG.sch" 60
F2 "S6_TCK" I L 5950 6450 60
F3 "S6_TDI" I L 5950 6550 60
F4 "S6_TDO" O L 5950 6650 60
F5 "S6_TMS" I L 5950 6750 60
F6 "PROG_MISO[0..3]" B R 9300 9150 60
F7 "PROG_CCLK" O R 9300 9050 60
F8 "PROG_CSO" O R 9300 8950 60
F9 "NF_D[0..7]" B R 9300 8700 60
F10 "ETH_COL" B R 9300 5850 60
F11 "ETH_CRS" B R 9300 5750 60
F12 "NF_WE_N" O R 9300 8400 60
F13 "NF_ALE" O R 9300 8200 60
F14 "NF_CLE" O R 9300 8300 60
F15 "NF_CS1_N" O R 9300 8100 60
F16 "NF_RE_N" O R 9300 8500 60
F17 "NF_RNB" B R 9300 8600 60
F18 "SD_CLK" B R 9300 7550 60
F19 "SD_CMD" B R 9300 7650 60
F20 "SD_DAT[0..3]" B R 9300 7750 60
F21 "ETH_CLK" B R 9300 6950 60
F22 "ETH_RXC" B R 9300 5550 60
F23 "ETH_TXC" B R 9300 6550 60
F24 "ETH_TXD[0..3]" O R 9300 6650 60
F25 "ETH_TXEN" B R 9300 6750 60
F26 "ETH_TXER" B R 9300 6850 60
F27 "ETH_RXER" B R 9300 6450 60
F28 "ETH_RXDV" B R 9300 6350 60
F29 "ETH_RXD[0..3]" I R 9300 6250 60
F30 "ETH_RESET_N" B R 9300 5650 60
F31 "ETH_MDIO" B R 9300 5950 60
F32 "ETH_MDC" B R 9300 6050 60
F33 "ETH_INT" B R 9300 5400 60
F34 "IS_DOUT[0..11]" I L 5950 9000 60
F35 "IS_TEST" O L 5950 8300 60
F36 "IS_STANDBY" O L 5950 8200 60
F37 "IS_OE_N" O L 5950 8100 60
F38 "IS_RESET_N" O L 5950 8000 60
F39 "IS_EXTCLK" O L 5950 7900 60
F40 "IS_I2C_ADDR" O L 5950 7800 60
F41 "IS_SCL" B L 5950 7700 60
F42 "IS_SDA" B L 5950 7600 60
F43 "IS_FRAME" I L 5950 8600 60
F44 "IS_LINE" I L 5950 8500 60
F45 "IS_PIXEL" I L 5950 8400 60
F46 "IS_FLASH" I L 5950 7500 60
F47 "IS_TRIGGER" O L 5950 7400 60
F2 "S6_TCK" I L 10100 6750 60
F3 "S6_TDI" I L 10100 6850 60
F4 "S6_TDO" O L 10100 6950 60
F5 "S6_TMS" I L 10100 7050 60
F6 "PROG_MISO[0..3]" B R 13450 5500 60
F7 "PROG_CCLK" O R 13450 5400 60
F8 "PROG_CSO" O R 13450 5300 60
F9 "NF_D[0..7]" B R 13450 5050 60
F10 "ETH_COL" B R 13450 2200 60
F11 "ETH_CRS" B R 13450 2100 60
F12 "NF_WE_N" O R 13450 4750 60
F13 "NF_ALE" O R 13450 4550 60
F14 "NF_CLE" O R 13450 4650 60
F15 "NF_CS1_N" O R 13450 4450 60
F16 "NF_RE_N" O R 13450 4850 60
F17 "NF_RNB" B R 13450 4950 60
F18 "SD_CLK" B R 13450 3900 60
F19 "SD_CMD" B R 13450 4000 60
F20 "SD_DAT[0..3]" B R 13450 4100 60
F21 "ETH_CLK" B R 13450 3300 60
F22 "ETH_RXC" B R 13450 1900 60
F23 "ETH_TXC" B R 13450 2900 60
F24 "ETH_TXD[0..3]" O R 13450 3000 60
F25 "ETH_TXEN" B R 13450 3100 60
F26 "ETH_TXER" B R 13450 3200 60
F27 "ETH_RXER" B R 13450 2800 60
F28 "ETH_RXDV" B R 13450 2700 60
F29 "ETH_RXD[0..3]" I R 13450 2600 60
F30 "ETH_RESET_N" B R 13450 2000 60
F31 "ETH_MDIO" B R 13450 2300 60
F32 "ETH_MDC" B R 13450 2400 60
F33 "ETH_INT" B R 13450 1750 60
F34 "IS_DOUT[0..11]" I L 10100 5350 60
F35 "IS_TEST" O L 10100 4650 60
F36 "IS_STANDBY" O L 10100 4550 60
F37 "IS_OE_N" O L 10100 4450 60
F38 "IS_RESET_N" O L 10100 4350 60
F39 "IS_EXTCLK" O L 10100 4250 60
F40 "IS_I2C_ADDR" O L 10100 4150 60
F41 "IS_SCL" B L 10100 4050 60
F42 "IS_SDA" B L 10100 3950 60
F43 "IS_FRAME" I L 10100 4950 60
F44 "IS_LINE" I L 10100 4850 60
F45 "IS_PIXEL" I L 10100 4750 60
F46 "IS_FLASH" I L 10100 3850 60
F47 "IS_TRIGGER" O L 10100 3750 60
F48 "FPGA_VCCO2_IO_AA18" B R 13450 5950 60
F49 "FPGA_VCCO2_IO_AB21" B R 13450 6050 60
F50 "FPGA_VCCO2_IO_W18" B R 13450 6150 60
F51 "FPGA_VCCO2_IO_AB16" B R 13450 6250 60
F52 "FPGA_VCCO2_IO_AB15" B R 13450 6350 60
F53 "FPGA_VCCO2_IO_V7" B R 13450 6450 60
F54 "FPGA_VCCO2_IO_W6" B R 13450 6550 60
F55 "FPGA_VCCO2_IO_W4" B R 13450 6650 60
F56 "FPGA_VCCO2_IO_Y10" B R 13450 6750 60
F57 "FPGA_VCCO2_IO_Y9" B R 13450 6850 60
F58 "FPGA_VCCO2_IO_Y15" B R 13450 6950 60
F59 "FPGA_VCCO2_IO_Y16" B R 13450 7050 60
F60 "FPGA_VCCO2_IO_W10" B R 13450 7150 60
F61 "FPGA_VCCO2_IO_W11" B R 13450 7250 60
F62 "FPGA_VCCO2_IO_Y12" B R 13450 7350 60
F63 "FPGA_VCCO2_IO_AB14" B R 13450 7450 60
F64 "FPGA_VCCO2_IO_AB13" B R 13450 7550 60
F65 "FPGA_VCCO2_IO_Y11" B R 13450 7650 60
F66 "FPGA_VCCO2_IO_W8" B R 13450 7750 60
F67 "FPGA_VCCO2_IO_U9" B R 13450 7850 60
$EndSheet
$Sheet
S 5950 700 3300 4200
S 10100 9250 3300 4350
U 4C7BC2A2
F0 "FPGA Port 1, Port 3 DDR, USB" 60
F1 "FPGA_1_3.sch" 60
F2 "USBD_VP" B R 9250 1850 60
F3 "USBD_SPD" B R 9250 1550 60
F4 "USBD_OE_N" B R 9250 1650 60
F5 "USBD_RCV" B R 9250 1750 60
F6 "USBD_VM" B R 9250 1950 60
F7 "M0_CKE" O L 5950 4100 60
F8 "M0_UDM" O L 5950 3850 60
F9 "M0_UDQS" O L 5950 3550 60
F10 "M0_BA[0..1]" O L 5950 3400 60
F11 "M0_CAS#" O L 5950 4450 60
F12 "M0_RAS#" O L 5950 4550 60
F13 "M0_WE#" O L 5950 4700 60
F14 "M0_LDM" O L 5950 3950 60
F15 "M0_LDQS" O L 5950 3650 60
F16 "M1_UDQS" O L 5950 1500 60
F17 "M1_UDM" O L 5950 1800 60
F18 "M1_LDQS" O L 5950 1600 60
F19 "M1_LDM" O L 5950 1900 60
F20 "M1_WE#" O L 5950 2650 60
F21 "M1_CKE" O L 5950 2050 60
F22 "M1_RAS#" O L 5950 2500 60
F23 "M1_CAS#" O L 5950 2400 60
F24 "M1_BA[0..1]" O L 5950 1300 60
F25 "M1_CS#" O L 5950 950 60
F26 "USBA_VM" B R 9250 1350 60
F27 "USBA_VP" B R 9250 1250 60
F28 "USBA_RCV" B R 9250 1150 60
F29 "USBA_OE_N" B R 9250 1050 60
F30 "USBA_SPD" B R 9250 950 60
F31 "M1_DQ[0..15]" B L 5950 1100 60
F32 "M0_CS#" O L 5950 3050 60
F33 "M0_DQ[0..15]" B L 5950 3200 60
F34 "M0_A[0..12]" O L 5950 3300 60
F35 "M1_A[0..12]" O L 5950 1200 60
F36 "M1_CLK" O L 5950 2150 60
F37 "M1_CLK#" O L 5950 2250 60
F38 "M0_CLK" O L 5950 4200 60
F39 "M0_CLK#" O L 5950 4300 60
F2 "USBD_VP" B R 13400 12950 60
F3 "USBD_SPD" B R 13400 12650 60
F4 "USBD_OE_N" B R 13400 12750 60
F5 "USBD_RCV" B R 13400 12850 60
F6 "USBD_VM" B R 13400 13050 60
F7 "M0_CKE" O L 10100 12650 60
F8 "M0_UDM" O L 10100 12400 60
F9 "M0_UDQS" O L 10100 12100 60
F10 "M0_BA[0..1]" O L 10100 11950 60
F11 "M0_CAS#" O L 10100 13000 60
F12 "M0_RAS#" O L 10100 13100 60
F13 "M0_WE#" O L 10100 13250 60
F14 "M0_LDM" O L 10100 12500 60
F15 "M0_LDQS" O L 10100 12200 60
F16 "M1_UDQS" O L 10100 10050 60
F17 "M1_UDM" O L 10100 10350 60
F18 "M1_LDQS" O L 10100 10150 60
F19 "M1_LDM" O L 10100 10450 60
F20 "M1_WE#" O L 10100 11200 60
F21 "M1_CKE" O L 10100 10600 60
F22 "M1_RAS#" O L 10100 11050 60
F23 "M1_CAS#" O L 10100 10950 60
F24 "M1_BA[0..1]" O L 10100 9850 60
F25 "M1_CS#" O L 10100 9500 60
F26 "USBA_VM" B R 13400 12450 60
F27 "USBA_VP" B R 13400 12350 60
F28 "USBA_RCV" B R 13400 12250 60
F29 "USBA_OE_N" B R 13400 12150 60
F30 "USBA_SPD" B R 13400 12050 60
F31 "M1_DQ[0..15]" B L 10100 9650 60
F32 "M0_CS#" O L 10100 11600 60
F33 "M0_DQ[0..15]" B L 10100 11750 60
F34 "M0_A[0..12]" O L 10100 11850 60
F35 "M1_A[0..12]" O L 10100 9750 60
F36 "M1_CLK" O L 10100 10700 60
F37 "M1_CLK#" O L 10100 10800 60
F38 "M0_CLK" O L 10100 12750 60
F39 "M0_CLK#" O L 10100 12850 60
F40 "FPGA_2.5V_IO_M17" B R 13400 9900 60
F41 "FPGA_2.5V_IO_N16" B R 13400 10000 60
F42 "FPGA_2.5V_IO_P19" B R 13400 10100 60
F43 "FPGA_2.5V_IO_P17" B R 13400 10200 60
F44 "FPGA_2.5V_IO_P18" B R 13400 10300 60
F45 "FPGA_2.5V_IO_U19" B R 13400 10400 60
F46 "FPGA_2.5V_IO_T20" B R 13400 10500 60
F47 "FPGA_2.5V_IO_V20" B R 13400 10600 60
F48 "FPGA_2.5V_IO_W20" B R 13400 10700 60
F49 "FPGA_2.5V_IO_W22" B R 13400 10800 60
F50 "FPGA_2.5V_IO_V3" B R 13400 10900 60
F51 "FPGA_2.5V_IO_U4" B R 13400 11000 60
F52 "FPGA_2.5V_IO_T3" B R 13400 11100 60
F53 "FPGA_2.5V_IO_T4" B R 13400 11200 60
F54 "FPGA_2.5V_IO_P7" B R 13400 11300 60
F55 "FPGA_2.5V_IO_P8" B R 13400 11400 60
F56 "FPGA_2.5V_IO_W1" B R 13400 11500 60
F57 "FPGA_2.5V_IO_W3" B R 13400 11600 60
F58 "FPGA_2.5V_IO_Y1" B R 13400 11700 60
F59 "FPGA_2.5V_IO_Y2" B R 13400 11800 60
$EndSheet
$Sheet
S 3750 6400 1200 700
S 7900 6700 1200 700
U 4C716A4D
F0 "DBG_PRG" 60
F1 "DBG_PRG.sch" 60
F2 "FPGA_TDO" B R 4950 6650 60
F3 "FPGA_TDI" B R 4950 6550 60
F4 "FPGA_TMS" B R 4950 6750 60
F5 "FPGA_TCK" B R 4950 6450 60
F2 "FPGA_TDO" B R 9100 6950 60
F3 "FPGA_TDI" B R 9100 6850 60
F4 "FPGA_TMS" B R 9100 7050 60
F5 "FPGA_TCK" B R 9100 6750 60
$EndSheet
$Sheet
S 3750 5400 1200 750
S 7900 1750 1200 750
U 4C69ED5F
F0 "PSU" 60
F1 "PSU.sch" 60
$EndSheet
$Sheet
S 10650 7350 1050 1950
S 14800 3700 1050 1950
U 4C4227FE
F0 "Non volatile memories" 60
F1 "NV_MEMORIES.sch" 60
F2 "SD_CMD" I L 10650 7650 60
F3 "SD_CLK" I L 10650 7550 60
F4 "SD_DAT[0..3]" B L 10650 7750 60
F5 "NF_D[0..7]" B L 10650 8700 60
F6 "NF_ALE" B L 10650 8200 60
F7 "NF_CLE" B L 10650 8300 60
F8 "NF_WE_N" B L 10650 8400 60
F9 "NF_CS1_N" B L 10650 8100 60
F10 "NF_RE_N" B L 10650 8500 60
F11 "NF_RNB" B L 10650 8600 60
F12 "SPI_CLK" I L 10650 9050 60
F13 "SPI_FLASH_CS#" I L 10650 8950 60
F14 "SPI_DQ[0..3]" B L 10650 9150 60
F2 "SD_CMD" I L 14800 4000 60
F3 "SD_CLK" I L 14800 3900 60
F4 "SD_DAT[0..3]" B L 14800 4100 60
F5 "NF_D[0..7]" B L 14800 5050 60
F6 "NF_ALE" B L 14800 4550 60
F7 "NF_CLE" B L 14800 4650 60
F8 "NF_WE_N" B L 14800 4750 60
F9 "NF_CS1_N" B L 14800 4450 60
F10 "NF_RE_N" B L 14800 4850 60
F11 "NF_RNB" B L 14800 4950 60
F12 "SPI_CLK" I L 14800 5400 60
F13 "SPI_FLASH_CS#" I L 14800 5300 60
F14 "SPI_DQ[0..3]" B L 14800 5500 60
$EndSheet
$Sheet
S 10600 900 1100 1150
S 14750 12000 1100 1150
U 4C5F1EDC
F0 "USB" 60
F1 "USB.sch" 60
F2 "USBA_SPD" B L 10600 950 60
F3 "USBA_OE_N" B L 10600 1050 60
F4 "USBA_RCV" B L 10600 1150 60
F5 "USBA_VP" B L 10600 1250 60
F6 "USBA_VM" B L 10600 1350 60
F7 "USBD_SPD" B L 10600 1550 60
F8 "USBD_OE_N" B L 10600 1650 60
F9 "USBD_RCV" B L 10600 1750 60
F10 "USBD_VP" B L 10600 1850 60
F11 "USBD_VM" B L 10600 1950 60
F2 "USBA_SPD" B L 14750 12050 60
F3 "USBA_OE_N" B L 14750 12150 60
F4 "USBA_RCV" B L 14750 12250 60
F5 "USBA_VP" B L 14750 12350 60
F6 "USBA_VM" B L 14750 12450 60
F7 "USBD_SPD" B L 14750 12650 60
F8 "USBD_OE_N" B L 14750 12750 60
F9 "USBD_RCV" B L 14750 12850 60
F10 "USBD_VP" B L 14750 12950 60
F11 "USBD_VM" B L 14750 13050 60
$EndSheet
Text Notes 12850 10750 0 60 ~ 0
Text Notes 19700 15650 0 60 ~ 0
Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
$Sheet
S 10600 5300 1300 1800
S 14750 1650 1300 1800
U 4C4320F3
F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60
F2 "ETH_RXC" O L 10600 5550 60
F3 "ETH_RST_N" I L 10600 5650 60
F4 "ETH_CRS" O L 10600 5750 60
F5 "ETH_COL" O L 10600 5850 60
F6 "ETH_MDIO" B L 10600 5950 60
F7 "ETH_MDC" I L 10600 6050 60
F8 "ETH_RXD[0..3]" O L 10600 6250 60
F9 "ETH_RXDV" O L 10600 6350 60
F10 "ETH_RXER" O L 10600 6450 60
F11 "ETH_TXC" B L 10600 6550 60
F12 "ETH_TXD[0..3]" I L 10600 6650 60
F13 "ETH_TXEN" I L 10600 6750 60
F14 "ETH_TXER" I L 10600 6850 60
F15 "ETH_CLK" I L 10600 6950 60
F16 "ETH_INT" O L 10600 5400 60
F2 "ETH_RXC" O L 14750 1900 60
F3 "ETH_RST_N" I L 14750 2000 60
F4 "ETH_CRS" O L 14750 2100 60
F5 "ETH_COL" O L 14750 2200 60
F6 "ETH_MDIO" B L 14750 2300 60
F7 "ETH_MDC" I L 14750 2400 60
F8 "ETH_RXD[0..3]" O L 14750 2600 60
F9 "ETH_RXDV" O L 14750 2700 60
F10 "ETH_RXER" O L 14750 2800 60
F11 "ETH_TXC" B L 14750 2900 60
F12 "ETH_TXD[0..3]" I L 14750 3000 60
F13 "ETH_TXEN" I L 14750 3100 60
F14 "ETH_TXER" I L 14750 3200 60
F15 "ETH_CLK" I L 14750 3300 60
F16 "ETH_INT" O L 14750 1750 60
$EndSheet
$Sheet
S 3600 850 1100 4000
S 7750 9400 1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M0_BA[0..1]" I R 4700 3400 60
F3 "M1_BA[0..1]" I R 4700 1300 60
F4 "M0_WE#" I R 4700 4700 60
F5 "M0_RAS#" I R 4700 4550 60
F6 "M1_RAS#" I R 4700 2500 60
F7 "M1_WE#" I R 4700 2650 60
F8 "M0_CAS#" I R 4700 4450 60
F9 "M0_CKE" I R 4700 4100 60
F10 "M0_CLK" I R 4700 4200 60
F11 "M0_CLK#" I R 4700 4300 60
F12 "M0_CS#" I R 4700 3050 60
F13 "M1_CLK#" I R 4700 2250 60
F14 "M1_CLK" I R 4700 2150 60
F15 "M1_CKE" I R 4700 2050 60
F16 "M1_CAS#" I R 4700 2400 60
F17 "M0_DQ[0..15]" B R 4700 3200 60
F18 "M0_UDM" I R 4700 3850 60
F19 "M0_LDQS" I R 4700 3650 60
F20 "M0_A[0..12]" I R 4700 3300 60
F21 "M0_LDM" I R 4700 3950 60
F22 "M0_UDQS" I R 4700 3550 60
F23 "M1_UDQS" I R 4700 1500 60
F24 "M1_LDM" I R 4700 1900 60
F25 "M1_LDQS" I R 4700 1600 60
F26 "M1_UDM" I R 4700 1800 60
F27 "M1_CS#" I R 4700 950 60
F28 "M1_A[0..12]" I R 4700 1200 60
F29 "M1_DQ[0..15]" B R 4700 1100 60
F2 "M0_BA[0..1]" I R 8850 11950 60
F3 "M1_BA[0..1]" I R 8850 9850 60
F4 "M0_WE#" I R 8850 13250 60
F5 "M0_RAS#" I R 8850 13100 60
F6 "M1_RAS#" I R 8850 11050 60
F7 "M1_WE#" I R 8850 11200 60
F8 "M0_CAS#" I R 8850 13000 60
F9 "M0_CKE" I R 8850 12650 60
F10 "M0_CLK" I R 8850 12750 60
F11 "M0_CLK#" I R 8850 12850 60
F12 "M0_CS#" I R 8850 11600 60
F13 "M1_CLK#" I R 8850 10800 60
F14 "M1_CLK" I R 8850 10700 60
F15 "M1_CKE" I R 8850 10600 60
F16 "M1_CAS#" I R 8850 10950 60
F17 "M0_DQ[0..15]" B R 8850 11750 60
F18 "M0_UDM" I R 8850 12400 60
F19 "M0_LDQS" I R 8850 12200 60
F20 "M0_A[0..12]" I R 8850 11850 60
F21 "M0_LDM" I R 8850 12500 60
F22 "M0_UDQS" I R 8850 12100 60
F23 "M1_UDQS" I R 8850 10050 60
F24 "M1_LDM" I R 8850 10450 60
F25 "M1_LDQS" I R 8850 10150 60
F26 "M1_UDM" I R 8850 10350 60
F27 "M1_CS#" I R 8850 9500 60
F28 "M1_A[0..12]" I R 8850 9750 60
F29 "M1_DQ[0..15]" B R 8850 9650 60
$EndSheet
$EndSCHEMATC