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Code

DDR de-coupling caps. added

Browse Source
This commit is contained in:
Andres Calderon 2010-08-10 17:38:37 -05:00
parent a8fcbf091c
commit cac88e3756
12 changed files with 3557 additions and 1957 deletions
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22
kicad/library/pasives-connectors.lib Normal file
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@ -0,0 +1,22 @@
EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 04:58:24 PM COT
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 50 100 50 H V L CNN
F1 "Cap" 50 -100 50 H V L CNN
$FPLIST
SM*
C?
C1-1
$ENDFPLIST
DRAW
S -50 -25 -50 -25 0 1 0 N
S -50 -25 50 -25 0 1 20 N
S -50 25 50 25 0 1 20 N
X ~ 1 0 100 65 D 40 40 1 1 P
X ~ 2 0 -100 65 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
#End Library

1057
kicad/xue-rnc/DRAM.sch
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File diff suppressed because it is too large Load Diff

251
kicad/xue-rnc/FPGA.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
LIBS:power LIBS:power
LIBS:v0402mhs03 LIBS:v0402mhs03
LIBS:usb-48204-0001 LIBS:usb-48204-0001
@ -40,6 +40,7 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
LIBS:pasives-connectors
LIBS:xue-rnc-cache LIBS:xue-rnc-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
@ -54,21 +55,16 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Text HLabel 12400 5450 0 60 Output ~ 0 Wire Bus Line
M1_CS# 13300 4350 13400 4350
$Comp Wire Bus Line
L GND #PWR? 13400 4350 13400 4450
U 1 1 4C60C24F
P 12550 5700
F 0 "#PWR?" H 12550 5700 30 0001 C CNN
F 1 "GND" H 12550 5630 30 0001 C CNN
1 12550 5700
-1 0 0 -1
$EndComp
Wire Wire Line Wire Wire Line
12550 5450 12550 5700 13500 4550 13900 4550
Wire Wire Line Wire Wire Line
12400 5450 12550 5450 12550 5700 12550 5450
Wire Wire Line
12550 5450 12400 5450
Wire Wire Line Wire Wire Line
1450 5700 1600 5700 1450 5700 1600 5700
Wire Wire Line Wire Wire Line
@ -104,39 +100,39 @@ Wire Bus Line
Wire Wire Line Wire Wire Line
18300 4950 18750 4950 18300 4950 18750 4950
Wire Wire Line Wire Wire Line
12500 4700 12050 4700 12150 4700 11700 4700
Wire Wire Line Wire Wire Line
12500 4900 12050 4900 12150 4900 11700 4900
Wire Wire Line Wire Wire Line
12500 5000 12050 5000 12150 5000 11700 5000
Wire Wire Line Wire Wire Line
12500 4800 12050 4800 12150 4800 11700 4800
Wire Wire Line Wire Wire Line
12500 4400 12050 4400 12150 4400 11700 4400
Wire Wire Line Wire Wire Line
12500 4600 12050 4600 12150 4600 11700 4600
Wire Wire Line Wire Wire Line
12500 4500 12050 4500 12150 4500 11700 4500
Wire Wire Line Wire Wire Line
12500 4300 12050 4300 12150 4300 11700 4300
Wire Wire Line Wire Wire Line
12500 3700 12050 3700 12150 3700 11700 3700
Wire Wire Line Wire Wire Line
12500 3500 12050 3500 12150 3500 11700 3500
Wire Wire Line Wire Wire Line
12500 3600 12050 3600 12150 3600 11700 3600
Wire Wire Line Wire Wire Line
12500 3800 12050 3800 12150 3800 11700 3800
Wire Wire Line Wire Wire Line
12500 4000 12050 4000 12150 4000 11700 4000
Wire Wire Line Wire Wire Line
12500 4200 12050 4200 12150 4200 11700 4200
Wire Wire Line Wire Wire Line
12500 3900 12050 3900 12150 3900 11700 3900
Wire Wire Line Wire Wire Line
12500 4100 12050 4100 12150 4100 11700 4100
Wire Bus Line Wire Bus Line
12500 3250 12600 3250 12150 3250 12250 3250
Wire Wire Line Wire Wire Line
13500 3450 13900 3450 13500 3450 13900 3450
Wire Wire Line Wire Wire Line
@ -166,31 +162,31 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
3200 3500 2750 3500 3200 3500 2750 3500
Wire Wire Line Wire Wire Line
12700 2250 12300 2250 12200 2250 11800 2250
Wire Wire Line Wire Wire Line
12700 2350 12300 2350 12200 2350 11800 2350
Wire Wire Line Wire Wire Line
12700 2550 12300 2550 12200 2550 11800 2550
Wire Wire Line Wire Wire Line
12700 2750 12300 2750 12200 2750 11800 2750
Wire Wire Line Wire Wire Line
12700 1650 12300 1650 12200 1650 11800 1650
Wire Wire Line Wire Wire Line
12700 1750 12300 1750 12200 1750 11800 1750
Wire Wire Line Wire Wire Line
12700 2050 12300 2050 12200 2050 11800 2050
Wire Wire Line Wire Wire Line
12700 1950 12300 1950 12200 1950 11800 1950
Wire Wire Line Wire Wire Line
12700 2450 12300 2450 12200 2450 11800 2450
Wire Wire Line Wire Wire Line
12700 1850 12300 1850 12200 1850 11800 1850
Wire Wire Line Wire Wire Line
12700 2150 12300 2150 12200 2150 11800 2150
Wire Wire Line Wire Wire Line
12700 2650 12300 2650 12200 2650 11800 2650
Wire Wire Line Wire Wire Line
12700 2850 12300 2850 12200 2850 11800 2850
Wire Wire Line Wire Wire Line
13900 4950 13550 4950 13900 4950 13550 4950
Connection ~ 5750 6900 Connection ~ 5750 6900
@ -625,9 +621,9 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
13900 4850 13550 4850 13900 4850 13550 4850
Wire Bus Line Wire Bus Line
12200 2750 12200 1500 11700 2750 11700 1500
Wire Bus Line Wire Bus Line
12200 1500 11800 1500 11700 1500 11300 1500
Wire Bus Line Wire Bus Line
1050 1300 1450 1300 1050 1300 1450 1300
Wire Bus Line Wire Bus Line
@ -765,7 +761,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
18300 5250 18750 5250 18300 5250 18750 5250
Wire Bus Line Wire Bus Line
12600 3250 12600 4900 12250 3250 12250 4900
Wire Wire Line Wire Wire Line
18750 4450 18300 4450 18750 4450 18300 4450
Wire Wire Line Wire Wire Line
@ -824,11 +820,44 @@ Wire Wire Line
14150 10750 14200 10750 14150 10750 14200 10750
Wire Wire Line Wire Wire Line
1600 5700 1600 5950 1600 5700 1600 5950
Wire Bus Line
8050 4200 7900 4200
Wire Bus Line
7900 4200 7900 4300
Wire Wire Line
13900 4450 13500 4450
Entry Wire Line
13400 4450 13500 4550
Entry Wire Line
13400 4350 13500 4450
Text Label 13850 4550 2 60 ~ 0
M1_BA1
Text Label 13850 4450 2 60 ~ 0
M1_BA0
Text HLabel 13300 4350 0 60 Output ~ 0
M1_BA[0..1]
Entry Wire Line
7800 4400 7900 4300
Entry Wire Line
7800 4300 7900 4200
Text HLabel 8050 4200 2 60 Output ~ 0
M0_BA[0..1]
Text HLabel 12400 5450 0 60 Output ~ 0
M1_CS#
$Comp $Comp
L GND #PWR? L GND #PWR01
U 1 1 4C60C24F
P 12550 5700
F 0 "#PWR01" H 12550 5700 30 0001 C CNN
F 1 "GND" H 12550 5630 30 0001 C CNN
1 12550 5700
-1 0 0 -1
$EndComp
$Comp
L GND #PWR02
U 1 1 4C60C21D U 1 1 4C60C21D
P 1600 5950 P 1600 5950
F 0 "#PWR?" H 1600 5950 30 0001 C CNN F 0 "#PWR02" H 1600 5950 30 0001 C CNN
F 1 "GND" H 1600 5880 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN
1 1600 5950 1 1600 5950
-1 0 0 -1 -1 0 0 -1
@ -932,70 +961,70 @@ M1_DQ11
Text Label 18350 4450 0 60 ~ 0 Text Label 18350 4450 0 60 ~ 0
M1_DQ10 M1_DQ10
Entry Wire Line Entry Wire Line
12500 5000 12600 4900 12150 5000 12250 4900
Entry Wire Line Entry Wire Line
12500 4900 12600 4800 12150 4900 12250 4800
Entry Wire Line Entry Wire Line
12500 4800 12600 4700 12150 4800 12250 4700
Entry Wire Line Entry Wire Line
12500 4700 12600 4600 12150 4700 12250 4600
Entry Wire Line Entry Wire Line
12500 4600 12600 4500 12150 4600 12250 4500
Entry Wire Line Entry Wire Line
12500 4500 12600 4400 12150 4500 12250 4400
Entry Wire Line Entry Wire Line
12500 4400 12600 4300 12150 4400 12250 4300
Entry Wire Line Entry Wire Line
12500 4300 12600 4200 12150 4300 12250 4200
Entry Wire Line Entry Wire Line
12500 4200 12600 4100 12150 4200 12250 4100
Entry Wire Line Entry Wire Line
12500 4100 12600 4000 12150 4100 12250 4000
Entry Wire Line Entry Wire Line
12500 4000 12600 3900 12150 4000 12250 3900
Entry Wire Line Entry Wire Line
12500 3900 12600 3800 12150 3900 12250 3800
Entry Wire Line Entry Wire Line
12500 3800 12600 3700 12150 3800 12250 3700
Entry Wire Line Entry Wire Line
12500 3700 12600 3600 12150 3700 12250 3600
Entry Wire Line Entry Wire Line
12500 3600 12600 3500 12150 3600 12250 3500
Entry Wire Line Entry Wire Line
12500 3500 12600 3400 12150 3500 12250 3400
Text Label 12050 4100 0 60 ~ 0 Text Label 11700 4100 0 60 ~ 0
M1_DQ6 M1_DQ6
Text Label 12050 4200 0 60 ~ 0 Text Label 11700 4200 0 60 ~ 0
M1_DQ7 M1_DQ7
Text Label 12050 4000 0 60 ~ 0 Text Label 11700 4000 0 60 ~ 0
M1_DQ5 M1_DQ5
Text Label 12050 3900 0 60 ~ 0 Text Label 11700 3900 0 60 ~ 0
M1_DQ4 M1_DQ4
Text Label 12050 3700 0 60 ~ 0 Text Label 11700 3700 0 60 ~ 0
M1_DQ2 M1_DQ2
Text Label 12050 3800 0 60 ~ 0 Text Label 11700 3800 0 60 ~ 0
M1_DQ3 M1_DQ3
Text Label 12050 3600 0 60 ~ 0 Text Label 11700 3600 0 60 ~ 0
M1_DQ1 M1_DQ1
Text Label 12050 3500 0 60 ~ 0 Text Label 11700 3500 0 60 ~ 0
M1_DQ0 M1_DQ0
Text Label 12050 4500 0 60 ~ 0 Text Label 11700 4500 0 60 ~ 0
M1_DQ10 M1_DQ10
Text Label 12050 4600 0 60 ~ 0 Text Label 11700 4600 0 60 ~ 0
M1_DQ11 M1_DQ11
Text Label 12050 4400 0 60 ~ 0 Text Label 11700 4400 0 60 ~ 0
M1_DQ9 M1_DQ9
Text Label 12050 4300 0 60 ~ 0 Text Label 11700 4300 0 60 ~ 0
M1_DQ8 M1_DQ8
Text Label 12050 4700 0 60 ~ 0 Text Label 11700 4700 0 60 ~ 0
M1_DQ12 M1_DQ12
Text Label 12050 4800 0 60 ~ 0 Text Label 11700 4800 0 60 ~ 0
M1_DQ13 M1_DQ13
Text Label 12050 5000 0 60 ~ 0 Text Label 11700 5000 0 60 ~ 0
M1_DQ15 M1_DQ15
Text Label 12050 4900 0 60 ~ 0 Text Label 11700 4900 0 60 ~ 0
M1_DQ14 M1_DQ14
Text HLabel 12500 3250 0 60 BiDi ~ 0 Text HLabel 12150 3250 0 60 BiDi ~ 0
M1_DQ[0..15] M1_DQ[0..15]
Text HLabel 1450 5700 0 60 Output ~ 0 Text HLabel 1450 5700 0 60 Output ~ 0
M0_CS# M0_CS#
@ -1198,31 +1227,31 @@ Entry Wire Line
Entry Wire Line Entry Wire Line
1450 1350 1550 1450 1450 1350 1550 1450
Entry Wire Line Entry Wire Line
12200 1550 12300 1650 11700 1550 11800 1650
Entry Wire Line Entry Wire Line
12200 1650 12300 1750 11700 1650 11800 1750
Entry Wire Line Entry Wire Line
12200 1750 12300 1850 11700 1750 11800 1850
Entry Wire Line Entry Wire Line
12200 1850 12300 1950 11700 1850 11800 1950
Entry Wire Line Entry Wire Line
12200 1950 12300 2050 11700 1950 11800 2050
Entry Wire Line Entry Wire Line
12200 2050 12300 2150 11700 2050 11800 2150
Entry Wire Line Entry Wire Line
12200 2150 12300 2250 11700 2150 11800 2250
Entry Wire Line Entry Wire Line
12200 2250 12300 2350 11700 2250 11800 2350
Entry Wire Line Entry Wire Line
12200 2350 12300 2450 11700 2350 11800 2450
Entry Wire Line Entry Wire Line
12200 2450 12300 2550 11700 2450 11800 2550
Entry Wire Line Entry Wire Line
12200 2550 12300 2650 11700 2550 11800 2650
Entry Wire Line Entry Wire Line
12200 2650 12300 2750 11700 2650 11800 2750
Entry Wire Line Entry Wire Line
12200 2750 12300 2850 11700 2750 11800 2850
Text HLabel 13550 5550 0 60 Output ~ 0 Text HLabel 13550 5550 0 60 Output ~ 0
M1_CAS# M1_CAS#
Text HLabel 13500 3450 0 60 Output ~ 0 Text HLabel 13500 3450 0 60 Output ~ 0
@ -1239,31 +1268,31 @@ Text HLabel 18750 5750 2 60 Output ~ 0
M1_LDM M1_LDM
Text HLabel 18750 4250 2 60 Output ~ 0 Text HLabel 18750 4250 2 60 Output ~ 0
M1_UDQS M1_UDQS
Text Label 12400 2350 0 60 ~ 0 Text Label 11900 2350 0 60 ~ 0
M1_A5 M1_A5
Text Label 12400 2250 0 60 ~ 0 Text Label 11900 2250 0 60 ~ 0
M1_A6 M1_A6
Text Label 12400 2550 0 60 ~ 0 Text Label 11900 2550 0 60 ~ 0
M1_A3 M1_A3
Text Label 12400 2750 0 60 ~ 0 Text Label 11900 2750 0 60 ~ 0
M1_A1 M1_A1
Text Label 12400 2850 0 60 ~ 0 Text Label 11900 2850 0 60 ~ 0
M1_A0 M1_A0
Text Label 12400 2650 0 60 ~ 0 Text Label 11900 2650 0 60 ~ 0
M1_A2 M1_A2
Text Label 12400 2150 0 60 ~ 0 Text Label 11900 2150 0 60 ~ 0
M1_A7 M1_A7
Text Label 12400 1850 0 60 ~ 0 Text Label 11900 1850 0 60 ~ 0
M1_A10 M1_A10
Text Label 12400 2450 0 60 ~ 0 Text Label 11900 2450 0 60 ~ 0
M1_A4 M1_A4
Text Label 12400 1950 0 60 ~ 0 Text Label 11900 1950 0 60 ~ 0
M1_A9 M1_A9
Text Label 12400 2050 0 60 ~ 0 Text Label 11900 2050 0 60 ~ 0
M1_A8 M1_A8
Text Label 12400 1750 0 60 ~ 0 Text Label 11900 1750 0 60 ~ 0
M1_A11 M1_A11
Text Label 12400 1650 0 60 ~ 0 Text Label 11900 1650 0 60 ~ 0
M1_A12 M1_A12
Text Label 13500 5350 0 60 ~ 0 Text Label 13500 5350 0 60 ~ 0
M1_A6 M1_A6
@ -1291,7 +1320,7 @@ Text Label 13500 4750 0 60 ~ 0
M1_A1 M1_A1
Text Label 13500 4650 0 60 ~ 0 Text Label 13500 4650 0 60 ~ 0
M1_A0 M1_A0
Text HLabel 11800 1500 0 60 Output ~ 0 Text HLabel 11300 1500 0 60 Output ~ 0
M1_A[0..12] M1_A[0..12]
Text HLabel 14150 8950 0 60 BiDi ~ 0 Text HLabel 14150 8950 0 60 BiDi ~ 0
ETH_INT ETH_INT
@ -1304,10 +1333,10 @@ M0_CLK
Text HLabel 7750 4700 2 60 Output ~ 0 Text HLabel 7750 4700 2 60 Output ~ 0
M0_CLK# M0_CLK#
$Comp $Comp
L GND #PWR01 L GND #PWR03
U 1 1 4C439B7E U 1 1 4C439B7E
P 13950 15700 P 13950 15700
F 0 "#PWR01" H 13950 15700 30 0001 C CNN F 0 "#PWR03" H 13950 15700 30 0001 C CNN
F 1 "GND" H 13950 15630 30 0001 C CNN F 1 "GND" H 13950 15630 30 0001 C CNN
1 13950 15700 1 13950 15700
-1 0 0 -1 -1 0 0 -1

11
kicad/xue-rnc/NV_MEMORIES.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
LIBS:power LIBS:power
LIBS:v0402mhs03 LIBS:v0402mhs03
LIBS:usb-48204-0001 LIBS:usb-48204-0001
@ -40,6 +40,7 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
LIBS:pasives-connectors
LIBS:xue-rnc-cache LIBS:xue-rnc-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
@ -172,19 +173,19 @@ Wire Wire Line
4400 5750 4400 5950 4400 5750 4400 5950
Connection ~ 4400 5850 Connection ~ 4400 5850
$Comp $Comp
L GND #PWR02 L GND #PWR04
U 1 1 4C438ADC U 1 1 4C438ADC
P 4400 5950 P 4400 5950
F 0 "#PWR02" H 4400 5950 30 0001 C CNN F 0 "#PWR04" H 4400 5950 30 0001 C CNN
F 1 "GND" H 4400 5880 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN
1 4400 5950 1 4400 5950
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR03 L GND #PWR05
U 1 1 4C438AD5 U 1 1 4C438AD5
P 3950 6300 P 3950 6300
F 0 "#PWR03" H 3950 6300 30 0001 C CNN F 0 "#PWR05" H 3950 6300 30 0001 C CNN
F 1 "GND" H 3950 6230 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN
1 3950 6300 1 3950 6300
1 0 0 -1 1 0 0 -1

3
kicad/xue-rnc/USB.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
LIBS:power LIBS:power
LIBS:v0402mhs03 LIBS:v0402mhs03
LIBS:usb-48204-0001 LIBS:usb-48204-0001
@ -40,6 +40,7 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
LIBS:pasives-connectors
LIBS:xue-rnc-cache LIBS:xue-rnc-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END

3
kicad/xue-rnc/eth_phy.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
LIBS:power LIBS:power
LIBS:v0402mhs03 LIBS:v0402mhs03
LIBS:usb-48204-0001 LIBS:usb-48204-0001
@ -40,6 +40,7 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
LIBS:pasives-connectors
LIBS:xue-rnc-cache LIBS:xue-rnc-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END

3
kicad/xue-rnc/xue-rnc-cache.dcm Normal file
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@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0 Date: Tue 10 Aug 2010 04:56:38 PM COT
#
#End Doc Library

34
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,17 @@
EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 10:11:04 PM COT EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 05:37:13 PM COT
#
# +2.5V
#
DEF +2.5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -50 20 H I C CNN
F1 "+2.5V" 0 100 30 H V C CNN
ALIAS +2,5V
DRAW
X +2.5V 1 0 0 0 U 20 30 0 0 W N
C 0 60 20 0 1 0 N
P 3 0 1 0 0 0 0 40 0 40 N
ENDDRAW
ENDDEF
# #
# C # C
# #
@ -18,6 +31,25 @@ X ~ 2 0 -200 170 U 40 40 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# Cap
#
DEF Cap C 0 10 N Y 1 F N
F0 "C" 50 100 50 H V L CNN
F1 "Cap" 50 -100 50 H V L CNN
$FPLIST
SM*
C?
C1-1
$ENDFPLIST
DRAW
S -50 -25 -50 -25 0 1 0 N
S -50 -25 50 -25 0 1 20 N
S -50 25 50 25 0 1 20 N
X ~ 1 0 100 65 D 40 40 1 1 P
X ~ 2 0 -100 65 U 40 40 1 1 P
ENDDRAW
ENDDEF
#
# GND # GND
# #
DEF ~GND #PWR 0 0 Y Y 1 F P DEF ~GND #PWR 0 0 Y Y 1 F P

2095
kicad/xue-rnc/xue-rnc.brd
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1718
kicad/xue-rnc/xue-rnc.net
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25
kicad/xue-rnc/xue-rnc.pro
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@ -1,8 +1,17 @@
update=Mon 09 Aug 2010 10:24:04 PM COT update=Tue 10 Aug 2010 05:37:22 PM COT
version=1 version=1
last_client=pcbnew last_client=pcbnew
[common] [common]
NetDir= NetDir=
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[eeschema] [eeschema]
version=1 version=1
LibDir= LibDir=
@ -33,9 +42,9 @@ offY_E=0
RptD_X=0 RptD_X=0
RptD_Y=100 RptD_Y=100
RptLab=1 RptLab=1
SimCmd=
UseNetN=0
LabSize=60 LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries] [eeschema/libraries]
LibName1=power LibName1=power
LibName2=../library/v0402mhs03 LibName2=../library/v0402mhs03
@ -78,15 +87,7 @@ LibName38=opto
LibName39=atmel LibName39=atmel
LibName40=contrib LibName40=contrib
LibName41=valves LibName41=valves
[general] LibName42=/stuff/devel/Qi/xue/kicad/library/pasives-connectors
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew] [pcbnew]
version=1 version=1
PadDrlX=320 PadDrlX=320

292
kicad/xue-rnc/xue-rnc.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT
LIBS:power LIBS:power
LIBS:v0402mhs03 LIBS:v0402mhs03
LIBS:usb-48204-0001 LIBS:usb-48204-0001
@ -40,6 +40,7 @@ LIBS:opto
LIBS:atmel LIBS:atmel
LIBS:contrib LIBS:contrib
LIBS:valves LIBS:valves
LIBS:pasives-connectors
LIBS:xue-rnc-cache LIBS:xue-rnc-cache
EELAYER 24 0 EELAYER 24 0
EELAYER END EELAYER END
@ -54,140 +55,104 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Wire Wire Line Wire Bus Line
10650 5400 9300 5400 10600 7200 9300 7200
Wire Wire Line Wire Bus Line
10650 5200 9300 5200
Wire Wire Line
10650 5000 9300 5000
Wire Wire Line
9300 7800 10600 7800
Wire Wire Line
9300 7600 10600 7600 9300 7600 10600 7600
Wire Wire Line Wire Wire Line
9300 7400 10600 7400 10650 5300 9300 5300
Wire Wire Line
9300 7200 10600 7200
Wire Wire Line
10600 6900 9300 6900
Wire Wire Line
9300 6700 10600 6700
Wire Wire Line
9300 6500 10600 6500
Wire Bus Line
4700 3150 5950 3150
Wire Wire Line
4700 2800 5950 2800
Wire Wire Line
4700 3750 5950 3750
Wire Wire Line
4700 3900 5950 3900
Wire Wire Line
4700 4250 5950 4250
Wire Wire Line
4700 5950 5950 5950
Wire Wire Line
4700 6550 5950 6550
Wire Bus Line
4700 5250 5950 5250
Wire Wire Line
4700 6300 5950 6300
Wire Wire Line
4700 5700 5950 5700
Wire Wire Line
4700 5400 5950 5400
Wire Bus Line
4700 3050 5950 3050
Wire Wire Line
5950 4100 4700 4100
Wire Wire Line
4700 6150 5950 6150
Wire Bus Line
5950 5100 5950 5050
Wire Bus Line
5950 5050 4700 5050
Wire Wire Line
4700 6050 5950 6050
Wire Wire Line
4700 4000 5950 4000
Wire Bus Line
4700 5150 5950 5150
Wire Wire Line
4700 5800 5950 5800
Wire Wire Line
4700 5500 5950 5500
Wire Wire Line
4700 6400 5950 6400
Wire Wire Line
4700 4900 5950 4900
Wire Wire Line
4700 4350 5950 4350
Wire Wire Line
4700 4500 5950 4500
Wire Wire Line
4700 3650 5950 3650
Wire Wire Line
4700 3450 5950 3450
Wire Wire Line
4700 3350 5950 3350
Wire Bus Line
4700 2950 5950 2950
Wire Wire Line
9300 6350 10600 6350
Wire Wire Line
9300 6600 10600 6600
Wire Wire Line
9300 6800 10600 6800
Wire Wire Line
9300 7000 10600 7000
Wire Wire Line
9300 7300 10600 7300
Wire Wire Line
9300 7500 10600 7500
Wire Wire Line
9300 7700 10600 7700
Wire Wire Line
9300 7900 10600 7900
Wire Wire Line Wire Wire Line
10650 5100 9300 5100 10650 5100 9300 5100
Wire Wire Line Wire Wire Line
10650 5300 9300 5300 9300 7900 10600 7900
Text HLabel 9300 5400 0 60 BiDi ~ 0 Wire Wire Line
USBA_VM 9300 7700 10600 7700
Text HLabel 9300 5300 0 60 BiDi ~ 0 Wire Wire Line
USBA_VP 9300 7500 10600 7500
Text HLabel 9300 5200 0 60 BiDi ~ 0 Wire Wire Line
USBA_RCV 9300 7300 10600 7300
Text HLabel 9300 5100 0 60 BiDi ~ 0 Wire Wire Line
USBA_OE_N 9300 7000 10600 7000
Text HLabel 9300 5000 0 60 BiDi ~ 0 Wire Wire Line
USBA_SPD 9300 6800 10600 6800
Text HLabel 9300 6900 0 60 BiDi ~ 0 Wire Wire Line
ETH_MDIO 9300 6600 10600 6600
Text HLabel 9300 7500 0 60 BiDi ~ 0 Wire Wire Line
ETH_TXC 9300 6350 10600 6350
Text HLabel 9300 7900 0 60 Input ~ 0 Wire Bus Line
ETH_CLK 4700 2950 5950 2950
Text HLabel 9300 7800 0 60 Input ~ 0 Wire Wire Line
ETH_TXER 4700 3350 5950 3350
Text HLabel 9300 7700 0 60 Input ~ 0 Wire Wire Line
ETH_TXEN 4700 3450 5950 3450
Text HLabel 9300 7600 0 60 Input ~ 0 Wire Wire Line
ETH_TXD[0..3] 4700 3650 5950 3650
Text HLabel 9300 7000 0 60 Input ~ 0 Wire Wire Line
ETH_MDC 4700 4500 5950 4500
Text HLabel 9300 6600 0 60 Input ~ 0 Wire Wire Line
ETH_RESET_N 4700 4350 5950 4350
Text HLabel 9300 7400 0 60 Output ~ 0 Wire Wire Line
ETH_RXER 4700 4900 5950 4900
Text HLabel 9300 7300 0 60 Output ~ 0 Wire Wire Line
ETH_RXDV 4700 6400 5950 6400
Text HLabel 9300 7200 0 60 Output ~ 0 Wire Wire Line
ETH_RXD[0..3] 4700 5500 5950 5500
Text HLabel 9300 6800 0 60 Output ~ 0 Wire Wire Line
ETH_COL 4700 5800 5950 5800
Text HLabel 9300 6700 0 60 Output ~ 0 Wire Bus Line
ETH_CRS 4700 5150 5950 5150
Wire Wire Line
4700 4000 5950 4000
Wire Wire Line
4700 6050 5950 6050
Wire Bus Line
4700 5050 5950 5050
Wire Bus Line
5950 5050 5950 5100
Wire Wire Line
4700 6150 5950 6150
Wire Wire Line
5950 4100 4700 4100
Wire Bus Line
4700 3050 5950 3050
Wire Wire Line
4700 5400 5950 5400
Wire Wire Line
4700 5700 5950 5700
Wire Wire Line
4700 6300 5950 6300
Wire Bus Line
4700 5250 5950 5250
Wire Wire Line
4700 6550 5950 6550
Wire Wire Line
4700 5950 5950 5950
Wire Wire Line
4700 4250 5950 4250
Wire Wire Line
4700 3900 5950 3900
Wire Wire Line
4700 3750 5950 3750
Wire Wire Line
4700 2800 5950 2800
Wire Bus Line
4700 3150 5950 3150
Wire Wire Line
9300 6500 10600 6500
Wire Wire Line
9300 6700 10600 6700
Wire Wire Line
10600 6900 9300 6900
Wire Wire Line
9300 7400 10600 7400
Wire Wire Line
9300 7800 10600 7800
Wire Wire Line
10650 5000 9300 5000
Wire Wire Line
10650 5200 9300 5200
Wire Wire Line
10650 5400 9300 5400
$Sheet $Sheet
S 5950 2700 3350 5800 S 5950 2700 3350 5800
U 4C431A63 U 4C431A63
@ -197,32 +162,49 @@ F2 "M1_CLK" O L 5950 4000 60
F3 "M1_CLK#" O L 5950 4100 60 F3 "M1_CLK#" O L 5950 4100 60
F4 "M0_CLK" O L 5950 6050 60 F4 "M0_CLK" O L 5950 6050 60
F5 "M0_CLK#" O L 5950 6150 60 F5 "M0_CLK#" O L 5950 6150 60
F6 "ETH_INT" I R 9300 6350 60 F6 "M0_A[0..12]" O L 5950 5150 60
F7 "M0_A[0..12]" O L 5950 5150 60 F7 "M1_A[0..12]" O L 5950 3050 60
F8 "M1_A[0..12]" O L 5950 3050 60 F8 "M0_DQ[0..15]" B L 5950 5050 60
F9 "M0_DQ[0..15]" B L 5950 5050 60 F9 "M0_UDQS" O L 5950 5400 60
F10 "M0_UDQS" O L 5950 5400 60 F10 "M0_LDM" O L 5950 5800 60
F11 "M0_LDM" O L 5950 5800 60 F11 "M0_LDQS" O L 5950 5500 60
F12 "M0_LDQS" O L 5950 5500 60 F12 "M0_UDM" O L 5950 5700 60
F13 "M0_UDM" O L 5950 5700 60 F13 "M0_RAS#" O L 5950 6400 60
F14 "M0_RAS#" O L 5950 6400 60 F14 "M0_WE#" O L 5950 6550 60
F15 "M0_WE#" O L 5950 6550 60 F15 "M0_CKE" O L 5950 5950 60
F16 "M0_CKE" O L 5950 5950 60 F16 "M0_CAS#" O L 5950 6300 60
F17 "M0_CAS#" O L 5950 6300 60 F17 "M1_CAS#" O L 5950 4250 60
F18 "M1_CAS#" O L 5950 4250 60 F18 "M1_CKE" O L 5950 3900 60
F19 "M1_CKE" O L 5950 3900 60 F19 "M0_CS#" O L 5950 4900 60
F20 "M0_CS#" O L 5950 4900 60 F20 "M1_CS#" O L 5950 2800 60
F21 "M1_CS#" O L 5950 2800 60 F21 "M1_WE#" O L 5950 4500 60
F22 "M1_WE#" O L 5950 4500 60 F22 "M1_RAS#" O L 5950 4350 60
F23 "M1_RAS#" O L 5950 4350 60 F23 "M1_UDM" O L 5950 3650 60
F24 "M1_UDM" O L 5950 3650 60 F24 "M1_LDQS" O L 5950 3450 60
F25 "M1_LDQS" O L 5950 3450 60 F25 "M1_LDM" O L 5950 3750 60
F26 "M1_LDM" O L 5950 3750 60 F26 "M1_UDQS" O L 5950 3350 60
F27 "M1_UDQS" O L 5950 3350 60 F27 "M1_DQ[0..15]" B L 5950 2950 60
F28 "M1_DQ[0..15]" B L 5950 2950 60 F28 "M1_BA[0..1]" O L 5950 3150 60
F29 "M0_BA[0..1]" O L 5950 5250 60
F30 "USBA_VM" B R 9300 5400 60
F31 "USBA_VP" B R 9300 5300 60
F32 "USBA_RCV" B R 9300 5200 60
F33 "USBA_OE_N" B R 9300 5100 60
F34 "USBA_SPD" B R 9300 5000 60
F35 "ETH_CLK" B R 9300 7900 60
F36 "ETH_RXC" B R 9300 6500 60
F37 "ETH_TXC" B R 9300 7500 60
F38 "ETH_TXD[0..3]" O R 9300 7600 60
F39 "ETH_TXEN" B R 9300 7700 60
F40 "ETH_TXER" B R 9300 7800 60
F41 "ETH_RXER" B R 9300 7400 60
F42 "ETH_RXDV" B R 9300 7300 60
F43 "ETH_RXD[0..3]" I R 9300 7200 60
F44 "ETH_RESET_N" B R 9300 6600 60
F45 "ETH_MDIO" B R 9300 6900 60
F46 "ETH_MDC" B R 9300 7000 60
F47 "ETH_INT" B R 9300 6350 60
$EndSheet $EndSheet
Text HLabel 9300 6500 0 60 Output ~ 0
ETH_RXC
Text HLabel 10650 5400 2 60 BiDi ~ 0 Text HLabel 10650 5400 2 60 BiDi ~ 0
USBA_VM USBA_VM
Text HLabel 10650 5300 2 60 BiDi ~ 0 Text HLabel 10650 5300 2 60 BiDi ~ 0