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85 lines
3.4 KiB
Verilog
85 lines
3.4 KiB
Verilog
/****************************************************************************************
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*
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* File Name: mobile_ddr_mcp.v
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*
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* Dependencies: mobile_ddr.v, mobile_ddr_parameters.vh
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*
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* Description: Micron MOBILE DDR SDRAM multi-chip package model
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2008 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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`timescale 1ns / 1ps
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module mobile_ddr_mcp (
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Clk ,
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Clk_n ,
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Cke ,
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Cs_n ,
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Ras_n ,
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Cas_n ,
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We_n ,
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Addr ,
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Ba ,
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Dq ,
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Dqs ,
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Dm
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);
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`include "mobile_ddr_parameters.vh"
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// Declare Ports
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input Clk ;
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input Clk_n ;
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input [CS_BITS - 1 : 0] Cke ;
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input [CS_BITS - 1 : 0] Cs_n ;
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input Ras_n ;
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input Cas_n ;
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input We_n ;
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input [ADDR_BITS - 1 : 0] Addr ;
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input [1 : 0] Ba ;
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inout [DQ_BITS - 1 : 0] Dq ;
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inout [DQS_BITS - 1 : 0] Dqs ;
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input [DM_BITS - 1 : 0] Dm ;
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wire [RANKS - 1 : 0] Cke_mcp = Cke ;
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wire [RANKS - 1 : 0] Cs_n_mcp = Cs_n ;
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mobile_ddr rank [RANKS - 1:0] (
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.Clk ( Clk ) ,
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.Clk_n ( Clk_n ) ,
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.Cke ( Cke_mcp ) ,
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.Cs_n ( Cs_n_mcp ) ,
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.Ras_n ( Ras_n ) ,
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.Cas_n ( Cas_n ) ,
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.We_n ( We_n ) ,
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.Addr ( Addr ) ,
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.Ba ( Ba ) ,
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.Dq ( Dq ) ,
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.Dqs ( Dqs ) ,
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.Dm ( Dm )
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);
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endmodule
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