mirror of
git://projects.qi-hardware.com/xue.git
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533 lines
13 KiB
Plaintext
533 lines
13 KiB
Plaintext
EESchema Schematic File Version 2 date Sat 09 Oct 2010 04:08:56 PM COT
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LIBS:power
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LIBS:r_pack2
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LIBS:v0402mhs03
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LIBS:usb-48204-0001
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LIBS:microsmd075f
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LIBS:mic2550
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LIBS:rj45-48025
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LIBS:xue-nv
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LIBS:xc6slx75fgg484
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LIBS:xc6slx45fgg484
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LIBS:micron_mobile_ddr
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LIBS:micron_ddr_512Mb
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LIBS:k8001
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:pasives-connectors
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LIBS:x25x64mb
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LIBS:attiny
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LIBS:PSU
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LIBS:tps793xx
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LIBS:reg102
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LIBS:mt9m033
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LIBS:m12-tu400a
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LIBS:xue-rnc-cache
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EELAYER 24 0
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EELAYER END
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$Descr A2 23400 16535
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Sheet 1 12
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Title ""
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Date "9 oct 2010"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 14800 5850 1100 5850
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U 4CB0D95D
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F0 "FPGA GPIOS" 60
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F1 "expantion.sch" 60
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$EndSheet
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Wire Wire Line
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9100 4950 10100 4950
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Wire Wire Line
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9100 4750 10100 4750
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Wire Wire Line
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10100 3750 9100 3750
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Wire Wire Line
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9100 4550 10100 4550
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Wire Wire Line
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9100 4350 10100 4350
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Wire Wire Line
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9100 4150 10100 4150
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Wire Wire Line
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10100 3950 9100 3950
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Wire Wire Line
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7300 5400 7550 5400
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Wire Wire Line
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7300 5100 7550 5100
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Wire Wire Line
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14750 13050 13400 13050
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Wire Wire Line
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14750 12850 13400 12850
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Wire Wire Line
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14750 12650 13400 12650
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Wire Wire Line
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9100 6950 10100 6950
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Wire Wire Line
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10100 6750 9100 6750
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Wire Bus Line
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14800 5500 13450 5500
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Wire Wire Line
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14800 4450 13450 4450
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Wire Wire Line
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14800 4850 13450 4850
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Wire Wire Line
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13450 4550 14800 4550
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Wire Wire Line
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14750 2200 13450 2200
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Wire Bus Line
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13450 4100 14800 4100
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Wire Wire Line
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13450 3900 14800 3900
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Wire Wire Line
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14750 12450 13400 12450
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Wire Wire Line
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14750 12250 13400 12250
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Wire Wire Line
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14750 12050 13400 12050
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Wire Wire Line
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13450 3200 14750 3200
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Wire Wire Line
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13450 2800 14750 2800
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Wire Wire Line
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14750 2300 13450 2300
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Wire Wire Line
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13450 1900 14750 1900
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Wire Bus Line
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8850 9850 10100 9850
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Wire Wire Line
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8850 9500 10100 9500
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Wire Wire Line
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8850 10450 10100 10450
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Wire Wire Line
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8850 10600 10100 10600
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Wire Wire Line
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8850 10950 10100 10950
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Wire Wire Line
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8850 12650 10100 12650
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Wire Wire Line
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8850 13250 10100 13250
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Wire Bus Line
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8850 11950 10100 11950
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Wire Wire Line
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8850 13000 10100 13000
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Wire Wire Line
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8850 12400 10100 12400
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Wire Wire Line
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8850 12100 10100 12100
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Wire Bus Line
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8850 9750 10100 9750
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Wire Wire Line
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10100 10800 8850 10800
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Wire Wire Line
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8850 12850 10100 12850
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Wire Bus Line
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10100 11800 10100 11750
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Wire Bus Line
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10100 11750 8850 11750
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Wire Wire Line
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8850 12750 10100 12750
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Wire Wire Line
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8850 10700 10100 10700
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Wire Bus Line
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8850 11850 10100 11850
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Wire Wire Line
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8850 12500 10100 12500
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Wire Wire Line
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8850 12200 10100 12200
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Wire Wire Line
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8850 13100 10100 13100
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Wire Wire Line
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8850 11600 10100 11600
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Wire Wire Line
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8850 11050 10100 11050
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Wire Wire Line
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8850 11200 10100 11200
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Wire Wire Line
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8850 10350 10100 10350
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Wire Wire Line
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8850 10150 10100 10150
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Wire Wire Line
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8850 10050 10100 10050
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Wire Bus Line
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8850 9650 10100 9650
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Wire Wire Line
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13450 1750 14750 1750
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Wire Wire Line
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13450 2000 14750 2000
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Wire Wire Line
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13450 2400 14750 2400
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Wire Wire Line
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13450 2700 14750 2700
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Wire Wire Line
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13450 2900 14750 2900
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Wire Wire Line
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13450 3100 14750 3100
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Wire Wire Line
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13450 3300 14750 3300
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Wire Wire Line
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14750 12150 13400 12150
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Wire Wire Line
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14750 12350 13400 12350
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Wire Bus Line
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13450 3000 14750 3000
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Wire Bus Line
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14750 2600 13450 2600
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Wire Wire Line
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13450 4000 14800 4000
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Wire Wire Line
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14750 2100 13450 2100
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Wire Bus Line
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14800 5050 13450 5050
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Wire Wire Line
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14800 4650 13450 4650
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Wire Wire Line
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14800 4750 13450 4750
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Wire Wire Line
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14800 4950 13450 4950
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Wire Wire Line
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14800 5300 13450 5300
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Wire Wire Line
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14800 5400 13450 5400
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Wire Wire Line
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10100 6850 9100 6850
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Wire Wire Line
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10100 7050 9100 7050
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Wire Wire Line
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14750 12750 13400 12750
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Wire Wire Line
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14750 12950 13400 12950
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Wire Wire Line
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7300 4950 7550 4950
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Wire Wire Line
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7300 5250 7550 5250
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Wire Wire Line
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7300 5550 7550 5550
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Wire Bus Line
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10100 5350 9100 5350
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Wire Wire Line
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9100 4050 10100 4050
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Wire Wire Line
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10100 4250 9100 4250
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Wire Wire Line
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9100 4450 10100 4450
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Wire Wire Line
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9100 4650 10100 4650
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Wire Wire Line
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9100 3850 10100 3850
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Wire Wire Line
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9100 4850 10100 4850
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$Sheet
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S 7550 3650 1550 2050
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U 4C9E2AF4
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F0 "Image Sensor" 60
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F1 "sensor.sch" 60
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F2 "+2.8_VDDIO" B L 7550 5100 60
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F3 "+1.8_VDD" B L 7550 5250 60
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F4 "+2.8_VAA" B L 7550 5550 60
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F5 "+2.8_VAAPIX" B L 7550 5400 60
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F6 "+2.8_VDDPLL" B L 7550 4950 60
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F7 "IS_TRIGGER" I R 9100 3750 60
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F8 "IS_FLASH" O R 9100 3850 60
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F9 "IS_SDA" B R 9100 3950 60
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F10 "IS_SCL" B R 9100 4050 60
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F11 "IS_I2C_ADDR" I R 9100 4150 60
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F12 "IS_EXTCLK" I R 9100 4250 60
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F13 "IS_RESET_N" I R 9100 4350 60
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F14 "IS_OE_N" I R 9100 4450 60
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F15 "IS_STANDBY" I R 9100 4550 60
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F16 "IS_TEST" I R 9100 4650 60
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F17 "IS_PIXEL" O R 9100 4750 60
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F18 "IS_LINE" O R 9100 4850 60
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F19 "IS_FRAME" O R 9100 4950 60
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F20 "IS_DOUT[0..11]" O R 9100 5350 60
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$EndSheet
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$Sheet
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S 6200 4650 1100 1000
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U 4C9E2B0F
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F0 "Snesor PSU" 60
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F1 "sensor_psu.sch" 60
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F2 "+2.8_VDDPLL" B R 7300 4950 60
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F3 "+2.8_VDDIO" B R 7300 5100 60
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F4 "+1.8_VDD" B R 7300 5250 60
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F5 "+2.8_VAAPIX" B R 7300 5400 60
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F6 "+2.8_VAA" B R 7300 5550 60
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$EndSheet
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$Sheet
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S 10100 1500 3350 6650
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U 4C7BC2B2
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F0 "FPGA, Port0, Port2, PROG IF" 60
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F1 "FPGA_0_2_PROG.sch" 60
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F2 "S6_TCK" I L 10100 6750 60
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F3 "S6_TDI" I L 10100 6850 60
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F4 "S6_TDO" O L 10100 6950 60
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F5 "S6_TMS" I L 10100 7050 60
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F6 "PROG_MISO[0..3]" B R 13450 5500 60
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F7 "PROG_CCLK" O R 13450 5400 60
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F8 "PROG_CSO" O R 13450 5300 60
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F9 "NF_D[0..7]" B R 13450 5050 60
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F10 "ETH_COL" B R 13450 2200 60
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F11 "ETH_CRS" B R 13450 2100 60
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F12 "NF_WE_N" O R 13450 4750 60
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F13 "NF_ALE" O R 13450 4550 60
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F14 "NF_CLE" O R 13450 4650 60
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F15 "NF_CS1_N" O R 13450 4450 60
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F16 "NF_RE_N" O R 13450 4850 60
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F17 "NF_RNB" B R 13450 4950 60
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F18 "SD_CLK" B R 13450 3900 60
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F19 "SD_CMD" B R 13450 4000 60
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F20 "SD_DAT[0..3]" B R 13450 4100 60
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F21 "ETH_CLK" B R 13450 3300 60
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F22 "ETH_RXC" B R 13450 1900 60
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F23 "ETH_TXC" B R 13450 2900 60
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F24 "ETH_TXD[0..3]" O R 13450 3000 60
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F25 "ETH_TXEN" B R 13450 3100 60
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F26 "ETH_TXER" B R 13450 3200 60
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F27 "ETH_RXER" B R 13450 2800 60
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F28 "ETH_RXDV" B R 13450 2700 60
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F29 "ETH_RXD[0..3]" I R 13450 2600 60
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F30 "ETH_RESET_N" B R 13450 2000 60
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F31 "ETH_MDIO" B R 13450 2300 60
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F32 "ETH_MDC" B R 13450 2400 60
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F33 "ETH_INT" B R 13450 1750 60
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F34 "IS_DOUT[0..11]" I L 10100 5350 60
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F35 "IS_TEST" O L 10100 4650 60
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F36 "IS_STANDBY" O L 10100 4550 60
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F37 "IS_OE_N" O L 10100 4450 60
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F38 "IS_RESET_N" O L 10100 4350 60
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F39 "IS_EXTCLK" O L 10100 4250 60
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F40 "IS_I2C_ADDR" O L 10100 4150 60
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F41 "IS_SCL" B L 10100 4050 60
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F42 "IS_SDA" B L 10100 3950 60
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F43 "IS_FRAME" I L 10100 4950 60
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F44 "IS_LINE" I L 10100 4850 60
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F45 "IS_PIXEL" I L 10100 4750 60
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F46 "IS_FLASH" I L 10100 3850 60
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F47 "IS_TRIGGER" O L 10100 3750 60
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F48 "FPGA_VCCO2_IO_AA18" B R 13450 5950 60
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F49 "FPGA_VCCO2_IO_AB21" B R 13450 6050 60
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F50 "FPGA_VCCO2_IO_W18" B R 13450 6150 60
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F51 "FPGA_VCCO2_IO_AB16" B R 13450 6250 60
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F52 "FPGA_VCCO2_IO_AB15" B R 13450 6350 60
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F53 "FPGA_VCCO2_IO_V7" B R 13450 6450 60
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F54 "FPGA_VCCO2_IO_W6" B R 13450 6550 60
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F55 "FPGA_VCCO2_IO_W4" B R 13450 6650 60
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F56 "FPGA_VCCO2_IO_Y10" B R 13450 6750 60
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F57 "FPGA_VCCO2_IO_Y9" B R 13450 6850 60
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F58 "FPGA_VCCO2_IO_Y15" B R 13450 6950 60
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F59 "FPGA_VCCO2_IO_Y16" B R 13450 7050 60
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F60 "FPGA_VCCO2_IO_W10" B R 13450 7150 60
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F61 "FPGA_VCCO2_IO_W11" B R 13450 7250 60
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F62 "FPGA_VCCO2_IO_Y12" B R 13450 7350 60
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F63 "FPGA_VCCO2_IO_AB14" B R 13450 7450 60
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F64 "FPGA_VCCO2_IO_AB13" B R 13450 7550 60
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F65 "FPGA_VCCO2_IO_Y11" B R 13450 7650 60
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F66 "FPGA_VCCO2_IO_W8" B R 13450 7750 60
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F67 "FPGA_VCCO2_IO_U9" B R 13450 7850 60
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$EndSheet
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$Sheet
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S 10100 9250 3300 4350
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U 4C7BC2A2
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F0 "FPGA Port 1, Port 3 DDR, USB" 60
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F1 "FPGA_1_3.sch" 60
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F2 "USBD_VP" B R 13400 12950 60
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F3 "USBD_SPD" B R 13400 12650 60
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F4 "USBD_OE_N" B R 13400 12750 60
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F5 "USBD_RCV" B R 13400 12850 60
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F6 "USBD_VM" B R 13400 13050 60
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F7 "M0_CKE" O L 10100 12650 60
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F8 "M0_UDM" O L 10100 12400 60
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F9 "M0_UDQS" O L 10100 12100 60
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F10 "M0_BA[0..1]" O L 10100 11950 60
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F11 "M0_CAS#" O L 10100 13000 60
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F12 "M0_RAS#" O L 10100 13100 60
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F13 "M0_WE#" O L 10100 13250 60
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F14 "M0_LDM" O L 10100 12500 60
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F15 "M0_LDQS" O L 10100 12200 60
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F16 "M1_UDQS" O L 10100 10050 60
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F17 "M1_UDM" O L 10100 10350 60
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F18 "M1_LDQS" O L 10100 10150 60
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F19 "M1_LDM" O L 10100 10450 60
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F20 "M1_WE#" O L 10100 11200 60
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F21 "M1_CKE" O L 10100 10600 60
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F22 "M1_RAS#" O L 10100 11050 60
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F23 "M1_CAS#" O L 10100 10950 60
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F24 "M1_BA[0..1]" O L 10100 9850 60
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F25 "M1_CS#" O L 10100 9500 60
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F26 "USBA_VM" B R 13400 12450 60
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F27 "USBA_VP" B R 13400 12350 60
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F28 "USBA_RCV" B R 13400 12250 60
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F29 "USBA_OE_N" B R 13400 12150 60
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F30 "USBA_SPD" B R 13400 12050 60
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F31 "M1_DQ[0..15]" B L 10100 9650 60
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F32 "M0_CS#" O L 10100 11600 60
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F33 "M0_DQ[0..15]" B L 10100 11750 60
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F34 "M0_A[0..12]" O L 10100 11850 60
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F35 "M1_A[0..12]" O L 10100 9750 60
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F36 "M1_CLK" O L 10100 10700 60
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F37 "M1_CLK#" O L 10100 10800 60
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F38 "M0_CLK" O L 10100 12750 60
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F39 "M0_CLK#" O L 10100 12850 60
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F40 "FPGA_2.5V_IO_M17" B R 13400 9900 60
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F41 "FPGA_2.5V_IO_N16" B R 13400 10000 60
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F42 "FPGA_2.5V_IO_P19" B R 13400 10100 60
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F43 "FPGA_2.5V_IO_P17" B R 13400 10200 60
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F44 "FPGA_2.5V_IO_P18" B R 13400 10300 60
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F45 "FPGA_2.5V_IO_U19" B R 13400 10400 60
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F46 "FPGA_2.5V_IO_T20" B R 13400 10500 60
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F47 "FPGA_2.5V_IO_V20" B R 13400 10600 60
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F48 "FPGA_2.5V_IO_W20" B R 13400 10700 60
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F49 "FPGA_2.5V_IO_W22" B R 13400 10800 60
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F50 "FPGA_2.5V_IO_V3" B R 13400 10900 60
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F51 "FPGA_2.5V_IO_U4" B R 13400 11000 60
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F52 "FPGA_2.5V_IO_T3" B R 13400 11100 60
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F53 "FPGA_2.5V_IO_T4" B R 13400 11200 60
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F54 "FPGA_2.5V_IO_P7" B R 13400 11300 60
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F55 "FPGA_2.5V_IO_P8" B R 13400 11400 60
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F56 "FPGA_2.5V_IO_W1" B R 13400 11500 60
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F57 "FPGA_2.5V_IO_W3" B R 13400 11600 60
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F58 "FPGA_2.5V_IO_Y1" B R 13400 11700 60
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F59 "FPGA_2.5V_IO_Y2" B R 13400 11800 60
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$EndSheet
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$Sheet
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S 7900 6700 1200 700
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U 4C716A4D
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F0 "DBG_PRG" 60
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F1 "DBG_PRG.sch" 60
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F2 "FPGA_TDO" B R 9100 6950 60
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F3 "FPGA_TDI" B R 9100 6850 60
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F4 "FPGA_TMS" B R 9100 7050 60
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F5 "FPGA_TCK" B R 9100 6750 60
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$EndSheet
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$Sheet
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S 7900 1750 1200 750
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U 4C69ED5F
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F0 "PSU" 60
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F1 "PSU.sch" 60
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$EndSheet
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$Sheet
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S 14800 3700 1050 1950
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U 4C4227FE
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F0 "Non volatile memories" 60
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F1 "NV_MEMORIES.sch" 60
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F2 "SD_CMD" I L 14800 4000 60
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F3 "SD_CLK" I L 14800 3900 60
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F4 "SD_DAT[0..3]" B L 14800 4100 60
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F5 "NF_D[0..7]" B L 14800 5050 60
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F6 "NF_ALE" B L 14800 4550 60
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F7 "NF_CLE" B L 14800 4650 60
|
|
F8 "NF_WE_N" B L 14800 4750 60
|
|
F9 "NF_CS1_N" B L 14800 4450 60
|
|
F10 "NF_RE_N" B L 14800 4850 60
|
|
F11 "NF_RNB" B L 14800 4950 60
|
|
F12 "SPI_CLK" I L 14800 5400 60
|
|
F13 "SPI_FLASH_CS#" I L 14800 5300 60
|
|
F14 "SPI_DQ[0..3]" B L 14800 5500 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 14750 12000 1100 1150
|
|
U 4C5F1EDC
|
|
F0 "USB" 60
|
|
F1 "USB.sch" 60
|
|
F2 "USBA_SPD" B L 14750 12050 60
|
|
F3 "USBA_OE_N" B L 14750 12150 60
|
|
F4 "USBA_RCV" B L 14750 12250 60
|
|
F5 "USBA_VP" B L 14750 12350 60
|
|
F6 "USBA_VM" B L 14750 12450 60
|
|
F7 "USBD_SPD" B L 14750 12650 60
|
|
F8 "USBD_OE_N" B L 14750 12750 60
|
|
F9 "USBD_RCV" B L 14750 12850 60
|
|
F10 "USBD_VP" B L 14750 12950 60
|
|
F11 "USBD_VM" B L 14750 13050 60
|
|
$EndSheet
|
|
Text Notes 19700 15650 0 60 ~ 0
|
|
Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com
|
|
$Sheet
|
|
S 14750 1650 1300 1800
|
|
U 4C4320F3
|
|
F0 "Ethernet Phy" 60
|
|
F1 "eth_phy.sch" 60
|
|
F2 "ETH_RXC" O L 14750 1900 60
|
|
F3 "ETH_RST_N" I L 14750 2000 60
|
|
F4 "ETH_CRS" O L 14750 2100 60
|
|
F5 "ETH_COL" O L 14750 2200 60
|
|
F6 "ETH_MDIO" B L 14750 2300 60
|
|
F7 "ETH_MDC" I L 14750 2400 60
|
|
F8 "ETH_RXD[0..3]" O L 14750 2600 60
|
|
F9 "ETH_RXDV" O L 14750 2700 60
|
|
F10 "ETH_RXER" O L 14750 2800 60
|
|
F11 "ETH_TXC" B L 14750 2900 60
|
|
F12 "ETH_TXD[0..3]" I L 14750 3000 60
|
|
F13 "ETH_TXEN" I L 14750 3100 60
|
|
F14 "ETH_TXER" I L 14750 3200 60
|
|
F15 "ETH_CLK" I L 14750 3300 60
|
|
F16 "ETH_INT" O L 14750 1750 60
|
|
$EndSheet
|
|
$Sheet
|
|
S 7750 9400 1100 4000
|
|
U 4C421DD3
|
|
F0 "DDR Banks" 60
|
|
F1 "DRAM.sch" 60
|
|
F2 "M0_BA[0..1]" I R 8850 11950 60
|
|
F3 "M1_BA[0..1]" I R 8850 9850 60
|
|
F4 "M0_WE#" I R 8850 13250 60
|
|
F5 "M0_RAS#" I R 8850 13100 60
|
|
F6 "M1_RAS#" I R 8850 11050 60
|
|
F7 "M1_WE#" I R 8850 11200 60
|
|
F8 "M0_CAS#" I R 8850 13000 60
|
|
F9 "M0_CKE" I R 8850 12650 60
|
|
F10 "M0_CLK" I R 8850 12750 60
|
|
F11 "M0_CLK#" I R 8850 12850 60
|
|
F12 "M0_CS#" I R 8850 11600 60
|
|
F13 "M1_CLK#" I R 8850 10800 60
|
|
F14 "M1_CLK" I R 8850 10700 60
|
|
F15 "M1_CKE" I R 8850 10600 60
|
|
F16 "M1_CAS#" I R 8850 10950 60
|
|
F17 "M0_DQ[0..15]" B R 8850 11750 60
|
|
F18 "M0_UDM" I R 8850 12400 60
|
|
F19 "M0_LDQS" I R 8850 12200 60
|
|
F20 "M0_A[0..12]" I R 8850 11850 60
|
|
F21 "M0_LDM" I R 8850 12500 60
|
|
F22 "M0_UDQS" I R 8850 12100 60
|
|
F23 "M1_UDQS" I R 8850 10050 60
|
|
F24 "M1_LDM" I R 8850 10450 60
|
|
F25 "M1_LDQS" I R 8850 10150 60
|
|
F26 "M1_UDM" I R 8850 10350 60
|
|
F27 "M1_CS#" I R 8850 9500 60
|
|
F28 "M1_A[0..12]" I R 8850 9750 60
|
|
F29 "M1_DQ[0..15]" B R 8850 9650 60
|
|
$EndSheet
|
|
$EndSCHEMATC
|