906 lines
23 KiB
C
906 lines
23 KiB
C
/* Compute register class preferences for pseudo-registers.
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Copyright (C) 1987, 1988 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* This file contains two passes of the compiler: reg_scan and reg_class.
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It also defines some tables of information about the hardware registers
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and a function init_reg_sets to initialize the tables. */
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#include "config.h"
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#include "rtl.h"
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#include "hard-reg-set.h"
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#include "flags.h"
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#include "basic-block.h"
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#include "regs.h"
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#include "insn-config.h"
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#include "recog.h"
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#define max(A,B) ((A) > (B) ? (A) : (B))
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#define min(A,B) ((A) < (B) ? (A) : (B))
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/* Register tables used by many passes. */
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/* Indexed by hard register number, contains 1 for registers
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that are fixed use (stack pointer, pc, frame pointer, etc.).
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These are the registers that cannot be used to allocate
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a pseudo reg whose life does not cross calls. */
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char fixed_regs[FIRST_PSEUDO_REGISTER];
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/* Same info as a HARD_REG_SET. */
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HARD_REG_SET fixed_reg_set;
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/* Data for initializing the above. */
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static char initial_fixed_regs[] = FIXED_REGISTERS;
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/* Indexed by hard register number, contains 1 for registers
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that are fixed use or are clobbered by function calls.
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These are the registers that cannot be used to allocate
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a pseudo reg whose life crosses calls. */
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char call_used_regs[FIRST_PSEUDO_REGISTER];
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/* Same info as a HARD_REG_SET. */
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HARD_REG_SET call_used_reg_set;
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/* Data for initializing the above. */
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static char initial_call_used_regs[] = CALL_USED_REGISTERS;
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/* Indexed by hard register number, contains 1 for registers that are
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fixed use -- i.e. in fixed_regs -- or a function value return register
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or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
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registers that cannot hold quantities across calls even if we are
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willing to save and restore them. */
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char call_fixed_regs[FIRST_PSEUDO_REGISTER];
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/* The same info as a HARD_REG_SET. */
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HARD_REG_SET call_fixed_reg_set;
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/* Indexed by hard register number, contains 1 for registers
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that are being used for global register decls.
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These must be exempt from ordinary flow analysis
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and are also considered fixed. */
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char global_regs[FIRST_PSEUDO_REGISTER];
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/* Table of register numbers in the order in which to try to use them. */
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#ifdef REG_ALLOC_ORDER
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int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
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#endif
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/* For each reg class, a HARD_REG_SET saying which registers are in it. */
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HARD_REG_SET reg_class_contents[] = REG_CLASS_CONTENTS;
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/* For each reg class, number of regs it contains. */
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int reg_class_size[N_REG_CLASSES];
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/* For each reg class, table listing all the containing classes. */
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enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
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/* For each reg class, table listing all the classes contained in it. */
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enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
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/* For each pair of reg classes,
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a largest reg class contained in their union. */
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enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
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/* Array containing all of the register names */
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char *reg_names[] = REGISTER_NAMES;
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/* Function called only once to initialize the above data on reg usage.
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Once this is done, various switches may override. */
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void
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init_reg_sets ()
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{
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register int i, j;
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bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs);
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bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs);
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bzero (global_regs, sizeof global_regs);
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/* Compute number of hard regs in each class. */
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bzero (reg_class_size, sizeof reg_class_size);
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for (i = 0; i < N_REG_CLASSES; i++)
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for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
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if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
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reg_class_size[i]++;
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/* Initialize the table of subunions.
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reg_class_subunion[I][J] gets the largest-numbered reg-class
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that is contained in the union of classes I and J. */
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for (i = 0; i < N_REG_CLASSES; i++)
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{
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for (j = 0; j < N_REG_CLASSES; j++)
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{
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#ifdef HARD_REG_SET
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register /* Declare it register if it's a scalar. */
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#endif
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HARD_REG_SET c;
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register int k;
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COPY_HARD_REG_SET (c, reg_class_contents[i]);
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IOR_HARD_REG_SET (c, reg_class_contents[j]);
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for (k = 0; k < N_REG_CLASSES; k++)
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{
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GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
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subclass1);
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continue;
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subclass1:
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reg_class_subunion[i][j] = (enum reg_class) k;
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}
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}
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}
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/* Initialize the tables of subclasses and superclasses of each reg class.
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First clear the whole table, then add the elements as they are found. */
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for (i = 0; i < N_REG_CLASSES; i++)
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{
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for (j = 0; j < N_REG_CLASSES; j++)
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{
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reg_class_superclasses[i][j] = LIM_REG_CLASSES;
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reg_class_subclasses[i][j] = LIM_REG_CLASSES;
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}
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}
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for (i = 0; i < N_REG_CLASSES; i++)
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{
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if (i == (int) NO_REGS)
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continue;
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for (j = i + 1; j < N_REG_CLASSES; j++)
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{
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enum reg_class *p;
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GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
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subclass);
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continue;
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subclass:
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/* Reg class I is a subclass of J.
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Add J to the table of superclasses of I. */
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p = ®_class_superclasses[i][0];
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while (*p != LIM_REG_CLASSES) p++;
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*p = (enum reg_class) j;
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/* Add I to the table of superclasses of J. */
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p = ®_class_subclasses[j][0];
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while (*p != LIM_REG_CLASSES) p++;
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*p = (enum reg_class) i;
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}
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}
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}
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/* After switches have been processed, which perhaps alter
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`fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
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void
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init_reg_sets_1 ()
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{
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register int i;
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/* This macro allows the fixed or call-used registers
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to depend on target flags. */
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#ifdef CONDITIONAL_REGISTER_USAGE
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CONDITIONAL_REGISTER_USAGE;
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#endif
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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if (global_regs[i])
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{
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if (call_used_regs[i] && ! fixed_regs[i])
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warning ("call-clobbered register used for global register variable");
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fixed_regs[i] = 1;
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/* Prevent saving/restoring of this reg. */
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call_used_regs[i] = 1;
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}
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/* Initialize "constant" tables. */
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CLEAR_HARD_REG_SET (fixed_reg_set);
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CLEAR_HARD_REG_SET (call_used_reg_set);
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CLEAR_HARD_REG_SET (call_fixed_reg_set);
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bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs);
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#ifdef STRUCT_VALUE_REGNUM
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call_fixed_regs[STRUCT_VALUE_REGNUM] = 1;
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#endif
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#ifdef STATIC_CHAIN_REGNUM
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call_fixed_regs[STATIC_CHAIN_REGNUM] = 1;
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#endif
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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{
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if (FUNCTION_VALUE_REGNO_P (i))
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call_fixed_regs[i] = 1;
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if (fixed_regs[i])
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SET_HARD_REG_BIT (fixed_reg_set, i);
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if (call_used_regs[i])
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SET_HARD_REG_BIT (call_used_reg_set, i);
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if (call_fixed_regs[i])
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SET_HARD_REG_BIT (call_fixed_reg_set, i);
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}
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}
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/* Specify the usage characteristics of the register named NAME.
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It should be a fixed register if FIXED and a
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call-used register if CALL_USED. */
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void
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fix_register (name, fixed, call_used)
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char *name;
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int fixed, call_used;
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{
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int i;
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/* Decode the name and update the primary form of
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the register info. */
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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if (!strcmp (reg_names[i], name))
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{
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fixed_regs[i] = fixed;
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call_used_regs[i] = call_used;
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break;
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}
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if (i == FIRST_PSEUDO_REGISTER)
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{
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warning ("unknown register name: %s", name);
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return;
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}
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}
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/* Now the data and code for the `regclass' pass, which happens
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just before local-alloc. */
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/* savings[R].savings[CL] is twice the amount saved by putting register R
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in class CL. This data is used within `regclass' and freed
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when it is finished. */
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struct savings
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{
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short savings[N_REG_CLASSES];
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short memcost;
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short nrefs;
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};
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static struct savings *savings;
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/* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
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This is available after `regclass' is run. */
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static char *prefclass;
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/* preferred_or_nothing[R] is nonzero if we should put pseudo number R
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in memory if we can't get its perferred class.
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This is available after `regclass' is run. */
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static char *preferred_or_nothing;
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void reg_class_record ();
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void record_address_regs ();
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/* Return the reg_class in which pseudo reg number REGNO is best allocated.
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This function is sometimes called before the info has been computed.
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When that happens, just return GENERAL_REGS, which is innocuous. */
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enum reg_class
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reg_preferred_class (regno)
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int regno;
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{
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if (prefclass == 0)
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return GENERAL_REGS;
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return (enum reg_class) prefclass[regno];
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}
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int
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reg_preferred_or_nothing (regno)
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{
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if (prefclass == 0)
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return 0;
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return preferred_or_nothing[regno];
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}
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/* This prevents dump_flow_info from losing if called
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before regclass is run. */
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int
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regclass_init ()
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{
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prefclass = 0;
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}
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/* This is a pass of the compiler that scans all instructions
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and calculates the preferred class for each pseudo-register.
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This information can be accessed later by calling `reg_preferred_class'.
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This pass comes just before local register allocation. */
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void
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regclass (f, nregs)
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rtx f;
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int nregs;
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{
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#ifdef REGISTER_CONSTRAINTS
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register rtx insn;
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register int i;
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init_recog ();
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/* Zero out our accumulation of the cost of each class for each reg. */
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savings = (struct savings *) alloca (nregs * sizeof (struct savings));
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bzero (savings, nregs * sizeof (struct savings));
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/* Scan the instructions and record each time it would
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save code to put a certain register in a certain class. */
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for (insn = f; insn; insn = NEXT_INSN (insn))
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if ((GET_CODE (insn) == INSN
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&& GET_CODE (PATTERN (insn)) != USE
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&& GET_CODE (PATTERN (insn)) != CLOBBER
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&& GET_CODE (PATTERN (insn)) != ASM_INPUT)
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|| (GET_CODE (insn) == JUMP_INSN
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&& GET_CODE (PATTERN (insn)) != ADDR_VEC
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&& GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
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|| GET_CODE (insn) == CALL_INSN)
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{
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if (GET_CODE (insn) == INSN && asm_noperands (PATTERN (insn)) >= 0)
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{
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int noperands = asm_noperands (PATTERN (insn));
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/* We don't use alloca because alloca would not free
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any of the space until this function returns. */
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rtx *operands = (rtx *) oballoc (noperands * sizeof (rtx));
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char **constraints
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= (char **) oballoc (noperands * sizeof (char *));
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decode_asm_operands (PATTERN (insn), operands, 0, constraints, 0);
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for (i = noperands - 1; i >= 0; i--)
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reg_class_record (operands[i], i, constraints);
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obfree (operands);
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}
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else
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{
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int insn_code_number = recog_memoized (insn);
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insn_extract (insn);
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for (i = insn_n_operands[insn_code_number] - 1; i >= 0; i--)
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reg_class_record (recog_operand[i], i,
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insn_operand_constraint[insn_code_number]);
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/* Improve handling of two-address insns such as
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(set X (ashift CONST Y)) where CONST must be made to match X.
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Change it into two insns: (set X CONST) (set X (ashift X Y)).
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If we left this for reloading, it would probably get three insns
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because X and Y might go in the same place.
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This prevents X and Y from receiving the same hard reg. */
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if (optimize
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&& insn_n_operands[insn_code_number] >= 3
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&& insn_operand_constraint[insn_code_number][1][0] == '0'
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&& insn_operand_constraint[insn_code_number][1][1] == 0
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&& CONSTANT_P (recog_operand[1])
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&& ! rtx_equal_p (recog_operand[0], recog_operand[1])
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&& ! rtx_equal_p (recog_operand[0], recog_operand[2])
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&& GET_CODE (recog_operand[0]) == REG)
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{
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rtx previnsn = prev_real_insn (insn);
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rtx newinsn
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= emit_insn_before (gen_move_insn (recog_operand[0],
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recog_operand[1]),
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insn);
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/* If this insn was the start of a basic block,
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include the new insn in that block. */
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if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
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{
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int b;
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for (b = 0; b < n_basic_blocks; b++)
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if (insn == basic_block_head[b])
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basic_block_head[b] = newinsn;
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}
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/* This makes one more setting of new insns's destination. */
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reg_n_sets[REGNO (recog_operand[0])]++;
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*recog_operand_loc[1] = recog_operand[0];
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for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--)
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if (recog_dup_num[i] == 1)
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*recog_dup_loc[i] = recog_operand[0];
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}
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}
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}
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/* Now for each register look at how desirable each class is
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and find which class is preferred. Store that in `prefclass[REGNO]'. */
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prefclass = (char *) oballoc (nregs);
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preferred_or_nothing = (char *) oballoc (nregs);
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for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
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{
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register int best_savings = 0;
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enum reg_class best = ALL_REGS;
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/* This is an enum reg_class, but we call it an int
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to save lots of casts. */
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register int class;
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register struct savings *p = &savings[i];
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for (class = (int) ALL_REGS - 1; class > 0; class--)
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{
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if (p->savings[class] > best_savings)
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{
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best_savings = p->savings[class];
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best = (enum reg_class) class;
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}
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else if (p->savings[class] == best_savings)
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{
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best = reg_class_subunion[(int)best][class];
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}
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}
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#if 0
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/* Note that best_savings is twice number of places something
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is saved. */
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if ((best_savings - p->savings[(int) GENERAL_REGS]) * 5 < reg_n_refs[i])
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prefclass[i] = (int) GENERAL_REGS;
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else
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prefclass[i] = (int) best;
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#else
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/* We cast to (int) because (char) hits bugs in some compilers. */
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prefclass[i] = (int) best;
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#endif
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/* reg_n_refs + p->memcost measures the cost of putting in memory.
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If a GENERAL_REG is no better, don't even try for one.
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Since savings and memcost are 2 * number of refs,
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this effectively counts each memory operand not needing reloading
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as costing 1/2 of a reload insn. */
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if (reg_n_refs != 0)
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preferred_or_nothing[i]
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= ((best_savings - p->savings[(int) GENERAL_REGS])
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>= p->nrefs + p->memcost);
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}
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#endif /* REGISTER_CONSTRAINTS */
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}
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#ifdef REGISTER_CONSTRAINTS
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/* Scan an operand OP for register class preferences.
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OPNO is the operand number, and CONSTRAINTS is the constraint
|
||
vector for the insn.
|
||
|
||
Record the preferred register classes from the constraint for OP
|
||
if OP is a register. If OP is a memory reference, record suitable
|
||
preferences for registers used in the address. */
|
||
|
||
void
|
||
reg_class_record (op, opno, constraints)
|
||
rtx op;
|
||
int opno;
|
||
char **constraints;
|
||
{
|
||
char *constraint = constraints[opno];
|
||
register char *p;
|
||
register enum reg_class class = NO_REGS;
|
||
char *next = 0;
|
||
int memok = 0;
|
||
int double_cost = 0;
|
||
|
||
while (1)
|
||
{
|
||
if (GET_CODE (op) == SUBREG)
|
||
op = SUBREG_REG (op);
|
||
else break;
|
||
}
|
||
|
||
/* Memory reference: scan the address. */
|
||
|
||
if (GET_CODE (op) == MEM)
|
||
record_address_regs (XEXP (op, 0), 2, 0);
|
||
|
||
if (GET_CODE (op) != REG)
|
||
{
|
||
/* If the constraint says the operand is supposed to BE an address,
|
||
scan it as one. */
|
||
|
||
if (constraint != 0 && constraint[0] == 'p')
|
||
record_address_regs (op, 2, 0);
|
||
return;
|
||
}
|
||
|
||
/* Operand is a register: examine the constraint for specified classes. */
|
||
|
||
for (p = constraint; *p || next; p++)
|
||
{
|
||
if (*p == 0)
|
||
{
|
||
p = next;
|
||
next = 0;
|
||
}
|
||
switch (*p)
|
||
{
|
||
case '=':
|
||
case '?':
|
||
case '#':
|
||
case '&':
|
||
case '!':
|
||
case '%':
|
||
case 'F':
|
||
case 'G':
|
||
case 'H':
|
||
case 'i':
|
||
case 'n':
|
||
case 's':
|
||
case 'p':
|
||
case ',':
|
||
break;
|
||
|
||
case '+':
|
||
/* An input-output operand is twice as costly if it loses. */
|
||
double_cost = 1;
|
||
break;
|
||
|
||
case 'm':
|
||
case 'o':
|
||
memok = 1;
|
||
break;
|
||
|
||
/* * means ignore following letter
|
||
when choosing register preferences. */
|
||
case '*':
|
||
p++;
|
||
break;
|
||
|
||
case 'g':
|
||
case 'r':
|
||
class
|
||
= reg_class_subunion[(int) class][(int) GENERAL_REGS];
|
||
break;
|
||
|
||
case '0':
|
||
case '1':
|
||
case '2':
|
||
case '3':
|
||
case '4':
|
||
/* If constraint says "match another operand",
|
||
use that operand's constraint to choose preferences. */
|
||
next = constraints[*p - '0'];
|
||
break;
|
||
|
||
default:
|
||
class
|
||
= reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (*p)];
|
||
}
|
||
}
|
||
|
||
{
|
||
register int i;
|
||
register struct savings *pp;
|
||
register enum reg_class class1;
|
||
int cost = 2 * (1 + double_cost);
|
||
pp = &savings[REGNO (op)];
|
||
|
||
/* Increment the savings for this reg
|
||
for each class contained in the one the constraint asks for. */
|
||
|
||
if (class != NO_REGS && class != ALL_REGS)
|
||
{
|
||
pp->savings[(int) class] += cost;
|
||
for (i = 0; ; i++)
|
||
{
|
||
class1 = reg_class_subclasses[(int)class][i];
|
||
if (class1 == LIM_REG_CLASSES)
|
||
break;
|
||
pp->savings[(int) class1] += cost;
|
||
}
|
||
}
|
||
|
||
if (! memok)
|
||
pp->memcost += 1 + 2 * double_cost;
|
||
pp->nrefs++;
|
||
}
|
||
}
|
||
|
||
/* Record the pseudo registers we must reload into hard registers
|
||
in a subexpression of a memory address, X.
|
||
BCOST is the cost if X is a register and it fails to be in BASE_REG_CLASS.
|
||
ICOST is the cost if it fails to be in INDEX_REG_CLASS. */
|
||
|
||
void
|
||
record_address_regs (x, bcost, icost)
|
||
rtx x;
|
||
int bcost, icost;
|
||
{
|
||
register enum rtx_code code = GET_CODE (x);
|
||
|
||
switch (code)
|
||
{
|
||
case CONST_INT:
|
||
case CONST:
|
||
case CC0:
|
||
case PC:
|
||
case SYMBOL_REF:
|
||
case LABEL_REF:
|
||
return;
|
||
|
||
case PLUS:
|
||
/* When we have an address that is a sum,
|
||
we must determine whether registers are "base" or "index" regs.
|
||
If there is a sum of two registers, we must choose one to be
|
||
the "base". Luckily, we can use the REGNO_POINTER_FLAG
|
||
to make a good choice most of the time. */
|
||
{
|
||
rtx arg0 = XEXP (x, 0);
|
||
rtx arg1 = XEXP (x, 1);
|
||
register enum rtx_code code0 = GET_CODE (arg0);
|
||
register enum rtx_code code1 = GET_CODE (arg1);
|
||
int icost0 = 0;
|
||
int icost1 = 0;
|
||
int suppress1 = 0;
|
||
int suppress0 = 0;
|
||
|
||
/* Look inside subregs. */
|
||
while (code0 == SUBREG)
|
||
arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
|
||
while (code1 == SUBREG)
|
||
arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
|
||
|
||
if (code0 == MULT || code1 == MEM)
|
||
icost0 = 2;
|
||
else if (code1 == MULT || code0 == MEM)
|
||
icost1 = 2;
|
||
else if (code0 == CONST_INT)
|
||
suppress0 = 1;
|
||
else if (code1 == CONST_INT)
|
||
suppress1 = 1;
|
||
else if (code0 == REG && code1 == REG)
|
||
{
|
||
if (REGNO_POINTER_FLAG (REGNO (arg0)))
|
||
icost1 = 2;
|
||
else if (REGNO_POINTER_FLAG (REGNO (arg1)))
|
||
icost0 = 2;
|
||
else
|
||
icost0 = icost1 = 1;
|
||
}
|
||
else if (code0 == REG)
|
||
{
|
||
if (code1 == PLUS
|
||
&& ! REGNO_POINTER_FLAG (REGNO (arg0)))
|
||
icost0 = 2;
|
||
else
|
||
REGNO_POINTER_FLAG (REGNO (arg0)) = 1;
|
||
}
|
||
else if (code1 == REG)
|
||
{
|
||
if (code0 == PLUS
|
||
&& ! REGNO_POINTER_FLAG (REGNO (arg1)))
|
||
icost1 = 2;
|
||
else
|
||
REGNO_POINTER_FLAG (REGNO (arg1)) = 1;
|
||
}
|
||
|
||
/* ICOST0 determines whether we are treating operand 0
|
||
as a base register or as an index register.
|
||
SUPPRESS0 nonzero means it isn't a register at all.
|
||
ICOST1 and SUPPRESS1 are likewise for operand 1. */
|
||
|
||
if (! suppress0)
|
||
record_address_regs (arg0, 2 - icost0, icost0);
|
||
if (! suppress1)
|
||
record_address_regs (arg1, 2 - icost1, icost1);
|
||
}
|
||
break;
|
||
|
||
case POST_INC:
|
||
case PRE_INC:
|
||
case POST_DEC:
|
||
case PRE_DEC:
|
||
/* Double the importance of a pseudo register that is incremented
|
||
or decremented, since it would take two extra insns
|
||
if it ends up in the wrong place. */
|
||
record_address_regs (XEXP (x, 0), 2 * bcost, 2 * icost);
|
||
break;
|
||
|
||
case REG:
|
||
{
|
||
register struct savings *pp;
|
||
register enum reg_class class, class1;
|
||
pp = &savings[REGNO (x)];
|
||
pp->nrefs++;
|
||
|
||
/* We have an address (or part of one) that is just one register. */
|
||
|
||
/* Record BCOST worth of savings for classes contained
|
||
in BASE_REG_CLASS. */
|
||
|
||
class = BASE_REG_CLASS;
|
||
if (class != NO_REGS && class != ALL_REGS)
|
||
{
|
||
register int i;
|
||
pp->savings[(int) class] += bcost;
|
||
for (i = 0; ; i++)
|
||
{
|
||
class1 = reg_class_subclasses[(int)class][i];
|
||
if (class1 == LIM_REG_CLASSES)
|
||
break;
|
||
pp->savings[(int) class1] += bcost;
|
||
}
|
||
}
|
||
|
||
/* Record ICOST worth of savings for classes contained
|
||
in INDEX_REG_CLASS. */
|
||
|
||
class = INDEX_REG_CLASS;
|
||
if (icost != 0 && class != NO_REGS && class != ALL_REGS)
|
||
{
|
||
register int i;
|
||
pp->savings[(int) class] += icost;
|
||
for (i = 0; ; i++)
|
||
{
|
||
class1 = reg_class_subclasses[(int)class][i];
|
||
if (class1 == LIM_REG_CLASSES)
|
||
break;
|
||
pp->savings[(int) class1] += icost;
|
||
}
|
||
}
|
||
}
|
||
break;
|
||
|
||
default:
|
||
{
|
||
register char *fmt = GET_RTX_FORMAT (code);
|
||
register int i;
|
||
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
||
if (fmt[i] == 'e')
|
||
record_address_regs (XEXP (x, i), bcost, icost);
|
||
}
|
||
}
|
||
}
|
||
#endif /* REGISTER_CONSTRAINTS */
|
||
|
||
/* This is the `regscan' pass of the compiler, run just before cse
|
||
and again just before loop.
|
||
|
||
It finds the first and last use of each pseudo-register
|
||
and records them in the vectors regno_first_uid, regno_last_uid.
|
||
REPEAT is nonzero the second time this is called. */
|
||
|
||
/* Indexed by pseudo register number, gives uid of first insn using the reg
|
||
(as of the time reg_scan is called). */
|
||
|
||
short *regno_first_uid;
|
||
|
||
/* Indexed by pseudo register number, gives uid of last insn using the reg
|
||
(as of the time reg_scan is called). */
|
||
|
||
short *regno_last_uid;
|
||
|
||
/* Maximum number of parallel sets and clobbers in any insn in this fn.
|
||
Always at least 3, since the combiner could put that many togetherm
|
||
and we want this to remain correct for all the remaining passes. */
|
||
|
||
int max_parallel;
|
||
|
||
void reg_scan_mark_refs ();
|
||
|
||
void
|
||
reg_scan (f, nregs, repeat)
|
||
rtx f;
|
||
int nregs;
|
||
int repeat;
|
||
{
|
||
register rtx insn;
|
||
|
||
if (!repeat)
|
||
regno_first_uid = (short *) oballoc (nregs * sizeof (short));
|
||
bzero (regno_first_uid, nregs * sizeof (short));
|
||
|
||
if (!repeat)
|
||
regno_last_uid = (short *) oballoc (nregs * sizeof (short));
|
||
bzero (regno_last_uid, nregs * sizeof (short));
|
||
|
||
max_parallel = 3;
|
||
|
||
for (insn = f; insn; insn = NEXT_INSN (insn))
|
||
if (GET_CODE (insn) == INSN
|
||
|| GET_CODE (insn) == CALL_INSN
|
||
|| GET_CODE (insn) == JUMP_INSN)
|
||
{
|
||
if (GET_CODE (PATTERN (insn)) == PARALLEL
|
||
&& XVECLEN (PATTERN (insn), 0) > max_parallel)
|
||
max_parallel = XVECLEN (PATTERN (insn), 0);
|
||
reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn));
|
||
}
|
||
}
|
||
|
||
void
|
||
reg_scan_mark_refs (x, uid)
|
||
rtx x;
|
||
int uid;
|
||
{
|
||
register enum rtx_code code = GET_CODE (x);
|
||
|
||
switch (code)
|
||
{
|
||
case CONST_INT:
|
||
case CONST:
|
||
case CONST_DOUBLE:
|
||
case CC0:
|
||
case PC:
|
||
case SYMBOL_REF:
|
||
case LABEL_REF:
|
||
case ADDR_VEC:
|
||
case ADDR_DIFF_VEC:
|
||
return;
|
||
|
||
case REG:
|
||
{
|
||
register int regno = REGNO (x);
|
||
|
||
regno_last_uid[regno] = uid;
|
||
if (regno_first_uid[regno] == 0)
|
||
regno_first_uid[regno] = uid;
|
||
}
|
||
break;
|
||
|
||
default:
|
||
{
|
||
register char *fmt = GET_RTX_FORMAT (code);
|
||
register int i;
|
||
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
||
{
|
||
if (fmt[i] == 'e')
|
||
reg_scan_mark_refs (XEXP (x, i), uid);
|
||
else if (fmt[i] == 'E' && XVEC (x, i) != 0)
|
||
{
|
||
register int j;
|
||
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
||
reg_scan_mark_refs (XVECEXP (x, i, j), uid);
|
||
}
|
||
}
|
||
}
|
||
}
|
||
}
|